From: Stefano Babic <sbabic@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board
Date: Fri, 17 May 2013 18:07:43 +0200 [thread overview]
Message-ID: <519655CF.4070608@denx.de> (raw)
In-Reply-To: <81BA6E5E0BC2344391CABCEE22D1B6D8331523@039-SN1MPN1-003.039d.mgd.msft.net>
On 17/05/2013 17:20, Wang Huan-B18965 wrote:
> Hi, Stefano,
>
Hi Alison,
>>> +void setup_iomux_ddr(void)
>>> +{
>>> + imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); }
>>> +
>>> +void ddr_phy_init(void)
>>> +{
>>> + struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
>>> +
>>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[0]);
>>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[16]);
>>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[32]);
>>> + __raw_writel(PHY_DQ_TIMING, &ddrmr->phy[48]);
>>> +
>>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[1]);
>>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[17]);
>>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[33]);
>>> + __raw_writel(PHY_DQS_TIMING, &ddrmr->phy[49]);
>>> +
>>> + __raw_writel(PHY_CTRL, &ddrmr->phy[2]);
>>> + __raw_writel(PHY_CTRL, &ddrmr->phy[18]);
>>> + __raw_writel(PHY_CTRL, &ddrmr->phy[34]);
>>> + __raw_writel(PHY_CTRL, &ddrmr->phy[50]);
>>> +
>>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[3]);
>>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[19]);
>>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[35]);
>>> + __raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[51]);
>>> +
>>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[4]);
>>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[20]);
>>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[36]);
>>> + __raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[52]);
>>> +
>>
>> Without reference manual, it is difficult to judge. But it is surely
>> difficult to read. What does hide under the magic index of the ddrmr
>> stucture ?
> [Alison Wang] In the reference manual, the registers are named as phy00, phy01, phy02.... cr00, cr01, cr02....
> I think there may be some confusion if I rename the registers.
Then the names of the registers are ok - I wanted only to be sure that
what we read here is what we can find in the RM.
>
>
> BTW, what's your suggestions about the other two patches, [PATCH v2 4/6] and [PATCH v2 5/6]?
> Thanks.
Patches 4/6 and 5/6 are ok for me.
Best regards,
Stefano Babic
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next prev parent reply other threads:[~2013-05-17 16:07 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-14 9:51 [U-Boot] [PATCH v2 0/6] arm: mvf600: Add Freescale Vybrid MVF600 CPU and MVF600TWR board support Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support Alison Wang
2013-05-15 8:13 ` Stefano Babic
2013-05-15 12:09 ` Albert ARIBAUD
2013-05-15 12:24 ` Stefano Babic
2013-05-15 12:39 ` Albert ARIBAUD
2013-05-15 13:20 ` Stefano Babic
[not found] ` <81BA6E5E0BC2344391CABCEE22D1B6D8322144@039-SN1MPN1-002.039d.mgd.msft.net>
2013-05-15 14:23 ` [U-Boot] 答复: " Stefano Babic
2013-05-16 4:00 ` [U-Boot] " Wang Huan-B18965
2013-05-14 9:51 ` [U-Boot] [PATCH v2 2/6] arm: mvf600: Add IOMUX support for Vybrid MVF600 Alison Wang
2013-05-15 8:16 ` Stefano Babic
2013-05-15 13:53 ` Benoît Thébaudeau
2013-05-14 9:51 ` [U-Boot] [PATCH v2 3/6] arm: mvf600: Add FEC " Alison Wang
2013-05-15 8:15 ` Stefano Babic
2013-05-15 14:19 ` Benoît Thébaudeau
2013-05-14 9:51 ` [U-Boot] [PATCH v2 4/6] arm: mvf600: Add watchdog " Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 5/6] arm: mvf600: Add uart " Alison Wang
2013-05-14 9:51 ` [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board Alison Wang
2013-05-15 4:14 ` Shawn Guo
2013-05-15 8:11 ` Wang Huan-B18965
2013-05-15 9:01 ` Stefano Babic
2013-05-17 15:20 ` Wang Huan-B18965
2013-05-17 16:07 ` Stefano Babic [this message]
2013-05-17 16:06 ` Benoît Thébaudeau
2013-05-17 16:57 ` Stefano Babic
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