From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stefano Babic <sbabic@denx.de>
Date: Fri, 17 May 2013 18:07:43 +0200
Subject: [U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for
 Vybrid MVF600TWR board
In-Reply-To: <81BA6E5E0BC2344391CABCEE22D1B6D8331523@039-SN1MPN1-003.039d.mgd.msft.net>
References: <1368525108-2266-1-git-send-email-b18965@freescale.com>
	<1368525108-2266-7-git-send-email-b18965@freescale.com>
	<51934EDC.9090002@denx.de>
	<81BA6E5E0BC2344391CABCEE22D1B6D8331523@039-SN1MPN1-003.039d.mgd.msft.net>
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On 17/05/2013 17:20, Wang Huan-B18965 wrote:
> Hi, Stefano,
> 

Hi Alison,

>>> +void setup_iomux_ddr(void)
>>> +{
>>> +	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); }
>>> +
>>> +void ddr_phy_init(void)
>>> +{
>>> +	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
>>> +
>>> +	__raw_writel(PHY_DQ_TIMING, &ddrmr->phy[0]);
>>> +	__raw_writel(PHY_DQ_TIMING, &ddrmr->phy[16]);
>>> +	__raw_writel(PHY_DQ_TIMING, &ddrmr->phy[32]);
>>> +	__raw_writel(PHY_DQ_TIMING, &ddrmr->phy[48]);
>>> +
>>> +	__raw_writel(PHY_DQS_TIMING, &ddrmr->phy[1]);
>>> +	__raw_writel(PHY_DQS_TIMING, &ddrmr->phy[17]);
>>> +	__raw_writel(PHY_DQS_TIMING, &ddrmr->phy[33]);
>>> +	__raw_writel(PHY_DQS_TIMING, &ddrmr->phy[49]);
>>> +
>>> +	__raw_writel(PHY_CTRL, &ddrmr->phy[2]);
>>> +	__raw_writel(PHY_CTRL, &ddrmr->phy[18]);
>>> +	__raw_writel(PHY_CTRL, &ddrmr->phy[34]);
>>> +	__raw_writel(PHY_CTRL, &ddrmr->phy[50]);
>>> +
>>> +	__raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[3]);
>>> +	__raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[19]);
>>> +	__raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[35]);
>>> +	__raw_writel(PHY_MASTER_CTRL, &ddrmr->phy[51]);
>>> +
>>> +	__raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[4]);
>>> +	__raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[20]);
>>> +	__raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[36]);
>>> +	__raw_writel(PHY_SLAVE_CTRL, &ddrmr->phy[52]);
>>> +
>>
>> Without reference manual, it is difficult to judge. But it is surely
>> difficult to read. What does hide under the magic index of the ddrmr
>> stucture ?
> [Alison Wang] In the reference manual, the registers are named as phy00, phy01, phy02.... cr00, cr01, cr02....
> I think there may be some confusion if I rename the registers.

Then the names of the registers are ok - I wanted only to be sure that
what we read here is what we can find in the RM.


> 
> 
> BTW, what's your suggestions about the other two patches, [PATCH v2 4/6] and [PATCH v2 5/6]?
> Thanks.

Patches 4/6 and 5/6 are ok for me.

Best regards,
Stefano Babic


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