[U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board

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* [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board
@ 2013-05-22 13:57 Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 01/10] MIPS: qemu-malta: add support for emulated MIPS " Gabor Juhos
                   ` (9 more replies)
  0 siblings, 10 replies; 16+ messages in thread
From: Gabor Juhos @ 2013-05-22 13:57 UTC (permalink / raw)
  To: u-boot

This patch set adds initial support for the MIPS Malta CoreLV
board emulated under Qemu.

The changes since the previous version of the series are described in
the individual patches.

The patches are against the master branch of git.denx.de/u-boot.git
tree.

Depends on the following patch:
  'MIPS: fix __raw_* IO accessors'
  http://patchwork.ozlabs.org/patch/222195/

Gabor Juhos (10):
  MIPS: qemu-malta: add support for emulated MIPS Malta board
  MIPS: qemu-malta: add reset support
  MIPS: qemu-malta: enable flash support
  MIPS: import gt64120.h header from Linux
  MIPS: qemu-malta: setup GT64120 registers as done by YAMON
  MIPS: qemu-malta: add PCI support
  net: pcnet: use pci_virt_to_mem to obtain buffer addresses
  MIPS: qemu-malta: bring up ethernet
  MIPS: bootm.c: add YAMON style Linux preparation/jump code
  MIPS: start.S: emulate REVISION register for qemu-malta

 arch/mips/cpu/mips32/start.S     |    8 +-
 arch/mips/include/asm/malta.h    |   23 ++
 arch/mips/lib/bootm.c            |   60 ++++-
 board/qemu-malta/Makefile        |   45 ++++
 board/qemu-malta/lowlevel_init.S |   71 +++++
 board/qemu-malta/qemu-malta.c    |   49 ++++
 boards.cfg                       |    2 +
 drivers/net/pcnet.c              |    2 +-
 drivers/pci/Makefile             |    1 +
 drivers/pci/pci_gt64120.c        |  178 ++++++++++++
 include/configs/qemu-malta.h     |  116 ++++++++
 include/gt64120.h                |  550 ++++++++++++++++++++++++++++++++++++++
 include/pci_gt64120.h            |   19 ++
 13 files changed, 1120 insertions(+), 4 deletions(-)
 create mode 100644 arch/mips/include/asm/malta.h
 create mode 100644 board/qemu-malta/Makefile
 create mode 100644 board/qemu-malta/lowlevel_init.S
 create mode 100644 board/qemu-malta/qemu-malta.c
 create mode 100644 drivers/pci/pci_gt64120.c
 create mode 100644 include/configs/qemu-malta.h
 create mode 100644 include/gt64120.h
 create mode 100644 include/pci_gt64120.h

--
1.7.10

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 01/10] MIPS: qemu-malta: add support for emulated MIPS Malta board
  2013-05-22 13:57 [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
@ 2013-05-22 13:57 ` Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 02/10] MIPS: qemu-malta: add reset support Gabor Juhos
                   ` (8 subsequent siblings)
  9 siblings, 0 replies; 16+ messages in thread
From: Gabor Juhos @ 2013-05-22 13:57 UTC (permalink / raw)
  To: u-boot

Add minimal support for the MIPS Malta CoreLV board
emulated by Qemu. The only supported peripherial is
the UART.

This is enough to boot U-Boot to the command prompt
both in little and big endian mode.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
Changes since v2:
 - rebased against the master branch of git.denx.de/u-boot.git

Changes since v1:
 - remove custom u-boot.lds file
 - rebased against mips/testing

Changes since RFC: ---

Screenshot:

  U-Boot 2013.04-00237-g8321627 (May 21 2013 - 22:29:38)

  Board: MIPS Malta CoreLV (Qemu)
  DRAM:  256 MiB
  Using default environment

  In:    serial
  Out:   serial
  Err:   serial
  qemu-malta # help
  ?       - alias for 'help'
  base    - print or set address offset
  bdinfo  - print Board Info structure
  boot    - boot default, i.e., run 'bootcmd'
  bootd   - boot default, i.e., run 'bootcmd'
  bootm   - boot application image from memory
  cmp     - memory compare
  coninfo - print console devices and information
  cp      - memory copy
  crc32   - checksum calculation
  echo    - echo args to console
  editenv - edit environment variable
  env     - environment handling commands
  go      - start application at address 'addr'
  help    - print command description/usage
  iminfo  - print header information for application image
  imxtract- extract a part of a multi-image
  itest   - return true/false on integer compare
  loop    - infinite loop on address range
  md      - memory display
  mm      - memory modify (auto-incrementing address)
  mw      - memory write (fill)
  nm      - memory modify (constant address)
  printenv- print environment variables
  reset   - Perform RESET of the CPU
  run     - run commands in an environment variable
  setenv  - set environment variables
  sleep   - delay execution for some time
  source  - run script from memory
  version - print monitor, compiler and linker version
  qemu-malta # printenv
  baudrate=115200
  stderr=serial
  stdin=serial
  stdout=serial

  Environment size: 66/65532 bytes
  qemu-malta #
---
 arch/mips/include/asm/malta.h    |   16 ++++++
 board/qemu-malta/Makefile        |   45 +++++++++++++++++
 board/qemu-malta/lowlevel_init.S |   19 +++++++
 board/qemu-malta/qemu-malta.c    |   20 ++++++++
 boards.cfg                       |    2 +
 include/configs/qemu-malta.h     |  104 ++++++++++++++++++++++++++++++++++++++
 6 files changed, 206 insertions(+)
 create mode 100644 arch/mips/include/asm/malta.h
 create mode 100644 board/qemu-malta/Makefile
 create mode 100644 board/qemu-malta/lowlevel_init.S
 create mode 100644 board/qemu-malta/qemu-malta.c
 create mode 100644 include/configs/qemu-malta.h

diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h
new file mode 100644
index 0000000..b215164
--- /dev/null
+++ b/arch/mips/include/asm/malta.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _MIPS_ASM_MALTA_H
+#define _MIPS_ASM_MALTA_H
+
+#define MALTA_IO_PORT_BASE	0x10000000
+
+#define MALTA_UART_BASE		(MALTA_IO_PORT_BASE + 0x3f8)
+
+#endif /* _MIPS_ASM_MALTA_H */
diff --git a/board/qemu-malta/Makefile b/board/qemu-malta/Makefile
new file mode 100644
index 0000000..6251bb8
--- /dev/null
+++ b/board/qemu-malta/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	= $(BOARD).o
+SOBJS	= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	 $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/qemu-malta/lowlevel_init.S b/board/qemu-malta/lowlevel_init.S
new file mode 100644
index 0000000..c5c5bd9
--- /dev/null
+++ b/board/qemu-malta/lowlevel_init.S
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/regdef.h>
+
+	.text
+	.set noreorder
+	.set mips32
+
+	.globl	lowlevel_init
+lowlevel_init:
+
+	jr	ra
+	 nop
diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c
new file mode 100644
index 0000000..9ba711d
--- /dev/null
+++ b/board/qemu-malta/qemu-malta.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+phys_size_t initdram(int board_type)
+{
+	return CONFIG_SYS_MEM_SIZE;
+}
+
+int checkboard(void)
+{
+	puts("Board: MIPS Malta CoreLV (Qemu)\n");
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 05318a1..cae9b28 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -451,6 +451,8 @@ qemu_mips                    mips        mips32      qemu-mips           -
 qemu_mipsel                  mips        mips32      qemu-mips           -              -           qemu-mips:SYS_LITTLE_ENDIAN
 qemu_mips64                  mips        mips64      qemu-mips           -              -           qemu-mips64:SYS_BIG_ENDIAN
 qemu_mips64el                mips        mips64      qemu-mips           -              -           qemu-mips64:SYS_LITTLE_ENDIAN
+qemu_malta                   mips        mips32      qemu-malta          -              -           qemu-malta:MIPS32,SYS_BIG_ENDIAN
+qemu_maltael                 mips        mips32      qemu-malta          -              -           qemu-malta:MIPS32,SYS_LITTLE_ENDIAN
 vct_platinum                 mips        mips32      vct                 micronas       -           vct:VCT_PLATINUM
 vct_platinumavc              mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
diff --git a/include/configs/qemu-malta.h b/include/configs/qemu-malta.h
new file mode 100644
index 0000000..c72c5dd
--- /dev/null
+++ b/include/configs/qemu-malta.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _QEMU_MALTA_CONFIG_H
+#define _QEMU_MALTA_CONFIG_H
+
+#include <asm/addrspace.h>
+#include <asm/malta.h>
+
+/*
+ * System configuration
+ */
+#define CONFIG_QEMU_MALTA
+
+/*
+ * CPU Configuration
+ */
+#define CONFIG_SYS_MHZ			250	/* arbitrary value */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_SYS_DCACHE_SIZE		16384	/* arbitrary value */
+#define CONFIG_SYS_ICACHE_SIZE		16384	/* arbitrary value */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* arbitrary value */
+
+#define CONFIG_SWAP_IO_SPACE
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_TEXT_BASE		0xbfc00000 /* Rom version */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000 /* Cached addr */
+#define CONFIG_SYS_MEM_SIZE		(256 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+#define CONFIG_SYS_LOAD_ADDR		0x81000000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
+
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+
+/*
+ * Console configuration
+ */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT		"qemu-maltael # "
+#else
+#define CONFIG_SYS_PROMPT		"qemu-malta # "
+#endif
+
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Serial driver
+ */
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		115200
+#define CONFIG_SYS_NS16550_COM1		CKSEG1ADDR(MALTA_UART_BASE)
+#define CONFIG_CONS_INDEX		1
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			0x10000
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Commands
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_SYS_LONGHELP		/* verbose help, undef to save memory */
+
+#endif /* _QEMU_MALTA_CONFIG_H */
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 02/10] MIPS: qemu-malta: add reset support
  2013-05-22 13:57 [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 01/10] MIPS: qemu-malta: add support for emulated MIPS " Gabor Juhos
@ 2013-05-22 13:57 ` Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 03/10] MIPS: qemu-malta: enable flash support Gabor Juhos
                   ` (7 subsequent siblings)
  9 siblings, 0 replies; 16+ messages in thread
From: Gabor Juhos @ 2013-05-22 13:57 UTC (permalink / raw)
  To: u-boot

The MIPS Malta board has a SOFTRES register. Writing a
magic value into that register initiates a board reset.

Use this feature to implement reset support.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
Changes since v2:
 - don't use le32_to_cpu accessor, it is not needed because
   the __raw_* IO accessors has been fixed mainline
 - rebased against the master branch of git.denx.de/u-boot.git

Changes since v1:
 - rebased against mips/testing

Changes since RFC: ---

Screenshot:

  U-Boot 2013.04-00238-g0320f0c (May 21 2013 - 22:31:20)

  Board: MIPS Malta CoreLV (Qemu)
  DRAM:  256 MiB
  Using default environment

  In:    serial
  Out:   serial
  Err:   serial
  qemu-malta # reset

  U-Boot 2013.04-00238-g0320f0c (May 21 2013 - 22:31:20)

  Board: MIPS Malta CoreLV (Qemu)
  DRAM:  256 MiB
  Using default environment

  In:    serial
  Out:   serial
  Err:   serial
  qemu-malta #
---
 arch/mips/include/asm/malta.h |    3 +++
 board/qemu-malta/qemu-malta.c |   11 +++++++++++
 2 files changed, 14 insertions(+)

diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h
index b215164..f2bbf0f 100644
--- a/arch/mips/include/asm/malta.h
+++ b/arch/mips/include/asm/malta.h
@@ -13,4 +13,7 @@
 
 #define MALTA_UART_BASE		(MALTA_IO_PORT_BASE + 0x3f8)
 
+#define MALTA_RESET_BASE	0x1f000500
+#define GORESET			0x42
+
 #endif /* _MIPS_ASM_MALTA_H */
diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c
index 9ba711d..449da9c 100644
--- a/board/qemu-malta/qemu-malta.c
+++ b/board/qemu-malta/qemu-malta.c
@@ -8,6 +8,9 @@
 
 #include <common.h>
 
+#include <asm/io.h>
+#include <asm/malta.h>
+
 phys_size_t initdram(int board_type)
 {
 	return CONFIG_SYS_MEM_SIZE;
@@ -18,3 +21,11 @@ int checkboard(void)
 	puts("Board: MIPS Malta CoreLV (Qemu)\n");
 	return 0;
 }
+
+void _machine_restart(void)
+{
+	void __iomem *reset_base;
+
+	reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
+	__raw_writel(GORESET, reset_base);
+}
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 03/10] MIPS: qemu-malta: enable flash support
  2013-05-22 13:57 [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 01/10] MIPS: qemu-malta: add support for emulated MIPS " Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 02/10] MIPS: qemu-malta: add reset support Gabor Juhos
@ 2013-05-22 13:57 ` Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 04/10] MIPS: import gt64120.h header from Linux Gabor Juhos
                   ` (6 subsequent siblings)
  9 siblings, 0 replies; 16+ messages in thread
From: Gabor Juhos @ 2013-05-22 13:57 UTC (permalink / raw)
  To: u-boot

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
Changes since v2:
 - remove CONFIG_SYS_WRITE_SWAPPED_DATA option, it is not
   needed since the __raw_* IO accessors has been fixed.
 - rebased against the master branch of git.denx.de/u-boot.git

Changes since v1:
 - rebased against mips/testing

Changes since RFC: ---

Screenshot:

  U-Boot 2013.04-00239-gea7c438 (May 22 2013 - 13:03:22)

  Board: MIPS Malta CoreLV (Qemu)
  DRAM:  256 MiB
  pflash_write: Unimplemented flash cmd sequence (offset 0000000000000000, wcycle 0x0 cmd 0x0 value 0xf0)
  Flash: 4 MiB
  Using default environment

  In:    serial
  Out:   serial
  Err:   serial
  qemu-malta # flinfo

  Bank # 1: CFI conformant flash (32 x 32)  Size: 4 MB in 64 Sectors
    Intel Extended command set, Manufacturer ID: 0x00, Device ID: 0x00
    Erase timeout: 16384 ms, write timeout: 3 ms
    Buffer write timeout: 3 ms, buffer size: 2048 bytes

    Sector Start Addresses:
    BFC00000   RO   BFC10000   RO   BFC20000        BFC30000        BFC40000
    BFC50000        BFC60000        BFC70000        BFC80000        BFC90000
    BFCA0000        BFCB0000        BFCC0000        BFCD0000        BFCE0000
    BFCF0000        BFD00000        BFD10000        BFD20000        BFD30000
    BFD40000        BFD50000        BFD60000        BFD70000        BFD80000
    BFD90000        BFDA0000        BFDB0000        BFDC0000        BFDD0000
    BFDE0000        BFDF0000        BFE00000        BFE10000        BFE20000
    BFE30000        BFE40000        BFE50000        BFE60000        BFE70000
    BFE80000        BFE90000        BFEA0000        BFEB0000        BFEC0000
    BFED0000        BFEE0000        BFEF0000        BFF00000        BFF10000
    BFF20000        BFF30000        BFF40000        BFF50000        BFF60000
    BFF70000        BFF80000        BFF90000        BFFA0000        BFFB0000
    BFFC0000        BFFD0000        BFFE0000        BFFF0000
  qemu-malta #
---
 arch/mips/include/asm/malta.h |    2 ++
 include/configs/qemu-malta.h  |    9 +++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h
index f2bbf0f..ab951e6 100644
--- a/arch/mips/include/asm/malta.h
+++ b/arch/mips/include/asm/malta.h
@@ -16,4 +16,6 @@
 #define MALTA_RESET_BASE	0x1f000500
 #define GORESET			0x42
 
+#define MALTA_FLASH_BASE	0x1fc00000
+
 #endif /* _MIPS_ASM_MALTA_H */
diff --git a/include/configs/qemu-malta.h b/include/configs/qemu-malta.h
index c72c5dd..436bb49 100644
--- a/include/configs/qemu-malta.h
+++ b/include/configs/qemu-malta.h
@@ -34,7 +34,7 @@
  * Memory map
  */
 #define CONFIG_SYS_TEXT_BASE		0xbfc00000 /* Rom version */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
 #define CONFIG_SYS_SDRAM_BASE		0x80000000 /* Cached addr */
 #define CONFIG_SYS_MEM_SIZE		(256 * 1024 * 1024)
@@ -86,7 +86,12 @@
 /*
  * Flash configuration
  */
-#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_BASE		(KSEG1 | MALTA_FLASH_BASE)
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /*
  * Commands
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 04/10] MIPS: import gt64120.h header from Linux
  2013-05-22 13:57 [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
                   ` (2 preceding siblings ...)
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 03/10] MIPS: qemu-malta: enable flash support Gabor Juhos
@ 2013-05-22 13:57 ` Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 05/10] MIPS: qemu-malta: setup GT64120 registers as done by YAMON Gabor Juhos
                   ` (5 subsequent siblings)
  9 siblings, 0 replies; 16+ messages in thread
From: Gabor Juhos @ 2013-05-22 13:57 UTC (permalink / raw)
  To: u-boot

The Linux specific register access macros, the
extern function declarations and the UL suffixes
has been removed.

The header file will be used for the qemu-malta
board.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
Changes since v2:
 - use the header file from Linux 3.10-rc2 instead of 3.8-rc3
 - move the header file from 'arch/mips/include/asm' to 'include'
 - rebased against the master branch of git.denx.de/u-boot.git

Changes since v1:
 - rebased against mips/testing

Changes since RFC: ---
---
 include/gt64120.h |  550 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 550 insertions(+)
 create mode 100644 include/gt64120.h

diff --git a/include/gt64120.h b/include/gt64120.h
new file mode 100644
index 0000000..c0accc6
--- /dev/null
+++ b/include/gt64120.h
@@ -0,0 +1,550 @@
+/*
+ * Copyright (C) 2000, 2004, 2005  MIPS Technologies, Inc.
+ *	All rights reserved.
+ *	Authors: Carsten Langgaard <carstenl@mips.com>
+ *		 Maciej W. Rozycki <macro@mips.com>
+ * Copyright (C) 2005 Ralf Baechle (ralf at linux-mips.org)
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef _ASM_GT64120_H
+#define _ASM_GT64120_H
+
+#define MSK(n)			((1 << (n)) - 1)
+
+/*
+ *  Register offset addresses
+ */
+/* CPU Configuration.  */
+#define GT_CPU_OFS		0x000
+
+#define GT_MULTI_OFS		0x120
+
+/* CPU Address Decode.	*/
+#define GT_SCS10LD_OFS		0x008
+#define GT_SCS10HD_OFS		0x010
+#define GT_SCS32LD_OFS		0x018
+#define GT_SCS32HD_OFS		0x020
+#define GT_CS20LD_OFS		0x028
+#define GT_CS20HD_OFS		0x030
+#define GT_CS3BOOTLD_OFS	0x038
+#define GT_CS3BOOTHD_OFS	0x040
+#define GT_PCI0IOLD_OFS		0x048
+#define GT_PCI0IOHD_OFS		0x050
+#define GT_PCI0M0LD_OFS		0x058
+#define GT_PCI0M0HD_OFS		0x060
+#define GT_ISD_OFS		0x068
+
+#define GT_PCI0M1LD_OFS		0x080
+#define GT_PCI0M1HD_OFS		0x088
+#define GT_PCI1IOLD_OFS		0x090
+#define GT_PCI1IOHD_OFS		0x098
+#define GT_PCI1M0LD_OFS		0x0a0
+#define GT_PCI1M0HD_OFS		0x0a8
+#define GT_PCI1M1LD_OFS		0x0b0
+#define GT_PCI1M1HD_OFS		0x0b8
+#define GT_PCI1M1LD_OFS		0x0b0
+#define GT_PCI1M1HD_OFS		0x0b8
+
+#define GT_SCS10AR_OFS		0x0d0
+#define GT_SCS32AR_OFS		0x0d8
+#define GT_CS20R_OFS		0x0e0
+#define GT_CS3BOOTR_OFS		0x0e8
+
+#define GT_PCI0IOREMAP_OFS	0x0f0
+#define GT_PCI0M0REMAP_OFS	0x0f8
+#define GT_PCI0M1REMAP_OFS	0x100
+#define GT_PCI1IOREMAP_OFS	0x108
+#define GT_PCI1M0REMAP_OFS	0x110
+#define GT_PCI1M1REMAP_OFS	0x118
+
+/* CPU Error Report.  */
+#define GT_CPUERR_ADDRLO_OFS	0x070
+#define GT_CPUERR_ADDRHI_OFS	0x078
+
+#define GT_CPUERR_DATALO_OFS	0x128			/* GT-64120A only  */
+#define GT_CPUERR_DATAHI_OFS	0x130			/* GT-64120A only  */
+#define GT_CPUERR_PARITY_OFS	0x138			/* GT-64120A only  */
+
+/* CPU Sync Barrier.  */
+#define GT_PCI0SYNC_OFS		0x0c0
+#define GT_PCI1SYNC_OFS		0x0c8
+
+/* SDRAM and Device Address Decode.  */
+#define GT_SCS0LD_OFS		0x400
+#define GT_SCS0HD_OFS		0x404
+#define GT_SCS1LD_OFS		0x408
+#define GT_SCS1HD_OFS		0x40c
+#define GT_SCS2LD_OFS		0x410
+#define GT_SCS2HD_OFS		0x414
+#define GT_SCS3LD_OFS		0x418
+#define GT_SCS3HD_OFS		0x41c
+#define GT_CS0LD_OFS		0x420
+#define GT_CS0HD_OFS		0x424
+#define GT_CS1LD_OFS		0x428
+#define GT_CS1HD_OFS		0x42c
+#define GT_CS2LD_OFS		0x430
+#define GT_CS2HD_OFS		0x434
+#define GT_CS3LD_OFS		0x438
+#define GT_CS3HD_OFS		0x43c
+#define GT_BOOTLD_OFS		0x440
+#define GT_BOOTHD_OFS		0x444
+
+#define GT_ADERR_OFS		0x470
+
+/* SDRAM Configuration.	 */
+#define GT_SDRAM_CFG_OFS	0x448
+
+#define GT_SDRAM_OPMODE_OFS	0x474
+#define GT_SDRAM_BM_OFS		0x478
+#define GT_SDRAM_ADDRDECODE_OFS 0x47c
+
+/* SDRAM Parameters.  */
+#define GT_SDRAM_B0_OFS		0x44c
+#define GT_SDRAM_B1_OFS		0x450
+#define GT_SDRAM_B2_OFS		0x454
+#define GT_SDRAM_B3_OFS		0x458
+
+/* Device Parameters.  */
+#define GT_DEV_B0_OFS		0x45c
+#define GT_DEV_B1_OFS		0x460
+#define GT_DEV_B2_OFS		0x464
+#define GT_DEV_B3_OFS		0x468
+#define GT_DEV_BOOT_OFS		0x46c
+
+/* ECC.	 */
+#define GT_ECC_ERRDATALO	0x480			/* GT-64120A only  */
+#define GT_ECC_ERRDATAHI	0x484			/* GT-64120A only  */
+#define GT_ECC_MEM		0x488			/* GT-64120A only  */
+#define GT_ECC_CALC		0x48c			/* GT-64120A only  */
+#define GT_ECC_ERRADDR		0x490			/* GT-64120A only  */
+
+/* DMA Record.	*/
+#define GT_DMA0_CNT_OFS		0x800
+#define GT_DMA1_CNT_OFS		0x804
+#define GT_DMA2_CNT_OFS		0x808
+#define GT_DMA3_CNT_OFS		0x80c
+#define GT_DMA0_SA_OFS		0x810
+#define GT_DMA1_SA_OFS		0x814
+#define GT_DMA2_SA_OFS		0x818
+#define GT_DMA3_SA_OFS		0x81c
+#define GT_DMA0_DA_OFS		0x820
+#define GT_DMA1_DA_OFS		0x824
+#define GT_DMA2_DA_OFS		0x828
+#define GT_DMA3_DA_OFS		0x82c
+#define GT_DMA0_NEXT_OFS	0x830
+#define GT_DMA1_NEXT_OFS	0x834
+#define GT_DMA2_NEXT_OFS	0x838
+#define GT_DMA3_NEXT_OFS	0x83c
+
+#define GT_DMA0_CUR_OFS		0x870
+#define GT_DMA1_CUR_OFS		0x874
+#define GT_DMA2_CUR_OFS		0x878
+#define GT_DMA3_CUR_OFS		0x87c
+
+/* DMA Channel Control.	 */
+#define GT_DMA0_CTRL_OFS	0x840
+#define GT_DMA1_CTRL_OFS	0x844
+#define GT_DMA2_CTRL_OFS	0x848
+#define GT_DMA3_CTRL_OFS	0x84c
+
+/* DMA Arbiter.	 */
+#define GT_DMA_ARB_OFS		0x860
+
+/* Timer/Counter.  */
+#define GT_TC0_OFS		0x850
+#define GT_TC1_OFS		0x854
+#define GT_TC2_OFS		0x858
+#define GT_TC3_OFS		0x85c
+
+#define GT_TC_CONTROL_OFS	0x864
+
+/* PCI Internal.  */
+#define GT_PCI0_CMD_OFS		0xc00
+#define GT_PCI0_TOR_OFS		0xc04
+#define GT_PCI0_BS_SCS10_OFS	0xc08
+#define GT_PCI0_BS_SCS32_OFS	0xc0c
+#define GT_PCI0_BS_CS20_OFS	0xc10
+#define GT_PCI0_BS_CS3BT_OFS	0xc14
+
+#define GT_PCI1_IACK_OFS	0xc30
+#define GT_PCI0_IACK_OFS	0xc34
+
+#define GT_PCI0_BARE_OFS	0xc3c
+#define GT_PCI0_PREFMBR_OFS	0xc40
+
+#define GT_PCI0_SCS10_BAR_OFS	0xc48
+#define GT_PCI0_SCS32_BAR_OFS	0xc4c
+#define GT_PCI0_CS20_BAR_OFS	0xc50
+#define GT_PCI0_CS3BT_BAR_OFS	0xc54
+#define GT_PCI0_SSCS10_BAR_OFS	0xc58
+#define GT_PCI0_SSCS32_BAR_OFS	0xc5c
+
+#define GT_PCI0_SCS3BT_BAR_OFS	0xc64
+
+#define GT_PCI1_CMD_OFS		0xc80
+#define GT_PCI1_TOR_OFS		0xc84
+#define GT_PCI1_BS_SCS10_OFS	0xc88
+#define GT_PCI1_BS_SCS32_OFS	0xc8c
+#define GT_PCI1_BS_CS20_OFS	0xc90
+#define GT_PCI1_BS_CS3BT_OFS	0xc94
+
+#define GT_PCI1_BARE_OFS	0xcbc
+#define GT_PCI1_PREFMBR_OFS	0xcc0
+
+#define GT_PCI1_SCS10_BAR_OFS	0xcc8
+#define GT_PCI1_SCS32_BAR_OFS	0xccc
+#define GT_PCI1_CS20_BAR_OFS	0xcd0
+#define GT_PCI1_CS3BT_BAR_OFS	0xcd4
+#define GT_PCI1_SSCS10_BAR_OFS	0xcd8
+#define GT_PCI1_SSCS32_BAR_OFS	0xcdc
+
+#define GT_PCI1_SCS3BT_BAR_OFS	0xce4
+
+#define GT_PCI1_CFGADDR_OFS	0xcf0
+#define GT_PCI1_CFGDATA_OFS	0xcf4
+#define GT_PCI0_CFGADDR_OFS	0xcf8
+#define GT_PCI0_CFGDATA_OFS	0xcfc
+
+/* Interrupts.	*/
+#define GT_INTRCAUSE_OFS	0xc18
+#define GT_INTRMASK_OFS		0xc1c
+
+#define GT_PCI0_ICMASK_OFS	0xc24
+#define GT_PCI0_SERR0MASK_OFS	0xc28
+
+#define GT_CPU_INTSEL_OFS	0xc70
+#define GT_PCI0_INTSEL_OFS	0xc74
+
+#define GT_HINTRCAUSE_OFS	0xc98
+#define GT_HINTRMASK_OFS	0xc9c
+
+#define GT_PCI0_HICMASK_OFS	0xca4
+#define GT_PCI1_SERR1MASK_OFS	0xca8
+
+
+/*
+ * I2O Support Registers
+ */
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x01c
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE		0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE		0x02c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE			0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE		0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x06c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x07c
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1c10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1c14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1c18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1c1c
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1c20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1c24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1c28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1c2c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1c30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1c34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1c40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1c44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE			0x1c50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE		0x1c54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c6c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c7c
+
+/*
+ *  Register encodings
+ */
+#define GT_CPU_ENDIAN_SHF	12
+#define GT_CPU_ENDIAN_MSK	(MSK(1) << GT_CPU_ENDIAN_SHF)
+#define GT_CPU_ENDIAN_BIT	GT_CPU_ENDIAN_MSK
+#define GT_CPU_WR_SHF		16
+#define GT_CPU_WR_MSK		(MSK(1) << GT_CPU_WR_SHF)
+#define GT_CPU_WR_BIT		GT_CPU_WR_MSK
+#define GT_CPU_WR_DXDXDXDX	0
+#define GT_CPU_WR_DDDD		1
+
+
+#define GT_PCI_DCRM_SHF		21
+#define GT_PCI_LD_SHF		0
+#define GT_PCI_LD_MSK		(MSK(15) << GT_PCI_LD_SHF)
+#define GT_PCI_HD_SHF		0
+#define GT_PCI_HD_MSK		(MSK(7) << GT_PCI_HD_SHF)
+#define GT_PCI_REMAP_SHF	0
+#define GT_PCI_REMAP_MSK	(MSK(11) << GT_PCI_REMAP_SHF)
+
+
+#define GT_CFGADDR_CFGEN_SHF	31
+#define GT_CFGADDR_CFGEN_MSK	(MSK(1) << GT_CFGADDR_CFGEN_SHF)
+#define GT_CFGADDR_CFGEN_BIT	GT_CFGADDR_CFGEN_MSK
+
+#define GT_CFGADDR_BUSNUM_SHF	16
+#define GT_CFGADDR_BUSNUM_MSK	(MSK(8) << GT_CFGADDR_BUSNUM_SHF)
+
+#define GT_CFGADDR_DEVNUM_SHF	11
+#define GT_CFGADDR_DEVNUM_MSK	(MSK(5) << GT_CFGADDR_DEVNUM_SHF)
+
+#define GT_CFGADDR_FUNCNUM_SHF	8
+#define GT_CFGADDR_FUNCNUM_MSK	(MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
+
+#define GT_CFGADDR_REGNUM_SHF	2
+#define GT_CFGADDR_REGNUM_MSK	(MSK(6) << GT_CFGADDR_REGNUM_SHF)
+
+
+#define GT_SDRAM_BM_ORDER_SHF	2
+#define GT_SDRAM_BM_ORDER_MSK	(MSK(1) << GT_SDRAM_BM_ORDER_SHF)
+#define GT_SDRAM_BM_ORDER_BIT	GT_SDRAM_BM_ORDER_MSK
+#define GT_SDRAM_BM_ORDER_SUB	1
+#define GT_SDRAM_BM_ORDER_LIN	0
+
+#define GT_SDRAM_BM_RSVD_ALL1	0xffb
+
+
+#define GT_SDRAM_ADDRDECODE_ADDR_SHF	0
+#define GT_SDRAM_ADDRDECODE_ADDR_MSK	(MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
+#define GT_SDRAM_ADDRDECODE_ADDR_0	0
+#define GT_SDRAM_ADDRDECODE_ADDR_1	1
+#define GT_SDRAM_ADDRDECODE_ADDR_2	2
+#define GT_SDRAM_ADDRDECODE_ADDR_3	3
+#define GT_SDRAM_ADDRDECODE_ADDR_4	4
+#define GT_SDRAM_ADDRDECODE_ADDR_5	5
+#define GT_SDRAM_ADDRDECODE_ADDR_6	6
+#define GT_SDRAM_ADDRDECODE_ADDR_7	7
+
+
+#define GT_SDRAM_B0_CASLAT_SHF		0
+#define GT_SDRAM_B0_CASLAT_MSK		(MSK(2) << GT_SDRAM_B0__SHF)
+#define GT_SDRAM_B0_CASLAT_2		1
+#define GT_SDRAM_B0_CASLAT_3		2
+
+#define GT_SDRAM_B0_FTDIS_SHF		2
+#define GT_SDRAM_B0_FTDIS_MSK		(MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
+#define GT_SDRAM_B0_FTDIS_BIT		GT_SDRAM_B0_FTDIS_MSK
+
+#define GT_SDRAM_B0_SRASPRCHG_SHF	3
+#define GT_SDRAM_B0_SRASPRCHG_MSK	(MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
+#define GT_SDRAM_B0_SRASPRCHG_BIT	GT_SDRAM_B0_SRASPRCHG_MSK
+#define GT_SDRAM_B0_SRASPRCHG_2		0
+#define GT_SDRAM_B0_SRASPRCHG_3		1
+
+#define GT_SDRAM_B0_B0COMPAB_SHF	4
+#define GT_SDRAM_B0_B0COMPAB_MSK	(MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
+#define GT_SDRAM_B0_B0COMPAB_BIT	GT_SDRAM_B0_B0COMPAB_MSK
+
+#define GT_SDRAM_B0_64BITINT_SHF	5
+#define GT_SDRAM_B0_64BITINT_MSK	(MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
+#define GT_SDRAM_B0_64BITINT_BIT	GT_SDRAM_B0_64BITINT_MSK
+#define GT_SDRAM_B0_64BITINT_2		0
+#define GT_SDRAM_B0_64BITINT_4		1
+
+#define GT_SDRAM_B0_BW_SHF		6
+#define GT_SDRAM_B0_BW_MSK		(MSK(1) << GT_SDRAM_B0_BW_SHF)
+#define GT_SDRAM_B0_BW_BIT		GT_SDRAM_B0_BW_MSK
+#define GT_SDRAM_B0_BW_32		0
+#define GT_SDRAM_B0_BW_64		1
+
+#define GT_SDRAM_B0_BLODD_SHF		7
+#define GT_SDRAM_B0_BLODD_MSK		(MSK(1) << GT_SDRAM_B0_BLODD_SHF)
+#define GT_SDRAM_B0_BLODD_BIT		GT_SDRAM_B0_BLODD_MSK
+
+#define GT_SDRAM_B0_PAR_SHF		8
+#define GT_SDRAM_B0_PAR_MSK		(MSK(1) << GT_SDRAM_B0_PAR_SHF)
+#define GT_SDRAM_B0_PAR_BIT		GT_SDRAM_B0_PAR_MSK
+
+#define GT_SDRAM_B0_BYPASS_SHF		9
+#define GT_SDRAM_B0_BYPASS_MSK		(MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
+#define GT_SDRAM_B0_BYPASS_BIT		GT_SDRAM_B0_BYPASS_MSK
+
+#define GT_SDRAM_B0_SRAS2SCAS_SHF	10
+#define GT_SDRAM_B0_SRAS2SCAS_MSK	(MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
+#define GT_SDRAM_B0_SRAS2SCAS_BIT	GT_SDRAM_B0_SRAS2SCAS_MSK
+#define GT_SDRAM_B0_SRAS2SCAS_2		0
+#define GT_SDRAM_B0_SRAS2SCAS_3		1
+
+#define GT_SDRAM_B0_SIZE_SHF		11
+#define GT_SDRAM_B0_SIZE_MSK		(MSK(1) << GT_SDRAM_B0_SIZE_SHF)
+#define GT_SDRAM_B0_SIZE_BIT		GT_SDRAM_B0_SIZE_MSK
+#define GT_SDRAM_B0_SIZE_16M		0
+#define GT_SDRAM_B0_SIZE_64M		1
+
+#define GT_SDRAM_B0_EXTPAR_SHF		12
+#define GT_SDRAM_B0_EXTPAR_MSK		(MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
+#define GT_SDRAM_B0_EXTPAR_BIT		GT_SDRAM_B0_EXTPAR_MSK
+
+#define GT_SDRAM_B0_BLEN_SHF		13
+#define GT_SDRAM_B0_BLEN_MSK		(MSK(1) << GT_SDRAM_B0_BLEN_SHF)
+#define GT_SDRAM_B0_BLEN_BIT		GT_SDRAM_B0_BLEN_MSK
+#define GT_SDRAM_B0_BLEN_8		0
+#define GT_SDRAM_B0_BLEN_4		1
+
+
+#define GT_SDRAM_CFG_REFINT_SHF		0
+#define GT_SDRAM_CFG_REFINT_MSK		(MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
+
+#define GT_SDRAM_CFG_NINTERLEAVE_SHF	14
+#define GT_SDRAM_CFG_NINTERLEAVE_MSK	(MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
+#define GT_SDRAM_CFG_NINTERLEAVE_BIT	GT_SDRAM_CFG_NINTERLEAVE_MSK
+
+#define GT_SDRAM_CFG_RMW_SHF		15
+#define GT_SDRAM_CFG_RMW_MSK		(MSK(1) << GT_SDRAM_CFG_RMW_SHF)
+#define GT_SDRAM_CFG_RMW_BIT		GT_SDRAM_CFG_RMW_MSK
+
+#define GT_SDRAM_CFG_NONSTAGREF_SHF	16
+#define GT_SDRAM_CFG_NONSTAGREF_MSK	(MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
+#define GT_SDRAM_CFG_NONSTAGREF_BIT	GT_SDRAM_CFG_NONSTAGREF_MSK
+
+#define GT_SDRAM_CFG_DUPCNTL_SHF	19
+#define GT_SDRAM_CFG_DUPCNTL_MSK	(MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
+#define GT_SDRAM_CFG_DUPCNTL_BIT	GT_SDRAM_CFG_DUPCNTL_MSK
+
+#define GT_SDRAM_CFG_DUPBA_SHF		20
+#define GT_SDRAM_CFG_DUPBA_MSK		(MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
+#define GT_SDRAM_CFG_DUPBA_BIT		GT_SDRAM_CFG_DUPBA_MSK
+
+#define GT_SDRAM_CFG_DUPEOT0_SHF	21
+#define GT_SDRAM_CFG_DUPEOT0_MSK	(MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
+#define GT_SDRAM_CFG_DUPEOT0_BIT	GT_SDRAM_CFG_DUPEOT0_MSK
+
+#define GT_SDRAM_CFG_DUPEOT1_SHF	22
+#define GT_SDRAM_CFG_DUPEOT1_MSK	(MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
+#define GT_SDRAM_CFG_DUPEOT1_BIT	GT_SDRAM_CFG_DUPEOT1_MSK
+
+#define GT_SDRAM_OPMODE_OP_SHF		0
+#define GT_SDRAM_OPMODE_OP_MSK		(MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
+#define GT_SDRAM_OPMODE_OP_NORMAL	0
+#define GT_SDRAM_OPMODE_OP_NOP		1
+#define GT_SDRAM_OPMODE_OP_PRCHG	2
+#define GT_SDRAM_OPMODE_OP_MODE		3
+#define GT_SDRAM_OPMODE_OP_CBR		4
+
+#define GT_TC_CONTROL_ENTC0_SHF		0
+#define GT_TC_CONTROL_ENTC0_MSK		(MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
+#define GT_TC_CONTROL_ENTC0_BIT		GT_TC_CONTROL_ENTC0_MSK
+#define GT_TC_CONTROL_SELTC0_SHF	1
+#define GT_TC_CONTROL_SELTC0_MSK	(MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
+#define GT_TC_CONTROL_SELTC0_BIT	GT_TC_CONTROL_SELTC0_MSK
+
+
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF	0
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK	\
+	(MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT	GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_SWSCS32DIS_SHF	1
+#define GT_PCI0_BARE_SWSCS32DIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
+#define GT_PCI0_BARE_SWSCS32DIS_BIT	GT_PCI0_BARE_SWSCS32DIS_MSK
+
+#define GT_PCI0_BARE_SWSCS10DIS_SHF	2
+#define GT_PCI0_BARE_SWSCS10DIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
+#define GT_PCI0_BARE_SWSCS10DIS_BIT	GT_PCI0_BARE_SWSCS10DIS_MSK
+
+#define GT_PCI0_BARE_INTIODIS_SHF	3
+#define GT_PCI0_BARE_INTIODIS_MSK	(MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
+#define GT_PCI0_BARE_INTIODIS_BIT	GT_PCI0_BARE_INTIODIS_MSK
+
+#define GT_PCI0_BARE_INTMEMDIS_SHF	4
+#define GT_PCI0_BARE_INTMEMDIS_MSK	(MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
+#define GT_PCI0_BARE_INTMEMDIS_BIT	GT_PCI0_BARE_INTMEMDIS_MSK
+
+#define GT_PCI0_BARE_CS3BOOTDIS_SHF	5
+#define GT_PCI0_BARE_CS3BOOTDIS_MSK	(MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_CS3BOOTDIS_BIT	GT_PCI0_BARE_CS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_CS20DIS_SHF	6
+#define GT_PCI0_BARE_CS20DIS_MSK	(MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
+#define GT_PCI0_BARE_CS20DIS_BIT	GT_PCI0_BARE_CS20DIS_MSK
+
+#define GT_PCI0_BARE_SCS32DIS_SHF	7
+#define GT_PCI0_BARE_SCS32DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
+#define GT_PCI0_BARE_SCS32DIS_BIT	GT_PCI0_BARE_SCS32DIS_MSK
+
+#define GT_PCI0_BARE_SCS10DIS_SHF	8
+#define GT_PCI0_BARE_SCS10DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
+#define GT_PCI0_BARE_SCS10DIS_BIT	GT_PCI0_BARE_SCS10DIS_MSK
+
+
+#define GT_INTRCAUSE_MASABORT0_SHF	18
+#define GT_INTRCAUSE_MASABORT0_MSK	(MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
+#define GT_INTRCAUSE_MASABORT0_BIT	GT_INTRCAUSE_MASABORT0_MSK
+
+#define GT_INTRCAUSE_TARABORT0_SHF	19
+#define GT_INTRCAUSE_TARABORT0_MSK	(MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
+#define GT_INTRCAUSE_TARABORT0_BIT	GT_INTRCAUSE_TARABORT0_MSK
+
+
+#define GT_PCI0_CFGADDR_REGNUM_SHF	2
+#define GT_PCI0_CFGADDR_REGNUM_MSK	(MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
+#define GT_PCI0_CFGADDR_FUNCTNUM_SHF	8
+#define GT_PCI0_CFGADDR_FUNCTNUM_MSK	(MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
+#define GT_PCI0_CFGADDR_DEVNUM_SHF	11
+#define GT_PCI0_CFGADDR_DEVNUM_MSK	(MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
+#define GT_PCI0_CFGADDR_BUSNUM_SHF	16
+#define GT_PCI0_CFGADDR_BUSNUM_MSK	(MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_SHF	31
+#define GT_PCI0_CFGADDR_CONFIGEN_MSK	(MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_BIT	GT_PCI0_CFGADDR_CONFIGEN_MSK
+
+#define GT_PCI0_CMD_MBYTESWAP_SHF	0
+#define GT_PCI0_CMD_MBYTESWAP_MSK	(MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
+#define GT_PCI0_CMD_MBYTESWAP_BIT	GT_PCI0_CMD_MBYTESWAP_MSK
+#define GT_PCI0_CMD_MWORDSWAP_SHF	10
+#define GT_PCI0_CMD_MWORDSWAP_MSK	(MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
+#define GT_PCI0_CMD_MWORDSWAP_BIT	GT_PCI0_CMD_MWORDSWAP_MSK
+#define GT_PCI0_CMD_SBYTESWAP_SHF	16
+#define GT_PCI0_CMD_SBYTESWAP_MSK	(MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
+#define GT_PCI0_CMD_SBYTESWAP_BIT	GT_PCI0_CMD_SBYTESWAP_MSK
+#define GT_PCI0_CMD_SWORDSWAP_SHF	11
+#define GT_PCI0_CMD_SWORDSWAP_MSK	(MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
+#define GT_PCI0_CMD_SWORDSWAP_BIT	GT_PCI0_CMD_SWORDSWAP_MSK
+
+#define GT_INTR_T0EXP_SHF		8
+#define GT_INTR_T0EXP_MSK		(MSK(1) << GT_INTR_T0EXP_SHF)
+#define GT_INTR_T0EXP_BIT		GT_INTR_T0EXP_MSK
+#define GT_INTR_RETRYCTR0_SHF		20
+#define GT_INTR_RETRYCTR0_MSK		(MSK(1) << GT_INTR_RETRYCTR0_SHF)
+#define GT_INTR_RETRYCTR0_BIT		GT_INTR_RETRYCTR0_MSK
+
+/*
+ *  Misc
+ */
+#define GT_DEF_PCI0_IO_BASE	0x10000000
+#define GT_DEF_PCI0_IO_SIZE	0x02000000
+#define GT_DEF_PCI0_MEM0_BASE	0x12000000
+#define GT_DEF_PCI0_MEM0_SIZE	0x02000000
+#define GT_DEF_BASE		0x14000000
+
+#define GT_MAX_BANKSIZE		(256 * 1024 * 1024)	/* Max 256MB bank  */
+#define GT_LATTIM_MIN		6			/* Minimum lat	*/
+
+#endif /* _ASM_GT64120_H */
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 05/10] MIPS: qemu-malta: setup GT64120 registers as done by YAMON
  2013-05-22 13:57 [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
                   ` (3 preceding siblings ...)
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 04/10] MIPS: import gt64120.h header from Linux Gabor Juhos
@ 2013-05-22 13:57 ` Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 06/10] MIPS: qemu-malta: add PCI support Gabor Juhos
                   ` (4 subsequent siblings)
  9 siblings, 0 replies; 16+ messages in thread
From: Gabor Juhos @ 2013-05-22 13:57 UTC (permalink / raw)
  To: u-boot

Move the GT64120 register base to 0x1be00000
and setup PCI BAR registers as done by the
original YAMON bootloader.

This is needed for running Linux kernel.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
Changes since v2:
 - rebased against the master branch of git.denx.de/u-boot.git

Changes since v1:
 - rebased against mips/testing

Changes since RFC: ---
---
 arch/mips/include/asm/malta.h    |    4 ++-
 board/qemu-malta/lowlevel_init.S |   52 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h
index ab951e6..d4d44a2 100644
--- a/arch/mips/include/asm/malta.h
+++ b/arch/mips/include/asm/malta.h
@@ -9,10 +9,12 @@
 #ifndef _MIPS_ASM_MALTA_H
 #define _MIPS_ASM_MALTA_H
 
-#define MALTA_IO_PORT_BASE	0x10000000
+#define MALTA_IO_PORT_BASE	0x18000000
 
 #define MALTA_UART_BASE		(MALTA_IO_PORT_BASE + 0x3f8)
 
+#define MALTA_GT_BASE		0x1be00000
+
 #define MALTA_RESET_BASE	0x1f000500
 #define GORESET			0x42
 
diff --git a/board/qemu-malta/lowlevel_init.S b/board/qemu-malta/lowlevel_init.S
index c5c5bd9..ff4a072 100644
--- a/board/qemu-malta/lowlevel_init.S
+++ b/board/qemu-malta/lowlevel_init.S
@@ -6,7 +6,20 @@
  * by the Free Software Foundation.
  */
 
+#include <config.h>
+#include <gt64120.h>
+
+#include <asm/addrspace.h>
 #include <asm/regdef.h>
+#include <asm/malta.h>
+
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CPU_TO_GT32(_x)		((_x))
+#else
+#define CPU_TO_GT32(_x) (					\
+	(((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) |	\
+	(((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
+#endif
 
 	.text
 	.set noreorder
@@ -15,5 +28,44 @@
 	.globl	lowlevel_init
 lowlevel_init:
 
+	/*
+	 * Load BAR registers of GT64120 as done by YAMON
+	 *
+	 * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
+	 * to the barebox mailing list.
+	 * The subject of the original patch:
+	 *   'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
+	 * URL:
+	 * http://www.mail-archive.com/barebox at lists.infradead.org/msg06128.html
+	 *
+	 * based on write_bootloader() in qemu.git/hw/mips_malta.c
+	 * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
+	 */
+
+	/* move GT64120 registers from 0x14000000 to 0x1be00000 */
+	li	t1, KSEG1ADDR(GT_DEF_BASE)
+	li	t0, CPU_TO_GT32(0xdf000000)
+	sw	t0, GT_ISD_OFS(t1)
+
+	/* setup MEM-to-PCI0 mapping */
+	li	t1, KSEG1ADDR(MALTA_GT_BASE)
+
+	/* setup PCI0 io window to 0x18000000-0x181fffff */
+	li	t0, CPU_TO_GT32(0xc0000000)
+	sw	t0, GT_PCI0IOLD_OFS(t1)
+	li	t0, CPU_TO_GT32(0x40000000)
+	sw	t0, GT_PCI0IOHD_OFS(t1)
+
+	/* setup PCI0 mem windows */
+	li	t0, CPU_TO_GT32(0x80000000)
+	sw	t0, GT_PCI0M0LD_OFS(t1)
+	li	t0, CPU_TO_GT32(0x3f000000)
+	sw	t0, GT_PCI0M0HD_OFS(t1)
+
+	li	t0, CPU_TO_GT32(0xc1000000)
+	sw	t0, GT_PCI0M1LD_OFS(t1)
+	li	t0, CPU_TO_GT32(0x5e000000)
+	sw	t0, GT_PCI0M1HD_OFS(t1)
+
 	jr	ra
 	 nop
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 06/10] MIPS: qemu-malta: add PCI support
  2013-05-22 13:57 [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
                   ` (4 preceding siblings ...)
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 05/10] MIPS: qemu-malta: setup GT64120 registers as done by YAMON Gabor Juhos
@ 2013-05-22 13:57 ` Gabor Juhos
  2013-05-22 20:15   ` Daniel Schwierzeck
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 07/10] net: pcnet: use pci_virt_to_mem to obtain buffer addresses Gabor Juhos
                   ` (3 subsequent siblings)
  9 siblings, 1 reply; 16+ messages in thread
From: Gabor Juhos @ 2013-05-22 13:57 UTC (permalink / raw)
  To: u-boot

Qemu emulates the Galileo GT64120 System Controller
which provides a CPU bus to PCI bus bridge.

The patch adds driver for this bridge and enables
PCI support for the emulated Malta board.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
Changes since v2:
 - move the PCI driver to drivers/pci
 - fix checkpatch warnings
 - rebased against the master branch of git.denx.de/u-boot.git

Changes since v1:
 - rebased against mips/testing

Changes since RFC:
  - use a C struct to define the register layout instead
    of using a base address plus offset notation
  - remove custom IO accessors

Screenshot:

  U-Boot 2013.04-00242-g8960ff8 (May 22 2013 - 13:25:13)

  Board: MIPS Malta CoreLV (Qemu)
  DRAM:  256 MiB
  pflash_write: Unimplemented flash cmd sequence (offset 0000000000000000, wcycle 0x0 cmd 0x0 value 0xf0)
  Flash: 4 MiB
  Using default environment

  In:    serial
  Out:   serial
  Err:   serial
  qemu-malta # pci
  Scanning PCI devices on bus 0
  BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
  _____________________________________________________________
  00.00.00   0x11ab     0x4620     Bridge device           0x00
  00.0a.00   0x8086     0x7110     Bridge device           0x01
  00.0a.01   0x8086     0x7111     Mass storage controller 0x01
  00.0a.02   0x8086     0x7112     Serial bus controller   0x03
  00.0a.03   0x8086     0x7113     Bridge device           0x80
  00.0b.00   0x1022     0x2000     Network controller      0x00
  qemu-malta #
---
 board/qemu-malta/qemu-malta.c |   12 +++
 drivers/pci/Makefile          |    1 +
 drivers/pci/pci_gt64120.c     |  178 +++++++++++++++++++++++++++++++++++++++++
 include/configs/qemu-malta.h  |    6 ++
 include/pci_gt64120.h         |   19 +++++
 5 files changed, 216 insertions(+)
 create mode 100644 drivers/pci/pci_gt64120.c
 create mode 100644 include/pci_gt64120.h

diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c
index 449da9c..e3a733f 100644
--- a/board/qemu-malta/qemu-malta.c
+++ b/board/qemu-malta/qemu-malta.c
@@ -8,8 +8,10 @@
 
 #include <common.h>
 
+#include <asm/addrspace.h>
 #include <asm/io.h>
 #include <asm/malta.h>
+#include <pci_gt64120.h>
 
 phys_size_t initdram(int board_type)
 {
@@ -29,3 +31,13 @@ void _machine_restart(void)
 	reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
 	__raw_writel(GORESET, reset_base);
 }
+
+void pci_init_board(void)
+{
+	set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
+
+	gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
+			 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+			 0x10000000, 0x10000000, 128 * 1024 * 1024,
+			 0x00000000, 0x00000000, 0x20000);
+}
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 1ae35d3..02d2309 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -27,6 +27,7 @@ LIB	:= $(obj)libpci.o
 
 COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
 COBJS-$(CONFIG_PCI) += pci.o pci_auto.o pci_indirect.o
+COBJS-$(CONFIG_PCI_GT64120) += pci_gt64120.o
 COBJS-$(CONFIG_FTPCI100) += pci_ftpci100.o
 COBJS-$(CONFIG_IXP_PCI) += pci_ixp.o
 COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o
diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
new file mode 100644
index 0000000..c2f2049
--- /dev/null
+++ b/drivers/pci/pci_gt64120.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Based on the Linux implementation.
+ *   Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
+ *   Authors: Carsten Langgaard <carstenl@mips.com>
+ *            Maciej W. Rozycki <macro@mips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <gt64120.h>
+#include <pci.h>
+#include <pci_gt64120.h>
+
+#include <asm/io.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+struct gt64120_regs {
+	u8	unused_000[0xc18];
+	u32	intrcause;
+	u8	unused_c1c[0x0dc];
+	u32	pci0_cfgaddr;
+	u32	pci0_cfgdata;
+};
+
+struct gt64120_pci_controller {
+	struct pci_controller hose;
+	struct gt64120_regs *regs;
+};
+
+static inline struct gt64120_pci_controller *
+hose_to_gt64120(struct pci_controller *hose)
+{
+	return container_of(hose, struct gt64120_pci_controller, hose);
+}
+
+#define GT_INTRCAUSE_ABORT_BITS	\
+		(GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)
+
+static int gt_config_access(struct gt64120_pci_controller *gt,
+			    unsigned char access_type, pci_dev_t bdf,
+			    int where, u32 *data)
+{
+	unsigned int bus = PCI_BUS(bdf);
+	unsigned int dev = PCI_DEV(bdf);
+	unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
+	u32 intr;
+	u32 addr;
+	u32 val;
+
+	if (bus == 0 && dev >= 31) {
+		/* Because of a bug in the galileo (for slot 31). */
+		return -1;
+	}
+
+	if (access_type == PCI_ACCESS_WRITE)
+		debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n",
+		      PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
+
+	/* Clear cause register bits */
+	writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
+
+	addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
+	addr |=	bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
+	addr |=	devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
+	addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
+
+	/* Setup address */
+	writel(addr, &gt->regs->pci0_cfgaddr);
+
+	if (access_type == PCI_ACCESS_WRITE) {
+		if (bus == 0 && dev == 0) {
+			/*
+			 * The Galileo system controller is acting
+			 * differently than other devices.
+			 */
+			val = *data;
+		} else {
+			val = cpu_to_le32(*data);
+		}
+
+		writel(val, &gt->regs->pci0_cfgdata);
+	} else {
+		val = readl(&gt->regs->pci0_cfgdata);
+
+		if (bus == 0 && dev == 0) {
+			/*
+			 * The Galileo system controller is acting
+			 * differently than other devices.
+			 */
+			*data = val;
+		} else {
+			*data = le32_to_cpu(val);
+		}
+	}
+
+	/* Check for master or target abort */
+	intr = readl(&gt->regs->intrcause);
+	if (intr & GT_INTRCAUSE_ABORT_BITS) {
+		/* Error occurred, clear abort bits */
+		writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
+		return -1;
+	}
+
+	if (access_type == PCI_ACCESS_READ)
+		debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n",
+		      PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
+
+	return 0;
+}
+
+static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
+				int where, u32 *value)
+{
+	struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
+
+	*value = 0xffffffff;
+	return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
+}
+
+static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
+				 int where, u32 value)
+{
+	struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
+	u32 data = value;
+
+	return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
+}
+
+int gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
+		     unsigned long sys_size, unsigned long mem_bus,
+		     unsigned long mem_phys, unsigned long mem_size,
+		     unsigned long io_bus, unsigned long io_phys,
+		     unsigned long io_size)
+{
+	static struct gt64120_pci_controller global_gt;
+	struct gt64120_pci_controller *gt;
+	struct pci_controller *hose;
+
+	gt = &global_gt;
+	gt->regs = regs;
+
+	hose = &gt->hose;
+
+	hose->first_busno = 0;
+	hose->last_busno = 0;
+
+	/* System memory space */
+	pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	/* PCI memory space */
+	pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
+		       PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
+		       PCI_REGION_IO);
+
+	hose->region_count = 3;
+
+	pci_set_ops(hose,
+		    pci_hose_read_config_byte_via_dword,
+		    pci_hose_read_config_word_via_dword,
+		    gt_read_config_dword,
+		    pci_hose_write_config_byte_via_dword,
+		    pci_hose_write_config_word_via_dword,
+		    gt_write_config_dword);
+
+	pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/include/configs/qemu-malta.h b/include/configs/qemu-malta.h
index 436bb49..ef44d3d 100644
--- a/include/configs/qemu-malta.h
+++ b/include/configs/qemu-malta.h
@@ -17,6 +17,10 @@
  */
 #define CONFIG_QEMU_MALTA
 
+#define CONFIG_PCI
+#define CONFIG_PCI_GT64120
+#define CONFIG_PCI_PNP
+
 /*
  * CPU Configuration
  */
@@ -104,6 +108,8 @@
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
 
+#define CONFIG_CMD_PCI
+
 #define CONFIG_SYS_LONGHELP		/* verbose help, undef to save memory */
 
 #endif /* _QEMU_MALTA_CONFIG_H */
diff --git a/include/pci_gt64120.h b/include/pci_gt64120.h
new file mode 100644
index 0000000..aae6b33
--- /dev/null
+++ b/include/pci_gt64120.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _PCI_GT64120_H
+#define _PCI_GT64120_H
+
+int gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
+		     unsigned long sys_size, unsigned long mem_bus,
+		     unsigned long mem_phys, unsigned long mem_size,
+		     unsigned long io_bus, unsigned long io_phys,
+		     unsigned long io_size);
+
+
+#endif /* _PCI_GT64120_H */
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 07/10] net: pcnet: use pci_virt_to_mem to obtain buffer addresses
  2013-05-22 13:57 [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
                   ` (5 preceding siblings ...)
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 06/10] MIPS: qemu-malta: add PCI support Gabor Juhos
@ 2013-05-22 13:57 ` Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 08/10] MIPS: qemu-malta: bring up ethernet Gabor Juhos
                   ` (2 subsequent siblings)
  9 siblings, 0 replies; 16+ messages in thread
From: Gabor Juhos @ 2013-05-22 13:57 UTC (permalink / raw)
  To: u-boot

The pcnet driver uses the pci_phys_to_mem function
to get the memory address of the DMA buffers. This
This assumes an 1:1 mapping between the PCI and
physical memory which is not true on all platforms.

On MIPS platform U-Boot is running within a mapped
memory region, and the pci_phys_to_mem macro can't
be used to obtain the memory address of the buffers.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
Changes since v2:
  - rebased against the master branch of git.denx.de/u-boot.git

Changes since v1:
 - rebased against mips/testing

Changes since RFC: ---

---
Note:

This is only tested with the qemu-malta target. The change
might break real platforms, however I have no suitable board
to test it.

-Gabor
---
 drivers/net/pcnet.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index c028a44..45a66fb 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -146,7 +146,7 @@ static int pcnet_recv (struct eth_device *dev);
 static void pcnet_halt (struct eth_device *dev);
 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
 
-#define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a))
+#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a))
 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
 
 static struct pci_device_id supported[] = {
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 08/10] MIPS: qemu-malta: bring up ethernet
  2013-05-22 13:57 [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
                   ` (6 preceding siblings ...)
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 07/10] net: pcnet: use pci_virt_to_mem to obtain buffer addresses Gabor Juhos
@ 2013-05-22 13:57 ` Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 09/10] MIPS: bootm.c: add YAMON style Linux preparation/jump code Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 10/10] MIPS: start.S: emulate REVISION register for qemu-malta Gabor Juhos
  9 siblings, 0 replies; 16+ messages in thread
From: Gabor Juhos @ 2013-05-22 13:57 UTC (permalink / raw)
  To: u-boot

Qemu emulates a PCNET PCI card for the Malta CoreLV board.
Enable the pcnet driver and add board specific ethernet
initialization function to bring it up. Also enable the
CONFIG_CMD_NET and CONFIG_CMD_PING options.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
Changes since v2:
 - rebased against the master branch of git.denx.de/u-boot.git

Changes since v1:
 - rebased against mips/testing

Changes since RFC: ---

Screenshot:

  U-Boot 2013.04-00244-g99710fc (May 22 2013 - 13:27:18)

  Board: MIPS Malta CoreLV (Qemu)
  DRAM:  256 MiB
  pflash_write: Unimplemented flash cmd sequence (offset 0000000000000000, wcycle 0x0 cmd 0x0 value 0xf0)
  Flash: 4 MiB
  Using default environment

  In:    serial
  Out:   serial
  Err:   serial
  Net:   pcnet#0
  qemu-malta # setenv ethaddr 00:11:22:33:44:55
  qemu-malta # setenv serverip 10.0.2.2
  qemu-malta # setenv ipaddr 10.0.2.1
  qemu-malta # ping 10.0.2.2
  Using pcnet#0 device
  host 10.0.2.2 is alive
  qemu-malta #
---
 board/qemu-malta/qemu-malta.c |    6 ++++++
 include/configs/qemu-malta.h  |    3 ++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c
index e3a733f..4cbd736 100644
--- a/board/qemu-malta/qemu-malta.c
+++ b/board/qemu-malta/qemu-malta.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 
 #include <asm/addrspace.h>
 #include <asm/io.h>
@@ -24,6 +25,11 @@ int checkboard(void)
 	return 0;
 }
 
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
 void _machine_restart(void)
 {
 	void __iomem *reset_base;
diff --git a/include/configs/qemu-malta.h b/include/configs/qemu-malta.h
index ef44d3d..c79c911 100644
--- a/include/configs/qemu-malta.h
+++ b/include/configs/qemu-malta.h
@@ -20,6 +20,7 @@
 #define CONFIG_PCI
 #define CONFIG_PCI_GT64120
 #define CONFIG_PCI_PNP
+#define CONFIG_PCNET
 
 /*
  * CPU Configuration
@@ -105,10 +106,10 @@
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_LOADB
 #undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
 
 #define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
 
 #define CONFIG_SYS_LONGHELP		/* verbose help, undef to save memory */
 
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 09/10] MIPS: bootm.c: add YAMON style Linux preparation/jump code
  2013-05-22 13:57 [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
                   ` (7 preceding siblings ...)
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 08/10] MIPS: qemu-malta: bring up ethernet Gabor Juhos
@ 2013-05-22 13:57 ` Gabor Juhos
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 10/10] MIPS: start.S: emulate REVISION register for qemu-malta Gabor Juhos
  9 siblings, 0 replies; 16+ messages in thread
From: Gabor Juhos @ 2013-05-22 13:57 UTC (permalink / raw)
  To: u-boot

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
Changes since v2:
 - rebased against the master branch of git.denx.de/u-boot.git
Changes since v1:
 - rebased against mips/testing

Changes since RFC: ---
---
 arch/mips/lib/bootm.c |   60 +++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 58 insertions(+), 2 deletions(-)

diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index a36154a..85492e5 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -33,6 +33,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define	LINUX_MAX_ENVS		256
 #define	LINUX_MAX_ARGS		256
 
+#if defined(CONFIG_QEMU_MALTA)
+#define board_is_qemu_malta	1
+#else
+#define board_is_qemu_malta	0
+#endif
+
 static int linux_argc;
 static char **linux_argv;
 
@@ -43,7 +49,7 @@ static int linux_env_idx;
 static void linux_params_init(ulong start, char *commandline);
 static void linux_env_set(char *env_name, char *env_val);
 
-static void boot_prep_linux(bootm_headers_t *images)
+static void boot_prep_linux_legacy(bootm_headers_t *images)
 {
 	char *commandline = getenv("bootargs");
 	char env_buf[12];
@@ -83,6 +89,52 @@ static void boot_prep_linux(bootm_headers_t *images)
 		linux_env_set("eth1addr", cp);
 }
 
+static void malta_env_set(char *env_name, char *env_val)
+{
+	if (linux_env_idx >= LINUX_MAX_ENVS - 2)
+		return;
+
+	linux_env[linux_env_idx] = linux_env_p;
+
+	strcpy(linux_env_p, env_name);
+	linux_env_p += strlen(env_name);
+
+	linux_env_p++;
+	linux_env[++linux_env_idx] = linux_env_p;
+
+	strcpy(linux_env_p, env_val);
+	linux_env_p += strlen(env_val);
+
+	linux_env_p++;
+	linux_env[++linux_env_idx] = 0;
+}
+
+static void boot_prep_linux_qemu_malta(bootm_headers_t *images)
+{
+	char *bootargs = getenv("bootargs");
+	char env_buf[12];
+	char *cp;
+
+	linux_params_init(UNCACHED_SDRAM(gd->bd->bi_boot_params), bootargs);
+
+	/* setup environment variables */
+	sprintf(env_buf, "%lu", (ulong)gd->ram_size);
+	malta_env_set("memsize", env_buf);
+	malta_env_set("modetty0", "38400n8r");
+
+	cp = getenv("ethaddr");
+	if (cp)
+		malta_env_set("ethaddr", cp);
+}
+
+static void boot_prep_linux(bootm_headers_t *images)
+{
+	if (board_is_qemu_malta)
+		boot_prep_linux_qemu_malta(images);
+	else
+		boot_prep_linux_legacy(images);
+}
+
 static void boot_jump_linux(bootm_headers_t *images)
 {
 	void (*theKernel) (int, char **, char **, int *);
@@ -98,7 +150,11 @@ static void boot_jump_linux(bootm_headers_t *images)
 	/* we assume that the kernel is in place */
 	printf("\nStarting kernel ...\n\n");
 
-	theKernel(linux_argc, linux_argv, linux_env, 0);
+	if (board_is_qemu_malta)
+		theKernel(linux_argc, linux_argv, linux_env,
+			  (int *)gd->ram_size);
+	else
+		theKernel(linux_argc, linux_argv, linux_env, 0);
 }
 
 int do_bootm_linux(int flag, int argc, char * const argv[],
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 10/10] MIPS: start.S: emulate REVISION register for qemu-malta
  2013-05-22 13:57 [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
                   ` (8 preceding siblings ...)
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 09/10] MIPS: bootm.c: add YAMON style Linux preparation/jump code Gabor Juhos
@ 2013-05-22 13:57 ` Gabor Juhos
  9 siblings, 0 replies; 16+ messages in thread
From: Gabor Juhos @ 2013-05-22 13:57 UTC (permalink / raw)
  To: u-boot

On the origial Malta boards the REVISION register is
accessible at the 0x1fc00010 address. The contents of
this register gives information about the revision
of the Malta and Core Boards.

This register is used by the Linux kernel to identify
the actual board it is running on. However the register
is not emulated properly by Qemu, so put a hardcoded
value into the flash to make Linux work.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
Changes since v2:
 - rebased against the master branch of git.denx.de/u-boot.git

Changes since v1:
 - rebased against mips/testing

Changes since RFC: ---

Screenshot:

  U-Boot 2013.04-00246-gd93f756 (May 22 2013 - 14:18:54)

  Board: MIPS Malta CoreLV (Qemu)
  DRAM:  256 MiB
  pflash_write: Unimplemented flash cmd sequence (offset 0000000000000000, wcycle 0x0 cmd 0x0 value 0xf0)
  Flash: 4 MiB
  Using default environment

  In:    serial
  Out:   serial
  Err:   serial
  Net:   pcnet#0
  qemu-maltael # setenv ethaddr 00:11:22:33:44:55
  qemu-maltael # setenv ipaddr 10.0.2.1
  qemu-maltael # setenv serverip 10.0.2.2
  qemu-maltael # tftp openwrt-malta-le-uImage-gzip
  Using pcnet#0 device
  TFTP from server 10.0.2.2; our IP address is 10.0.2.1
  Filename 'openwrt-malta-le-uImage-gzip'.
  Load address: 0x81000000
  Loading:
           #################################################################
           #################################################################
           #################################################################
           #################################################################
           #################################################################
           #################################################################
           #################################################################
           ######################################################
           52.8 MiB/s
  done
  Bytes transferred = 2935968 (2ccca0 hex)
  qemu-maltael # bootm
  ## Booting kernel from Legacy Image at 81000000 ...
     Image Name:   MIPS OpenWrt Linux-3.8.13
     Image Type:   MIPS Linux Kernel Image (gzip compressed)
     Data Size:    2935904 Bytes = 2.8 MiB
     Load Address: 80100000
     Entry Point:  80104a90
     Verifying Checksum ... OK
     Uncompressing Kernel Image ... OK

  Starting kernel ...

  [    0.000000] Linux version 3.8.13 (juhosg at mag2) (gcc version 4.6.4 20121210 (prerelease) (Linaro GCC 4.6-2012.12) ) #1 SMP Wed May 22 14:13:27 CEST 2013
  [    0.000000] Config serial console: console=ttyS0,38400n8r
  [    0.000000] bootconsole [early0] enabled
  [    0.000000] CPU revision is: 00019300 (MIPS 24Kc)
  [    0.000000] FPU revision is: 00739300
  [    0.000000] Determined physical RAM map:
  [    0.000000]  memory: 00001000 @ 00000000 (reserved)
  [    0.000000]  memory: 000ef000 @ 00001000 (ROM data)
  [    0.000000]  memory: 00676000 @ 000f0000 (reserved)
  [    0.000000]  memory: 0f89a000 @ 00766000 (usable)
  [    0.000000] Wasting 60608 bytes for tracking 1894 unused pages
  [    0.000000] Initrd not found or empty - disabling initrd
  [    0.000000] Zone ranges:
  [    0.000000]   DMA      [mem 0x00000000-0x00ffffff]
  [    0.000000]   Normal   [mem 0x01000000-0x0fffffff]
  [    0.000000] Movable zone start for each node
  [    0.000000] Early memory node ranges
  [    0.000000]   node   0: [mem 0x00000000-0x0fffffff]
  [    0.000000] Primary instruction cache 2kB, VIPT, 2-way, linesize 16 bytes.
  [    0.000000] Primary data cache 2kB, 2-way, VIPT, no aliases, linesize 16 bytes
  [    0.000000] PERCPU: Embedded 7 pages/cpu @81203000 s6464 r8192 d14016 u32768
  [    0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
  [    0.000000] Kernel command line:  console=ttyS0,38400n8r
  [    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
  [    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
  [    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
  [    0.000000] __ex_table already sorted, skipping sort
  [    0.000000] Writing ErrCtl register=00000000
  [    0.000000] Readback ErrCtl register=00000000
  [    0.000000] Memory: 252260k/254568k available (2517k kernel code, 2308k reserved, 624k data, 3320k init, 0k highmem)
  [    0.000000] Hierarchical RCU implementation.
  [    0.000000]  RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
  [    0.000000] NR_IRQS:256
  [    0.000000] CPU frequency 199.93 MHz
  [    0.000000] Console: colour dummy device 80x25
  [    0.000000] Calibrating delay loop... 1168.17 BogoMIPS (lpj=5840896)
  [    0.120000] pid_max: default: 32768 minimum: 301
  [    0.120000] Mount-cache hash table entries: 512
  [    0.130000] Brought up 1 CPUs
  [    0.140000] NET: Registered protocol family 16
  [    0.180000] bio: create slab <bio-0> at 0
  [    0.190000] SCSI subsystem initialized
  [    0.190000] PCI host bridge to bus 0000:00
  [    0.190000] pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff]
  [    0.190000] pci_bus 0000:00: root bus resource [io 0x2000-0x1fffff]
  [    0.190000] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
  [    0.200000] pci 0000:00:0a.3: no compatible bridge window for [io 0x1100-0x110f]
  [    0.200000] pci 0000:00:0a.3: BAR 8: [io  0x1100-0x110f] has bogus alignment
  [    0.200000] pci 0000:00:0a.2: BAR 4: assigned [io  0x2000-0x201f]
  [    0.200000] pci 0000:00:0b.0: BAR 0: assigned [io  0x2020-0x203f]
  [    0.200000] pci 0000:00:0b.0: BAR 1: assigned [mem 0x10000000-0x1000001f]
  [    0.210000] pci 0000:00:0a.1: BAR 4: assigned [io  0x2040-0x204f]
  [    0.210000] Switching to clocksource MIPS
  [    0.240000] NET: Registered protocol family 2
  [    0.240000] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
  [    0.250000] TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
  [    0.250000] TCP: Hash tables configured (established 2048 bind 2048)
  [    0.250000] TCP: reno registered
  [    0.250000] UDP hash table entries: 256 (order: 1, 8192 bytes)
  [    0.250000] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
  [    0.250000] NET: Registered protocol family 1
  [    0.350000] VFS: Disk quotas dquot_6.5.2
  [    0.360000] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
  [    0.360000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  [    0.360000] jffs2: version 2.2 (NAND) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
  [    0.360000] msgmni has been set to 492
  [    0.360000] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
  [    0.360000] io scheduler noop registered
  [    0.360000] io scheduler deadline registered (default)
  [    0.560000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
  [    0.590000] serial8250.0: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
  [    0.590000] console [ttyS0] enabled, bootconsole disabled
  [    0.590000] console [ttyS0] enabled, bootconsole disabled
  [    0.610000] serial8250.0: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
  [    0.640000] serial8250.0: ttyS2 at MMIO 0x1f000900 (irq = 20) is a 16550A
  [    0.660000] brd: module loaded
  [    0.660000] physmap platform flash device: 00400000 at 1e000000
  pflash_write: Unimplemented flash cmd sequence (offset 0000000000000000, wcycle 0x0 cmd 0x0 value 0xf000f0)
  [    0.660000] physmap-flash.0: Found 1 x32 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
  [    0.670000] Intel/Sharp Extended Query Table at 0x0031
  pflash_write: Unimplemented flash cmd sequence (offset 0000000000000000, wcycle 0x0 cmd 0x0 value 0xf0)
  [    0.670000] Using buffer write method
  [    0.670000] Creating 3 MTD partitions on "physmap-flash.0":
  [    0.670000] 0x000000000000-0x000000100000 : "YAMON"
  [    0.680000] 0x000000100000-0x0000003e0000 : "User FS"
  [    0.680000] 0x0000003e0000-0x000000400000 : "Board Config"
  [    0.680000] mousedev: PS/2 mouse device common for all mice
  [    0.680000] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0
  [    0.690000] rtc0: alarms up to one day, 242 bytes nvram
  [    0.690000] TCP: cubic registered
  [    0.690000] NET: Registered protocol family 17
  [    0.690000] 8021q: 802.1Q VLAN Support v1.8
  [    0.690000] rtc_cmos rtc_cmos: setting system clock to 2013-05-22 12:20:16 UTC (1369225216)
  [    0.690000] Please be patient, while OpenWrt loads ...
  [    0.700000] Freeing prom memory: 956k freed
  [    0.710000] Freeing unused kernel memory: 3320k freed
  - preinit -
  Press the [f] key and hit [enter] to enter failsafe mode
  - regular preinit -
  - init -

  Please press Enter to activate this console.
  [    7.310000] compat-drivers backport release: compat-drivers-2013-03-28-5
  [    7.310000] Backport based on wireless-testing.git master-2013-04-16
  [    7.310000] compat.git: wireless-testing.git
  [    7.360000] cfg80211: Calling CRDA to update world regulatory domain
  [    7.360000] cfg80211: World regulatory domain updated:
  [    7.360000] cfg80211:   (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
  [    7.360000] cfg80211:   (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
  [    7.360000] cfg80211:   (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
  [    7.360000] cfg80211:   (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
  [    7.360000] cfg80211:   (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
  [    7.360000] cfg80211:   (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
  [    7.550000] pcnet32: pcnet32.c:v1.35 21.Apr.2008 tsbogend at alpha.franken.de
  [    7.550000] PCI: Enabling device 0000:00:0b.0 (0005 -> 0007)
  [    7.550000] pcnet32: PCnet/PCI II 79C970A at 0x2020, 52:54:00:12:34:56 assigned IRQ 10
  [    7.550000] pcnet32: eth0: registered as PCnet/PCI II 79C970A
  [    7.550000] pcnet32: 1 cards_found
  [    7.610000] mac80211_hwsim: initializing netlink
  [   12.820000] pcnet32 0000:00:0b.0 eth0: link up
  [   12.840000] device eth0 entered promiscuous mode
  [   12.840000] br-lan: port 1(eth0) entered forwarding state
  [   12.840000] br-lan: port 1(eth0) entered forwarding state
  [   14.840000] br-lan: port 1(eth0) entered forwarding state

  BusyBox v1.19.4 (2013-05-22 14:04:57 CEST) built-in shell (ash)
  Enter 'help' for a list of built-in commands.

    _______                     ________        __
   |       |.-----.-----.-----.|  |  |  |.----.|  |_
   |   -   ||  _  |  -__|     ||  |  |  ||   _||   _|
   |_______||   __|_____|__|__||________||__|  |____|
            |__| W I R E L E S S   F R E E D O M
   -----------------------------------------------------
   BARRIER BREAKER (Bleeding Edge, r36689)
   -----------------------------------------------------
    * 1/2 oz Galliano         Pour all ingredients into
    * 4 oz cold Coffee        an irish coffee mug filled
    * 1 1/2 oz Dark Rum       with crushed ice. Stir.
    * 2 tsp. Creme de Cacao
   -----------------------------------------------------
  root at OpenWrt:/# uname -a
  Linux OpenWrt 3.8.13 #1 SMP Wed May 22 14:13:27 CEST 2013 mips GNU/Linux
  root at OpenWrt:/# cat /proc/cpuinfo
  system type             : MIPS Malta
  processor               : 0
  cpu model               : MIPS 24Kc V0.0  FPU V0.0
  BogoMIPS                : 1168.17
  wait instruction        : yes
  microsecond timers      : yes
  tlb_entries             : 16
  extra interrupt vector  : yes
  hardware watchpoint     : yes, count: 1, address/irw mask: [0x0ff8]
  ASEs implemented        : mips16
  shadow register sets    : 1
  kscratch registers      : 0
  core                    : 0
  VCED exceptions         : not available
  VCEI exceptions         : not available

  root at OpenWrt:/#
---
 arch/mips/cpu/mips32/start.S |    8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 76abbaa..a448f9f 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -57,7 +57,7 @@ _start:
 	 nop
 
 	.org 0x10
-#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
+#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
 	/*
 	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
 	 * access external NOR flashes. If the board boots from NOR flash the
@@ -67,6 +67,12 @@ _start:
 	 */
 	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
 	.word 0x0
+#elif defined(CONFIG_QEMU_MALTA)
+	/*
+	 * Linux expects the Board ID here.
+	 */
+	.word 0x00000420	# 0x420 (Malta Board with CoreLV)
+	.word 0x00000000
 #endif
 
 	.org 0x200
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 06/10] MIPS: qemu-malta: add PCI support
  2013-05-22 13:57 ` [U-Boot] [PATCH v3 06/10] MIPS: qemu-malta: add PCI support Gabor Juhos
@ 2013-05-22 20:15   ` Daniel Schwierzeck
  2013-05-23 11:59     ` Gabor Juhos
  0 siblings, 1 reply; 16+ messages in thread
From: Daniel Schwierzeck @ 2013-05-22 20:15 UTC (permalink / raw)
  To: u-boot

2013/5/22 Gabor Juhos <juhosg@openwrt.org>:
> Qemu emulates the Galileo GT64120 System Controller
> which provides a CPU bus to PCI bus bridge.
>
> The patch adds driver for this bridge and enables
> PCI support for the emulated Malta board.
>
> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>


ELDK-5.3 shows some warnings:

pci_indirect.c: In function 'indirect_read_config_byte':
pci_indirect.c:101:1: warning: implicit declaration of function
'out_le32' [-Wimplicit-function-declaration]
pci_indirect.c:101:1: warning: implicit declaration of function 'in_8'
[-Wimplicit-function-declaration]
pci_indirect.c: In function 'indirect_read_config_word':
pci_indirect.c:102:1: warning: implicit declaration of function
'in_le16' [-Wimplicit-function-declaration]
pci_indirect.c: In function 'indirect_read_config_dword':
pci_indirect.c:103:1: warning: implicit declaration of function
'in_le32' [-Wimplicit-function-declaration]
pci_indirect.c: In function 'indirect_write_config_byte':
pci_indirect.c:109:1: warning: implicit declaration of function
'out_8' [-Wimplicit-function-declaration]
pci_indirect.c: In function 'indirect_write_config_word':
pci_indirect.c:110:1: warning: implicit declaration of function
'out_le16' [-Wimplicit-function-declaration]
pci_gt64120.c: In function 'gt64120_pci_init':
pci_gt64120.c:178:1: warning: control reaches end of non-void function
[-Wreturn-type]


> ---
> Changes since v2:
>  - move the PCI driver to drivers/pci
>  - fix checkpatch warnings
>  - rebased against the master branch of git.denx.de/u-boot.git
>
> Changes since v1:
>  - rebased against mips/testing
>
> Changes since RFC:
>   - use a C struct to define the register layout instead
>     of using a base address plus offset notation
>   - remove custom IO accessors
>
> Screenshot:
>
>   U-Boot 2013.04-00242-g8960ff8 (May 22 2013 - 13:25:13)
>
>   Board: MIPS Malta CoreLV (Qemu)
>   DRAM:  256 MiB
>   pflash_write: Unimplemented flash cmd sequence (offset 0000000000000000, wcycle 0x0 cmd 0x0 value 0xf0)
>   Flash: 4 MiB
>   Using default environment
>
>   In:    serial
>   Out:   serial
>   Err:   serial
>   qemu-malta # pci
>   Scanning PCI devices on bus 0
>   BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
>   _____________________________________________________________
>   00.00.00   0x11ab     0x4620     Bridge device           0x00
>   00.0a.00   0x8086     0x7110     Bridge device           0x01
>   00.0a.01   0x8086     0x7111     Mass storage controller 0x01
>   00.0a.02   0x8086     0x7112     Serial bus controller   0x03
>   00.0a.03   0x8086     0x7113     Bridge device           0x80
>   00.0b.00   0x1022     0x2000     Network controller      0x00
>   qemu-malta #
> ---
>  board/qemu-malta/qemu-malta.c |   12 +++
>  drivers/pci/Makefile          |    1 +
>  drivers/pci/pci_gt64120.c     |  178 +++++++++++++++++++++++++++++++++++++++++
>  include/configs/qemu-malta.h  |    6 ++
>  include/pci_gt64120.h         |   19 +++++
>  5 files changed, 216 insertions(+)
>  create mode 100644 drivers/pci/pci_gt64120.c
>  create mode 100644 include/pci_gt64120.h
>
> diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c
> index 449da9c..e3a733f 100644
> --- a/board/qemu-malta/qemu-malta.c
> +++ b/board/qemu-malta/qemu-malta.c
> @@ -8,8 +8,10 @@
>
>  #include <common.h>
>
> +#include <asm/addrspace.h>
>  #include <asm/io.h>
>  #include <asm/malta.h>
> +#include <pci_gt64120.h>
>
>  phys_size_t initdram(int board_type)
>  {
> @@ -29,3 +31,13 @@ void _machine_restart(void)
>         reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
>         __raw_writel(GORESET, reset_base);
>  }
> +
> +void pci_init_board(void)
> +{
> +       set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
> +
> +       gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
> +                        0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
> +                        0x10000000, 0x10000000, 128 * 1024 * 1024,
> +                        0x00000000, 0x00000000, 0x20000);
> +}
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index 1ae35d3..02d2309 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -27,6 +27,7 @@ LIB   := $(obj)libpci.o
>
>  COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
>  COBJS-$(CONFIG_PCI) += pci.o pci_auto.o pci_indirect.o
> +COBJS-$(CONFIG_PCI_GT64120) += pci_gt64120.o
>  COBJS-$(CONFIG_FTPCI100) += pci_ftpci100.o
>  COBJS-$(CONFIG_IXP_PCI) += pci_ixp.o
>  COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o
> diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
> new file mode 100644
> index 0000000..c2f2049
> --- /dev/null
> +++ b/drivers/pci/pci_gt64120.c
> @@ -0,0 +1,178 @@
> +/*
> + * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
> + *
> + * Based on the Linux implementation.
> + *   Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
> + *   Authors: Carsten Langgaard <carstenl@mips.com>
> + *            Maciej W. Rozycki <macro@mips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + */
> +
> +#include <common.h>
> +#include <gt64120.h>
> +#include <pci.h>
> +#include <pci_gt64120.h>
> +
> +#include <asm/io.h>
> +
> +#define PCI_ACCESS_READ  0
> +#define PCI_ACCESS_WRITE 1
> +
> +struct gt64120_regs {
> +       u8      unused_000[0xc18];
> +       u32     intrcause;
> +       u8      unused_c1c[0x0dc];
> +       u32     pci0_cfgaddr;
> +       u32     pci0_cfgdata;
> +};
> +
> +struct gt64120_pci_controller {
> +       struct pci_controller hose;
> +       struct gt64120_regs *regs;
> +};
> +
> +static inline struct gt64120_pci_controller *
> +hose_to_gt64120(struct pci_controller *hose)
> +{
> +       return container_of(hose, struct gt64120_pci_controller, hose);
> +}
> +
> +#define GT_INTRCAUSE_ABORT_BITS        \
> +               (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)
> +
> +static int gt_config_access(struct gt64120_pci_controller *gt,
> +                           unsigned char access_type, pci_dev_t bdf,
> +                           int where, u32 *data)
> +{
> +       unsigned int bus = PCI_BUS(bdf);
> +       unsigned int dev = PCI_DEV(bdf);
> +       unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
> +       u32 intr;
> +       u32 addr;
> +       u32 val;
> +
> +       if (bus == 0 && dev >= 31) {
> +               /* Because of a bug in the galileo (for slot 31). */
> +               return -1;
> +       }
> +
> +       if (access_type == PCI_ACCESS_WRITE)
> +               debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n",
> +                     PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
> +
> +       /* Clear cause register bits */
> +       writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
> +
> +       addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
> +       addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
> +       addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
> +       addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
> +
> +       /* Setup address */
> +       writel(addr, &gt->regs->pci0_cfgaddr);
> +
> +       if (access_type == PCI_ACCESS_WRITE) {
> +               if (bus == 0 && dev == 0) {
> +                       /*
> +                        * The Galileo system controller is acting
> +                        * differently than other devices.
> +                        */
> +                       val = *data;
> +               } else {
> +                       val = cpu_to_le32(*data);
> +               }

braces not needed (checkpatch.pl does not catch this)

> +
> +               writel(val, &gt->regs->pci0_cfgdata);
> +       } else {
> +               val = readl(&gt->regs->pci0_cfgdata);
> +
> +               if (bus == 0 && dev == 0) {
> +                       /*
> +                        * The Galileo system controller is acting
> +                        * differently than other devices.
> +                        */
> +                       *data = val;
> +               } else {
> +                       *data = le32_to_cpu(val);
> +               }
> +       }
> +
> +       /* Check for master or target abort */
> +       intr = readl(&gt->regs->intrcause);
> +       if (intr & GT_INTRCAUSE_ABORT_BITS) {
> +               /* Error occurred, clear abort bits */
> +               writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
> +               return -1;
> +       }
> +
> +       if (access_type == PCI_ACCESS_READ)
> +               debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n",
> +                     PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
> +
> +       return 0;
> +}
> +
> +static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
> +                               int where, u32 *value)
> +{
> +       struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
> +
> +       *value = 0xffffffff;
> +       return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
> +}
> +
> +static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
> +                                int where, u32 value)
> +{
> +       struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
> +       u32 data = value;
> +
> +       return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
> +}
> +
> +int gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
> +                    unsigned long sys_size, unsigned long mem_bus,
> +                    unsigned long mem_phys, unsigned long mem_size,
> +                    unsigned long io_bus, unsigned long io_phys,
> +                    unsigned long io_size)
> +{
> +       static struct gt64120_pci_controller global_gt;
> +       struct gt64120_pci_controller *gt;
> +       struct pci_controller *hose;
> +
> +       gt = &global_gt;
> +       gt->regs = regs;
> +
> +       hose = &gt->hose;
> +
> +       hose->first_busno = 0;
> +       hose->last_busno = 0;
> +
> +       /* System memory space */
> +       pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
> +                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
> +
> +       /* PCI memory space */
> +       pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
> +                      PCI_REGION_MEM);
> +
> +       /* PCI I/O space */
> +       pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
> +                      PCI_REGION_IO);
> +
> +       hose->region_count = 3;
> +
> +       pci_set_ops(hose,
> +                   pci_hose_read_config_byte_via_dword,
> +                   pci_hose_read_config_word_via_dword,
> +                   gt_read_config_dword,
> +                   pci_hose_write_config_byte_via_dword,
> +                   pci_hose_write_config_word_via_dword,
> +                   gt_write_config_dword);
> +
> +       pci_register_hose(hose);
> +       hose->last_busno = pci_hose_scan(hose);

missing return keyword

> +}
> diff --git a/include/configs/qemu-malta.h b/include/configs/qemu-malta.h
> index 436bb49..ef44d3d 100644
> --- a/include/configs/qemu-malta.h
> +++ b/include/configs/qemu-malta.h
> @@ -17,6 +17,10 @@
>   */
>  #define CONFIG_QEMU_MALTA
>
> +#define CONFIG_PCI
> +#define CONFIG_PCI_GT64120
> +#define CONFIG_PCI_PNP
> +
>  /*
>   * CPU Configuration
>   */
> @@ -104,6 +108,8 @@
>  #undef CONFIG_CMD_NET
>  #undef CONFIG_CMD_NFS
>
> +#define CONFIG_CMD_PCI
> +
>  #define CONFIG_SYS_LONGHELP            /* verbose help, undef to save memory */
>
>  #endif /* _QEMU_MALTA_CONFIG_H */
> diff --git a/include/pci_gt64120.h b/include/pci_gt64120.h
> new file mode 100644
> index 0000000..aae6b33
> --- /dev/null
> +++ b/include/pci_gt64120.h
> @@ -0,0 +1,19 @@
> +/*
> + * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + */
> +
> +#ifndef _PCI_GT64120_H
> +#define _PCI_GT64120_H
> +
> +int gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
> +                    unsigned long sys_size, unsigned long mem_bus,
> +                    unsigned long mem_phys, unsigned long mem_size,
> +                    unsigned long io_bus, unsigned long io_phys,
> +                    unsigned long io_size);
> +
> +
> +#endif /* _PCI_GT64120_H */
> --
> 1.7.10
>



--
Best regards,
Daniel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 06/10] MIPS: qemu-malta: add PCI support
  2013-05-22 20:15   ` Daniel Schwierzeck
@ 2013-05-23 11:59     ` Gabor Juhos
  2013-05-23 13:55       ` Daniel Schwierzeck
  0 siblings, 1 reply; 16+ messages in thread
From: Gabor Juhos @ 2013-05-23 11:59 UTC (permalink / raw)
  To: u-boot

Hi Daniel,

Thank you for the review!

> 2013/5/22 Gabor Juhos <juhosg@openwrt.org>:
>> Qemu emulates the Galileo GT64120 System Controller
>> which provides a CPU bus to PCI bus bridge.
>>
>> The patch adds driver for this bridge and enables
>> PCI support for the emulated Malta board.
>>
>> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
>> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
> 
> 
> ELDK-5.3 shows some warnings:
> 
> pci_indirect.c: In function 'indirect_read_config_byte':
> pci_indirect.c:101:1: warning: implicit declaration of function
> 'out_le32' [-Wimplicit-function-declaration]
> pci_indirect.c:101:1: warning: implicit declaration of function 'in_8'
> [-Wimplicit-function-declaration]
> pci_indirect.c: In function 'indirect_read_config_word':
> pci_indirect.c:102:1: warning: implicit declaration of function
> 'in_le16' [-Wimplicit-function-declaration]
> pci_indirect.c: In function 'indirect_read_config_dword':
> pci_indirect.c:103:1: warning: implicit declaration of function
> 'in_le32' [-Wimplicit-function-declaration]
> pci_indirect.c: In function 'indirect_write_config_byte':
> pci_indirect.c:109:1: warning: implicit declaration of function
> 'out_8' [-Wimplicit-function-declaration]
> pci_indirect.c: In function 'indirect_write_config_word':
> pci_indirect.c:110:1: warning: implicit declaration of function
> 'out_le16' [-Wimplicit-function-declaration]

Hm, you are right. My toolchain also shows the warning but I did not notice
those because I forgot to redirect stderr when I have generated the build logs.

The pci_indirect.c file is always compiled when CONFIG_PCI is defined although
it is not needed at all for Malta PCI support.

The issue can be resolved on a few different ways:

1. Extend the '#if !defined(__I386__)' directive in pci_indirect.c with a new
'&& !defined(__MIPS__)' condition. This would be the simplest solution but the
drawback of this is that indirect support will not be usable on any MIPS board.

2. Introduce a new 'CONFIG_PCI_INDIRECT_BRIDGE' option and only compile the
pci_indirect.c file if this option is present. Probably this is the best
solution however the new symbol should be added into the configuration of the
affected boards.

3. Introduce a new 'CONFIG_PCI_NO_INDIRECT_BRIDGE' option and use an '#ifndef
CONFIG_PCI_NO_INDIRECT_BRIDGE' directive in pci_indirect.c.

I'm unsure about which approach is preferred.

> pci_gt64120.c: In function 'gt64120_pci_init':
> pci_gt64120.c:178:1: warning: control reaches end of non-void function
> [-Wreturn-type]

<snip>

>> +int gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
>> +                    unsigned long sys_size, unsigned long mem_bus,
>> +                    unsigned long mem_phys, unsigned long mem_size,
>> +                    unsigned long io_bus, unsigned long io_phys,
>> +                    unsigned long io_size)
>> +{
>> +       static struct gt64120_pci_controller global_gt;
>> +       struct gt64120_pci_controller *gt;
>> +       struct pci_controller *hose;
>> +
>> +       gt = &global_gt;
>> +       gt->regs = regs;
>> +
>> +       hose = &gt->hose;
>> +
>> +       hose->first_busno = 0;
>> +       hose->last_busno = 0;
>> +
>> +       /* System memory space */
>> +       pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
>> +                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
>> +
>> +       /* PCI memory space */
>> +       pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
>> +                      PCI_REGION_MEM);
>> +
>> +       /* PCI I/O space */
>> +       pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
>> +                      PCI_REGION_IO);
>> +
>> +       hose->region_count = 3;
>> +
>> +       pci_set_ops(hose,
>> +                   pci_hose_read_config_byte_via_dword,
>> +                   pci_hose_read_config_word_via_dword,
>> +                   gt_read_config_dword,
>> +                   pci_hose_write_config_byte_via_dword,
>> +                   pci_hose_write_config_word_via_dword,
>> +                   gt_write_config_dword);
>> +
>> +       pci_register_hose(hose);
>> +       hose->last_busno = pci_hose_scan(hose);
> 
> missing return keyword

Correct. However the function never fails, so I will convert it to void instead
of adding a 'return 0;' line.

> 
>> +}

-Gabor

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 06/10] MIPS: qemu-malta: add PCI support
  2013-05-23 11:59     ` Gabor Juhos
@ 2013-05-23 13:55       ` Daniel Schwierzeck
  2013-05-23 15:49         ` Tom Rini
  0 siblings, 1 reply; 16+ messages in thread
From: Daniel Schwierzeck @ 2013-05-23 13:55 UTC (permalink / raw)
  To: u-boot

Hi Tom, Wolfgang,

we do not have a dedicated PCI custodian so could you comment this
please? Thanks.

2013/5/23 Gabor Juhos <juhosg@openwrt.org>:
> Hi Daniel,
>
> Thank you for the review!
>
>> 2013/5/22 Gabor Juhos <juhosg@openwrt.org>:
>>> Qemu emulates the Galileo GT64120 System Controller
>>> which provides a CPU bus to PCI bus bridge.
>>>
>>> The patch adds driver for this bridge and enables
>>> PCI support for the emulated Malta board.
>>>
>>> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
>>> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
>>
>>
>> ELDK-5.3 shows some warnings:
>>
>> pci_indirect.c: In function 'indirect_read_config_byte':
>> pci_indirect.c:101:1: warning: implicit declaration of function
>> 'out_le32' [-Wimplicit-function-declaration]
>> pci_indirect.c:101:1: warning: implicit declaration of function 'in_8'
>> [-Wimplicit-function-declaration]
>> pci_indirect.c: In function 'indirect_read_config_word':
>> pci_indirect.c:102:1: warning: implicit declaration of function
>> 'in_le16' [-Wimplicit-function-declaration]
>> pci_indirect.c: In function 'indirect_read_config_dword':
>> pci_indirect.c:103:1: warning: implicit declaration of function
>> 'in_le32' [-Wimplicit-function-declaration]
>> pci_indirect.c: In function 'indirect_write_config_byte':
>> pci_indirect.c:109:1: warning: implicit declaration of function
>> 'out_8' [-Wimplicit-function-declaration]
>> pci_indirect.c: In function 'indirect_write_config_word':
>> pci_indirect.c:110:1: warning: implicit declaration of function
>> 'out_le16' [-Wimplicit-function-declaration]
>
> Hm, you are right. My toolchain also shows the warning but I did not notice
> those because I forgot to redirect stderr when I have generated the build logs.
>
> The pci_indirect.c file is always compiled when CONFIG_PCI is defined although
> it is not needed at all for Malta PCI support.
>
> The issue can be resolved on a few different ways:
>
> 1. Extend the '#if !defined(__I386__)' directive in pci_indirect.c with a new
> '&& !defined(__MIPS__)' condition. This would be the simplest solution but the
> drawback of this is that indirect support will not be usable on any MIPS board.
>
> 2. Introduce a new 'CONFIG_PCI_INDIRECT_BRIDGE' option and only compile the
> pci_indirect.c file if this option is present. Probably this is the best
> solution however the new symbol should be added into the configuration of the
> affected boards.
>
> 3. Introduce a new 'CONFIG_PCI_NO_INDIRECT_BRIDGE' option and use an '#ifndef
> CONFIG_PCI_NO_INDIRECT_BRIDGE' directive in pci_indirect.c.
>
> I'm unsure about which approach is preferred.
>

I favor the second option.

--
Best regards,
Daniel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 06/10] MIPS: qemu-malta: add PCI support
  2013-05-23 13:55       ` Daniel Schwierzeck
@ 2013-05-23 15:49         ` Tom Rini
  2013-05-24 18:55           ` Gabor Juhos
  0 siblings, 1 reply; 16+ messages in thread
From: Tom Rini @ 2013-05-23 15:49 UTC (permalink / raw)
  To: u-boot

On Thu, May 23, 2013 at 03:55:43PM +0200, Daniel Schwierzeck wrote:

> Hi Tom, Wolfgang,
> 
> we do not have a dedicated PCI custodian so could you comment this
> please? Thanks.
> 
> 2013/5/23 Gabor Juhos <juhosg@openwrt.org>:
> > Hi Daniel,
> >
> > Thank you for the review!
> >
> >> 2013/5/22 Gabor Juhos <juhosg@openwrt.org>:
> >>> Qemu emulates the Galileo GT64120 System Controller
> >>> which provides a CPU bus to PCI bus bridge.
> >>>
> >>> The patch adds driver for this bridge and enables
> >>> PCI support for the emulated Malta board.
> >>>
> >>> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
> >>> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
> >>
> >>
> >> ELDK-5.3 shows some warnings:
> >>
> >> pci_indirect.c: In function 'indirect_read_config_byte':
> >> pci_indirect.c:101:1: warning: implicit declaration of function
> >> 'out_le32' [-Wimplicit-function-declaration]
> >> pci_indirect.c:101:1: warning: implicit declaration of function 'in_8'
> >> [-Wimplicit-function-declaration]
> >> pci_indirect.c: In function 'indirect_read_config_word':
> >> pci_indirect.c:102:1: warning: implicit declaration of function
> >> 'in_le16' [-Wimplicit-function-declaration]
> >> pci_indirect.c: In function 'indirect_read_config_dword':
> >> pci_indirect.c:103:1: warning: implicit declaration of function
> >> 'in_le32' [-Wimplicit-function-declaration]
> >> pci_indirect.c: In function 'indirect_write_config_byte':
> >> pci_indirect.c:109:1: warning: implicit declaration of function
> >> 'out_8' [-Wimplicit-function-declaration]
> >> pci_indirect.c: In function 'indirect_write_config_word':
> >> pci_indirect.c:110:1: warning: implicit declaration of function
> >> 'out_le16' [-Wimplicit-function-declaration]
> >
> > Hm, you are right. My toolchain also shows the warning but I did not notice
> > those because I forgot to redirect stderr when I have generated the build logs.
> >
> > The pci_indirect.c file is always compiled when CONFIG_PCI is defined although
> > it is not needed at all for Malta PCI support.
> >
> > The issue can be resolved on a few different ways:
> >
> > 1. Extend the '#if !defined(__I386__)' directive in pci_indirect.c with a new
> > '&& !defined(__MIPS__)' condition. This would be the simplest solution but the
> > drawback of this is that indirect support will not be usable on any MIPS board.
> >
> > 2. Introduce a new 'CONFIG_PCI_INDIRECT_BRIDGE' option and only compile the
> > pci_indirect.c file if this option is present. Probably this is the best
> > solution however the new symbol should be added into the configuration of the
> > affected boards.
> >
> > 3. Introduce a new 'CONFIG_PCI_NO_INDIRECT_BRIDGE' option and use an '#ifndef
> > CONFIG_PCI_NO_INDIRECT_BRIDGE' directive in pci_indirect.c.
> >
> > I'm unsure about which approach is preferred.
> >
> 
> I favor the second option.

A quick check around in the kernel says that microblaze and powerpc have
similar type code and keep it under arch/ rather than drivers, but I'm
good with option #2.

-- 
Tom
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^ permalink raw reply	[flat|nested] 16+ messages in thread

* [U-Boot] [PATCH v3 06/10] MIPS: qemu-malta: add PCI support
  2013-05-23 15:49         ` Tom Rini
@ 2013-05-24 18:55           ` Gabor Juhos
  0 siblings, 0 replies; 16+ messages in thread
From: Gabor Juhos @ 2013-05-24 18:55 UTC (permalink / raw)
  To: u-boot

2013.05.23. 17:49 keltez?ssel, Tom Rini ?rta:

<...>

>>> The pci_indirect.c file is always compiled when CONFIG_PCI is defined
>>> although it is not needed at all for Malta PCI support.
>>> 
>>> The issue can be resolved on a few different ways:
>>> 
>>> 1. Extend the '#if !defined(__I386__)' directive in pci_indirect.c with
>>> a new '&& !defined(__MIPS__)' condition. This would be the simplest
>>> solution but the drawback of this is that indirect support will not be
>>> usable on any MIPS board.
>>> 
>>> 2. Introduce a new 'CONFIG_PCI_INDIRECT_BRIDGE' option and only compile
>>> the pci_indirect.c file if this option is present. Probably this is the
>>> best solution however the new symbol should be added into the
>>> configuration of the affected boards.
>>> 
>>> 3. Introduce a new 'CONFIG_PCI_NO_INDIRECT_BRIDGE' option and use an
>>> '#ifndef CONFIG_PCI_NO_INDIRECT_BRIDGE' directive in pci_indirect.c.
>>> 
>>> I'm unsure about which approach is preferred.
>>> 
>> 
>> I favor the second option.
> 
> A quick check around in the kernel says that microblaze and powerpc have 
> similar type code and keep it under arch/ rather than drivers, but I'm good
> with option #2.

Ok, I will create a patch for that.

Thanks,
Gabor

^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2013-05-24 18:55 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-05-22 13:57 [U-Boot] [PATCH v3 00/10] MIPS: initial support for emulated Malta board Gabor Juhos
2013-05-22 13:57 ` [U-Boot] [PATCH v3 01/10] MIPS: qemu-malta: add support for emulated MIPS " Gabor Juhos
2013-05-22 13:57 ` [U-Boot] [PATCH v3 02/10] MIPS: qemu-malta: add reset support Gabor Juhos
2013-05-22 13:57 ` [U-Boot] [PATCH v3 03/10] MIPS: qemu-malta: enable flash support Gabor Juhos
2013-05-22 13:57 ` [U-Boot] [PATCH v3 04/10] MIPS: import gt64120.h header from Linux Gabor Juhos
2013-05-22 13:57 ` [U-Boot] [PATCH v3 05/10] MIPS: qemu-malta: setup GT64120 registers as done by YAMON Gabor Juhos
2013-05-22 13:57 ` [U-Boot] [PATCH v3 06/10] MIPS: qemu-malta: add PCI support Gabor Juhos
2013-05-22 20:15   ` Daniel Schwierzeck
2013-05-23 11:59     ` Gabor Juhos
2013-05-23 13:55       ` Daniel Schwierzeck
2013-05-23 15:49         ` Tom Rini
2013-05-24 18:55           ` Gabor Juhos
2013-05-22 13:57 ` [U-Boot] [PATCH v3 07/10] net: pcnet: use pci_virt_to_mem to obtain buffer addresses Gabor Juhos
2013-05-22 13:57 ` [U-Boot] [PATCH v3 08/10] MIPS: qemu-malta: bring up ethernet Gabor Juhos
2013-05-22 13:57 ` [U-Boot] [PATCH v3 09/10] MIPS: bootm.c: add YAMON style Linux preparation/jump code Gabor Juhos
2013-05-22 13:57 ` [U-Boot] [PATCH v3 10/10] MIPS: start.S: emulate REVISION register for qemu-malta Gabor Juhos

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