[U-Boot] [Patch] fsl_esdhc: Fix DMA transfer completion waiting loop

Gabbasov, Andrew
2013-06-11T15:24:03Z

Hi Dirk,
________________________________________
> From: Behme, Dirk - Bosch
> Sent: Tuesday, June 11, 2013 12:16
> To: Gabbasov, Andrew
> Cc: u-boot at lists.denx.de; Stefano Babic; Fleming Andy-AFLEMING
> Subject: Re: [U-Boot] [Patch] fsl_esdhc: Fix DMA transfer completion waiting loop
>
> On 10.06.2013 16:51, Gabbasov, Andrew wrote:
> > Hi Dirk,

[ skipped ]

> >>
> >> I haven't tested this myself, but I got the following issue report
> >> regarding this patch:
> >>
> >> Using a SANDISK ULTRA II 8GB card (or alternatively Transcend 16GB or
> >> 32GB cards) and trying an mmc write [1] into the upper area of the 8GB
> >> card makes the write hang in 9 of 10 cases. Sometimes even more.
> >> Reverting this patch make these writes work again.
> >>
> >> mmc read does work fine, though. Even newer SANDISK Extreme III or
> >> several micro SD cards are working fine.
> >>
> >> Any idea?
> >>
> >> Best regards
> >>
> >> Dirk
> >
> > So far the only idea that comes into my mind is that DMA for some reason completes
> > its part of work too early so that the corresponding interrupt status bit appears and
> > has already been cleared even before entering this loop.
> >
> > I will be trying to reproduce the issue.
> >
> > Meanwhile, is it possible to ask the reporter (who obviously can reproduce it)
> > to try to add the debug print from the diff below and show what it prints when
> > the write command hangs and when it succeeds?
> >
> > Thanks.
> >
> > Best regards,
> > Andrew
> >
> > diff -u fsl_esdhc.c.orig fsl_esdhc.c
> > --- fsl_esdhc.c.orig 2013-05-30 03:48:26.000000000 -0500
> > +++ fsl_esdhc.c 2013-06-10 09:38:30.071905119 -0500
> > @@ -329,6 +329,7 @@
> >
> > irqstat = esdhc_read32(&regs->irqstat);
> > esdhc_write32(&regs->irqstat, irqstat);
> > + printf("fsl_esdhc: irqstat = 0x%08x\n", irqstat);
> >
> > /* Reset CMD and DATA portions on error */
> > if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
>
> 1. Sandisk 8GB Ultra 2 class 4 SDHC
>
> [ 23.967081] MMC write: dev # 0, block # 7400000, count 1 ...
> fsl_esdhc: irqstat = 0x00000001
> [ 23.977473] fsl_esdhc: irqstat = 0x00000009
> => hang
>
> With "fsl_esdhc: Fix DMA transfer completion waiting loop" reverted:
> [ 41.769231] MMC write: dev # 0, block # 7400000, count 1 ...
> fsl_esdhc: irqstat = 0x00000001
> [ 41.779622] fsl_esdhc: irqstat = 0x00000009
> [ 41.798490] fsl_esdhc: irqstat = 0x00000001
> [ 41.802593] 1 blocks write: OK
> => work
>
>
> 2. Sandisk 16GB Extreme class 10 (30MB/s)
>
> [ 45.871140] MMC write: dev # 0, block # 7400000, count 1 ...
> fsl_esdhc: irqstat = 0x00000001
> [ 45.881528] fsl_esdhc: irqstat = 0x00000001
> [ 46.054409] fsl_esdhc: irqstat = 0x00000001
> [ 46.058513] 1 blocks write: OK
> => work
>
> With "fsl_esdhc: Fix DMA transfer completion waiting loop" reverted:
> [ 17.901514] MMC write: dev # 0, block # 7400000, count 1 ...
> fsl_esdhc: irqstat = 0x00000001
> [ 17.911901] fsl_esdhc: irqstat = 0x00000001
> [ 18.081153] fsl_esdhc: irqstat = 0x00000001
> [ 18.085256] 1 blocks write: OK
> => work
>
> Best regards
>
> Dirk

Indeed, the DMA End interrupt bit appears in the register already by the time
of Command Complete event. Then, it gets cleared together with command-related
bits. So, the data completion waiting loop, that starts later, never gets it and waits forever.

One of solutions could be to explicitly clear only the command related bits (command complete
and may be command errors). However, it is easier just not clear the bits at all,
leave them all until the data part processing completes too, and clear the whole
register at once at the very end (which is being done anyway).

I'm submitting the patch removing clearing of interrupt status bits at that point. See Subject line
"fsl_esdhc: Do not clear interrupt status bits until data processed".

Thanks.

Best regards,
Andrew