[U-Boot] [Patch] fsl_esdhc: Fix DMA transfer completion waiting loop

Andrew Gabbasov
2013-04-08T09:06:08Z

Rework the waiting for transfer completion loop condition
to continue waiting until both Transfer Complete and DMA End
interrupts occur. Checking of DLA bit in Present State register
looks not needed in addition to interrupts status checking,
so it can be removed from the condition. Also, DMA Error
condition is added to the list of data errors, checked in the loop.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
---
drivers/mmc/fsl_esdhc.c | 3 +--
include/fsl_esdhc.h | 4 +++-
2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 54b5363..814bba4 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -400,8 +400,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)

if (irqstat & DATA_ERR)
return COMM_ERR;
- } while (!(irqstat & IRQSTAT_TC) &&
- (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
+ } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
#endif
}

diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 47d2fe4..ea0880b 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -63,7 +63,9 @@
#define IRQSTAT_CC (0x00000001)

#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
-#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE)
+#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
+ IRQSTAT_DMAE)
+#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)

#define IRQSTATEN 0x0002e034
#define IRQSTATEN_DMAE (0x10000000)
--
1.7.10.4