From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mike Dunn Date: Thu, 20 Jun 2013 10:04:00 -0700 Subject: [U-Boot] [PATCH] arm: fix memory coherency problem after relocation In-Reply-To: <201306201556.27564.marex@denx.de> References: <1371492435-14330-1-git-send-email-mikedunn@newsguy.com> <201306201556.27564.marex@denx.de> Message-ID: <51C33600.2070103@newsguy.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 06/20/2013 06:56 AM, Marek Vasut wrote: > Dear Mike Dunn, > >> On the xscale, the icache must be invalidated and the write buffers drained >> after writing code over the data bus, even if the caches are disabled. >> After rebasing with the main git repository, u-boot began crashing in odd >> places on my pxa270 board (palmtreo680) after the code relocation routine >> ran. This patch fixes it. Cache coherency problems are often >> hit-and-miss (ha ha), and this latent problem didn't rear its ugly head >> until now. Tested on the pxa270. >> >> Signed-off-by: Mike Dunn >> --- >> >> I realize that __ARM_ARCH_5TE__ does not necessarily mean xscale. > > We should introduce some CONFIG_PXA I guess. I think CONFIG_XSCALE is more correct, because if I'm not mistaken more recent Marvell processors continue to use the 'pxa' nomenclature in their name but do not contain xscale cores. I'll take a stab at a patch if you like. Maybe something like this macro in arch/arm/include/asm/arch-pxa/hardware.h /* * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected. * PXA300/310/320 all have distinct register mappings in some cases, that's why * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common * drivers and compatibility glue with old source then. */ #ifndef CONFIG_CPU_MONAHANS #if defined(CONFIG_CPU_PXA300) || \ defined(CONFIG_CPU_PXA310) || \ defined(CONFIG_CPU_PXA320) #define CONFIG_CPU_MONAHANS #endif #endif Thanks, Mike