* [U-Boot] [PATCH v4 1/3] Prepare for TI816X : reuse existing code from TI814X
[not found] <1371636501-23411-1-git-send-email-atenart@adeneo-embedded.com>
@ 2013-06-19 10:08 ` TENART Antoine
2013-06-25 19:59 ` Tom Rini
2013-06-19 10:08 ` [U-Boot] [PATCH v4 2/3] Add TI816X support TENART Antoine
2013-06-19 10:08 ` [U-Boot] [PATCH v4 3/3] Add TI816X evm board support TENART Antoine
2 siblings, 1 reply; 9+ messages in thread
From: TENART Antoine @ 2013-06-19 10:08 UTC (permalink / raw)
To: u-boot
Rename some CONFIG_TI814X to a more generic CONFIG_81XX
Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com>
---
Makefile | 2 +-
arch/arm/cpu/armv7/Makefile | 2 +-
arch/arm/cpu/armv7/omap-common/Makefile | 2 +-
arch/arm/include/asm/arch-am33xx/cpu.h | 2 +-
arch/arm/include/asm/arch-am33xx/omap.h | 2 +-
drivers/serial/ns16550.c | 4 ++--
spl/Makefile | 2 +-
7 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/Makefile b/Makefile
index 693b3f2..248b1f4 100644
--- a/Makefile
+++ b/Makefile
@@ -337,7 +337,7 @@ LIBS-y += api/libapi.o
LIBS-y += post/libpost.o
LIBS-y += test/libtest.o
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 7a8c2d0..415ace8 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS += cache_v7.o
COBJS += cpu.o
COBJS += syslib.o
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),)
SOBJS += lowlevel_init.o
endif
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index c4b9809..20586d3 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -37,7 +37,7 @@ COBJS += vc.o
COBJS += abb.o
endif
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),)
COBJS += boot-common.o
SOBJS += lowlevel_init.o
endif
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 3d3a7c8..13c0667 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -54,7 +54,7 @@
/* Reset control */
#ifdef CONFIG_AM33XX
#define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
-#elif defined(CONFIG_TI814X)
+#elif defined(CONFIG_TI81XX)
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
#endif
#define PRM_RSTST (PRM_RSTCTRL + 8)
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index e7576c1..777a456 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -32,7 +32,7 @@
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40310000
#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000
-#elif defined(CONFIG_TI814X)
+#elif defined(CONFIG_TI81XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000
#define SRAM_SCRATCH_SPACE_ADDR 0x4031B800
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index d77c25f..d659eb0 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -57,7 +57,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
- defined(CONFIG_AM33XX) || defined(CONFIG_TI814X)
+ defined(CONFIG_AM33XX) || defined(CONFIG_TI81XX)
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
@@ -72,7 +72,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out(UART_LCRVAL, &com_port->lcr);
#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
- defined(CONFIG_TI814X)
+ defined(CONFIG_TI81XX)
/* /16 is proper to hit 115200 with 48MHz */
serial_out(0, &com_port->mdr1);
diff --git a/spl/Makefile b/spl/Makefile
index d8fe948..3ea8ce0 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -84,7 +84,7 @@ LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o
LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o
LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v4 2/3] Add TI816X support
[not found] <1371636501-23411-1-git-send-email-atenart@adeneo-embedded.com>
2013-06-19 10:08 ` [U-Boot] [PATCH v4 1/3] Prepare for TI816X : reuse existing code from TI814X TENART Antoine
@ 2013-06-19 10:08 ` TENART Antoine
2013-06-25 19:59 ` Tom Rini
2013-06-19 10:08 ` [U-Boot] [PATCH v4 3/3] Add TI816X evm board support TENART Antoine
2 siblings, 1 reply; 9+ messages in thread
From: TENART Antoine @ 2013-06-19 10:08 UTC (permalink / raw)
To: u-boot
Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com>
---
arch/arm/cpu/armv7/am33xx/Makefile | 1 +
arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 95 ----
arch/arm/cpu/armv7/am33xx/clock_ti816x.c | 529 ++++++++++++++++++++
arch/arm/cpu/armv7/am33xx/emif4.c | 2 +
arch/arm/include/asm/arch-am33xx/clock.h | 4 +
arch/arm/include/asm/arch-am33xx/clock_ti81xx.h | 142 ++++++
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 35 +-
arch/arm/include/asm/arch-am33xx/hardware.h | 7 +-
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 5 +
arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 5 +
arch/arm/include/asm/arch-am33xx/hardware_ti816x.h | 57 +++
arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 3 +
arch/arm/include/asm/arch-am33xx/mux.h | 2 +
arch/arm/include/asm/arch-am33xx/mux_ti816x.h | 363 ++++++++++++++
arch/arm/include/asm/arch-am33xx/spl.h | 11 +-
15 files changed, 1147 insertions(+), 114 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock_ti816x.c
create mode 100644 arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti816x.h
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index c97e30d..703d7a2 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -18,6 +18,7 @@ LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_AM33XX) += clock_am33xx.o
COBJS-$(CONFIG_TI814X) += clock_ti814x.o
+COBJS-$(CONFIG_TI816X) += clock_ti816x.o
COBJS += sys_info.o
COBJS += mem.o
COBJS += ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index 8b2878d..f7181de 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -108,103 +108,8 @@ struct ad_pll {
#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
-/* PRCM */
#define ENET_CLKCTRL_CMPL 0x30000
-#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
-
-struct cm_def {
- unsigned int resv0[2];
- unsigned int l3fastclkstctrl;
- unsigned int resv1[1];
- unsigned int pciclkstctrl;
- unsigned int resv2[1];
- unsigned int ducaticlkstctrl;
- unsigned int resv3[1];
- unsigned int emif0clkctrl;
- unsigned int emif1clkctrl;
- unsigned int dmmclkctrl;
- unsigned int fwclkctrl;
- unsigned int resv4[10];
- unsigned int usbclkctrl;
- unsigned int resv5[1];
- unsigned int sataclkctrl;
- unsigned int resv6[4];
- unsigned int ducaticlkctrl;
- unsigned int pciclkctrl;
-};
-
-#define CM_ALWON_BASE (PRCM_BASE + 0x1400)
-
-struct cm_alwon {
- unsigned int l3slowclkstctrl;
- unsigned int ethclkstctrl;
- unsigned int l3medclkstctrl;
- unsigned int mmu_clkstctrl;
- unsigned int mmucfg_clkstctrl;
- unsigned int ocmc0clkstctrl;
- unsigned int vcpclkstctrl;
- unsigned int mpuclkstctrl;
- unsigned int sysclk4clkstctrl;
- unsigned int sysclk5clkstctrl;
- unsigned int sysclk6clkstctrl;
- unsigned int rtcclkstctrl;
- unsigned int l3fastclkstctrl;
- unsigned int resv0[67];
- unsigned int mcasp0clkctrl;
- unsigned int mcasp1clkctrl;
- unsigned int mcasp2clkctrl;
- unsigned int mcbspclkctrl;
- unsigned int uart0clkctrl;
- unsigned int uart1clkctrl;
- unsigned int uart2clkctrl;
- unsigned int gpio0clkctrl;
- unsigned int gpio1clkctrl;
- unsigned int i2c0clkctrl;
- unsigned int i2c1clkctrl;
- unsigned int mcasp345clkctrl;
- unsigned int atlclkctrl;
- unsigned int mlbclkctrl;
- unsigned int pataclkctrl;
- unsigned int resv1[1];
- unsigned int uart3clkctrl;
- unsigned int uart4clkctrl;
- unsigned int uart5clkctrl;
- unsigned int wdtimerclkctrl;
- unsigned int spiclkctrl;
- unsigned int mailboxclkctrl;
- unsigned int spinboxclkctrl;
- unsigned int mmudataclkctrl;
- unsigned int resv2[2];
- unsigned int mmucfgclkctrl;
- unsigned int resv3[2];
- unsigned int ocmc0clkctrl;
- unsigned int vcpclkctrl;
- unsigned int resv4[2];
- unsigned int controlclkctrl;
- unsigned int resv5[2];
- unsigned int gpmcclkctrl;
- unsigned int ethernet0clkctrl;
- unsigned int ethernet1clkctrl;
- unsigned int mpuclkctrl;
- unsigned int debugssclkctrl;
- unsigned int l3clkctrl;
- unsigned int l4hsclkctrl;
- unsigned int l4lsclkctrl;
- unsigned int rtcclkctrl;
- unsigned int tpccclkctrl;
- unsigned int tptc0clkctrl;
- unsigned int tptc1clkctrl;
- unsigned int tptc2clkctrl;
- unsigned int tptc3clkctrl;
- unsigned int resv7[4];
- unsigned int dcan01clkctrl;
- unsigned int mmchs0clkctrl;
- unsigned int mmchs1clkctrl;
- unsigned int mmchs2clkctrl;
- unsigned int custefuseclkctrl;
-};
-
#define SATA_PLL_BASE (CTRL_BASE + 0x0720)
struct sata_pll {
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
new file mode 100644
index 0000000..b6e9d07
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
@@ -0,0 +1,529 @@
+/*
+ * clock_ti816x.c
+ *
+ * Clocks for TI816X based boards
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * Copyright (C) 2009, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#include <asm/emif.h>
+
+#define CM_PLL_BASE (CTRL_BASE + 0x0400)
+
+/* Main PLL */
+#define MAIN_N 64
+#define MAIN_P 0x1
+#define MAIN_INTFREQ1 0x8
+#define MAIN_FRACFREQ1 0x800000
+#define MAIN_MDIV1 0x2
+#define MAIN_INTFREQ2 0xE
+#define MAIN_FRACFREQ2 0x0
+#define MAIN_MDIV2 0x1
+#define MAIN_INTFREQ3 0x8
+#define MAIN_FRACFREQ3 0xAAAAB0
+#define MAIN_MDIV3 0x3
+#define MAIN_INTFREQ4 0x9
+#define MAIN_FRACFREQ4 0x55554F
+#define MAIN_MDIV4 0x3
+#define MAIN_INTFREQ5 0x9
+#define MAIN_FRACFREQ5 0x374BC6
+#define MAIN_MDIV5 0xC
+#define MAIN_MDIV6 0x48
+#define MAIN_MDIV7 0x4
+
+/* DDR PLL */
+#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */
+#define DDR_N 59
+#define DDR_P 0x1
+#define DDR_MDIV1 0x4
+#define DDR_INTFREQ2 0x8
+#define DDR_FRACFREQ2 0xD99999
+#define DDR_MDIV2 0x1E
+#define DDR_INTFREQ3 0x8
+#define DDR_FRACFREQ3 0x0
+#define DDR_MDIV3 0x4
+#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4 0x0
+#define DDR_MDIV4 0x4
+#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5 0x0
+#define DDR_MDIV5 0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */
+#define DDR_N 59
+#define DDR_P 0x1
+#define DDR_MDIV1 0x3
+#define DDR_INTFREQ2 0x8
+#define DDR_FRACFREQ2 0xD99999
+#define DDR_MDIV2 0x1E
+#define DDR_INTFREQ3 0x8
+#define DDR_FRACFREQ3 0x0
+#define DDR_MDIV3 0x4
+#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4 0x0
+#define DDR_MDIV4 0x4
+#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5 0x0
+#define DDR_MDIV5 0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */
+#define DDR_N 50
+#define DDR_P 0x1
+#define DDR_MDIV1 0x2
+#define DDR_INTFREQ2 0x9
+#define DDR_FRACFREQ2 0x0
+#define DDR_MDIV2 0x19
+#define DDR_INTFREQ3 0x13
+#define DDR_FRACFREQ3 0x800000
+#define DDR_MDIV3 0x2
+#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4 0x0
+#define DDR_MDIV4 0x4
+#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5 0x0
+#define DDR_MDIV5 0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */
+#define DDR_N 59
+#define DDR_P 0x1
+#define DDR_MDIV1 0x2
+#define DDR_INTFREQ2 0x8
+#define DDR_FRACFREQ2 0xD99999
+#define DDR_MDIV2 0x1E
+#define DDR_INTFREQ3 0x8
+#define DDR_FRACFREQ3 0x0
+#define DDR_MDIV3 0x4
+#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4 0x0
+#define DDR_MDIV4 0x4
+#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5 0x0
+#define DDR_MDIV5 0x4
+#endif
+
+#define CONTROL_STATUS (CTRL_BASE + 0x40)
+#define DDR_RCD (CTRL_BASE + 0x070C)
+#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390)
+#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420)
+#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628)
+
+#define INTCPS_SYSCONFIG 0x48200010
+#define CM_SYSCLK10_CLKSEL 0x48180324
+
+/* WDT related */
+#define WDT_WDSC (WDT_BASE + 0x010)
+#define WDT_WDST (WDT_BASE + 0x014)
+#define WDT_WISR (WDT_BASE + 0x018)
+#define WDT_WIER (WDT_BASE + 0x01C)
+#define WDT_WWER (WDT_BASE + 0x020)
+#define WDT_WCLR (WDT_BASE + 0x024)
+#define WDT_WCRR (WDT_BASE + 0x028)
+#define WDT_WLDR (WDT_BASE + 0x02C)
+#define WDT_WTGR (WDT_BASE + 0x030)
+#define WDT_WWPS (WDT_BASE + 0x034)
+#define WDT_WDLY (WDT_BASE + 0x044)
+#define WDT_WSPR (WDT_BASE + 0x048)
+#define WDT_WIRQEOI (WDT_BASE + 0x050)
+#define WDT_WIRQSTATRAW (WDT_BASE + 0x054)
+#define WDT_WIRQSTAT (WDT_BASE + 0x058)
+#define WDT_WIRQENSET (WDT_BASE + 0x05C)
+#define WDT_WIRQENCLR (WDT_BASE + 0x060)
+#define WDT_UNFREEZE (CTRL_BASE + 0x100)
+
+struct cm_pll {
+ unsigned int mainpll_ctrl; /* offset 0x400 */
+ unsigned int mainpll_pwd;
+ unsigned int mainpll_freq1;
+ unsigned int mainpll_div1;
+ unsigned int mainpll_freq2;
+ unsigned int mainpll_div2;
+ unsigned int mainpll_freq3;
+ unsigned int mainpll_div3;
+ unsigned int mainpll_freq4;
+ unsigned int mainpll_div4;
+ unsigned int mainpll_freq5;
+ unsigned int mainpll_div5;
+ unsigned int resv0[1];
+ unsigned int mainpll_div6;
+ unsigned int resv1[1];
+ unsigned int mainpll_div7;
+ unsigned int ddrpll_ctrl; /* offset 0x440 */
+ unsigned int ddrpll_pwd;
+ unsigned int resv2[1];
+ unsigned int ddrpll_div1;
+ unsigned int ddrpll_freq2;
+ unsigned int ddrpll_div2;
+ unsigned int ddrpll_freq3;
+ unsigned int ddrpll_div3;
+ unsigned int ddrpll_freq4;
+ unsigned int ddrpll_div4;
+ unsigned int ddrpll_freq5;
+ unsigned int ddrpll_div5;
+ unsigned int videopll_ctrl; /* offset 0x470 */
+ unsigned int videopll_pwd;
+ unsigned int videopll_freq1;
+ unsigned int videopll_div1;
+ unsigned int videopll_freq2;
+ unsigned int videopll_div2;
+ unsigned int videopll_freq3;
+ unsigned int videopll_div3;
+ unsigned int resv3[4];
+ unsigned int audiopll_ctrl; /* offset 0x4A0 */
+ unsigned int audiopll_pwd;
+ unsigned int resv4[2];
+ unsigned int audiopll_freq2;
+ unsigned int audiopll_div2;
+ unsigned int audiopll_freq3;
+ unsigned int audiopll_div3;
+ unsigned int audiopll_freq4;
+ unsigned int audiopll_div4;
+ unsigned int audiopll_freq5;
+ unsigned int audiopll_div5;
+};
+
+const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
+const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
+
+const struct ddr_regs *ddr_reg[2] = {
+ (struct ddr_regs *)DDRPHY_0_CONFIG_BASE,
+ (struct ddr_regs *)DDRPHY_1_CONFIG_BASE,
+};
+
+/* needed by config_dmm() */
+void enable_dmm_clocks(void) {}
+
+void enable_emif_clocks(void)
+{
+ writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
+ writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
+ writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
+ while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
+ ;
+ while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
+ ;
+ while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
+ ;
+
+ writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
+ while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
+ ;
+
+ /* Enable Tiled Access */
+ writel(0x80000000, DMM_PAT_BASE_ADDR);
+}
+
+void ddr_pll_config(unsigned int pll)
+{
+ writel(0x5, &(ddr_reg[pll])->cm0config);
+ writel(0x5, &(ddr_reg[pll])->cm0configclk);
+ writel(0x5, &(ddr_reg[pll])->cm1config);
+ writel(0x5, &(ddr_reg[pll])->cm1configclk);
+ writel(0x5, &(ddr_reg[pll])->cm2config);
+ writel(0x5, &(ddr_reg[pll])->cm2configclk);
+}
+
+/* assume delay is aprox at least 1us */
+static void ddr_delay(int d)
+{
+ int i;
+
+ /*
+ * read a control module register.
+ * this is a bit more delay and cannot be optimized by the compiler
+ * assuming one read takes 200 cycles and A8 is runing 1 GHz
+ * somewhat conservative setting
+ */
+ for (i = 0; i < 50*d; i++)
+ readl(CONTROL_STATUS);
+}
+
+static void main_pll_init_ti816x(u32 sil_index, u32 clk_index)
+{
+ u32 main_pll_ctrl = 0;
+
+ /*
+ * Sequence to be followed:
+ * 1. Put the PLL in bypass mode by setting BIT2 in its ctrl reg
+ * 2. Write the values of N,P in the CTRL reg
+ * 3. Program the freq values, divider values for the required output
+ * in the Control module reg
+ * 4. Note: Loading the freq value requires a particular bit to be set
+ * in the freq reg.
+ * 4. Program the CM divider value in the CM module reg
+ * 5. Enable the PLL by setting the appropriate bit in the CTRL reg of
+ * the PLL
+ */
+
+ /* If the registers have been set by the ROM code dont do anything */
+
+ main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+ main_pll_ctrl &= 0xFFFFFFFB;
+ main_pll_ctrl |= 4;
+ writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+ main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+ main_pll_ctrl &= 0xFFFFFFF7;
+ main_pll_ctrl |= 8;
+ writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+ main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+ main_pll_ctrl &= 0xFF;
+ main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
+ writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+ writel(0x0, &cmpll->mainpll_pwd);
+
+ writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
+ &cmpll->mainpll_freq1);
+ writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
+
+ writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
+ &cmpll->mainpll_freq2);
+ writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
+
+ writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
+ &cmpll->mainpll_freq3);
+ writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
+
+ writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
+ &cmpll->mainpll_freq4);
+ writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
+
+ writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
+ &cmpll->mainpll_freq5);
+ writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
+
+ writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
+
+ writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
+
+ while ((readl(&cmpll->mainpll_ctrl) & 0x80) != 0x80)
+ ;
+
+ main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+ main_pll_ctrl &= 0xFFFFFFFB;
+
+ writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+}
+
+static void ddr_pll_init_ti816x(u32 sil_index, u32 clk_index)
+{
+ u32 ddr_pll_ctrl = 0;
+
+ /*
+ * Sequence to be followed:
+ * 1. Put the PLL in bypass mode by setting BIT2 in its ctrl reg
+ * 2. Write the values of N,P in the CTRL reg
+ * 3. Program the freq values, divider values for the required output
+ * in the Control module reg
+ * 4. Note: Loading the freq value requires a particular bit to be set
+ * in the freq reg.
+ * 5. Program the CM divider value in the CM module reg
+ * 6. Enable the PLL by setting the appropriate bit in the CTRL reg of
+ * the PLL
+ */
+
+ /* If the registers have been set by the ROM code dont do anything */
+
+ ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+ ddr_pll_ctrl &= 0xFFFFFFFB;
+ writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+ ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+ ddr_pll_ctrl &= 0xFFFFFFF7;
+ ddr_pll_ctrl |= 8;
+ writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+ ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+ ddr_pll_ctrl &= 0xFF;
+ ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
+ writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+ /* 10usec delay */
+ ddr_delay(10);
+
+ writel(0x0, &cmpll->ddrpll_pwd);
+
+ writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
+ ddr_delay(1);
+ writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
+
+ writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
+ &cmpll->ddrpll_freq2);
+ writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
+
+ writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
+ ddr_delay(1);
+ writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
+ ddr_delay(1);
+ writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
+ &cmpll->ddrpll_freq3);
+ ddr_delay(1);
+ writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
+ &cmpll->ddrpll_freq3);
+
+ ddr_delay(5);
+
+ /* Wait for PLL to lock */
+ while ((readl(&cmpll->ddrpll_ctrl) & 0x80) != 0x80)
+ ;
+
+ ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+ ddr_pll_ctrl &= 0xFFFFFFFB;
+ ddr_pll_ctrl |= 4;
+ writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+ writel(0x1, DDR_RCD);
+}
+static void peripheral_enable(void)
+{
+ /* DMTimers */
+ writel(0x2, &cmalwon->l3slowclkstctrl);
+
+ /*
+ * Note on Timers:
+ * There are 8 timers(0-7) out of which timer 0 is a secure timer.
+ * Timer 0 mux should not be changed
+ * For other timers, there are 3 inputs TCLKIN, 32KHz (external clk
+ * or SYSCLK18?) and CLKIN(27MHz)
+ * We select CLKIN and use that
+ */
+
+ /*
+ * First we need to enable the modules and setup the clk path
+ * Then the timers need to be configured by writing to their registers
+ * To access the timer registers we need the module to be
+ * enabled which is what we do in the first step
+ */
+
+ /* TIMER 1 */
+ writel(0x2, &cmalwon->timer1clkctrl);
+
+ /* Selects CLKIN (27MHz) */
+ writel(0x2, CM_TIMER1_CLKSEL);
+
+ while (((readl(&cmalwon->l3slowclkstctrl)
+ & (0x80000<<1)) >> (19+1)) != 1)
+ ;
+
+ while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
+ ;
+
+
+ writel(0x2, (DM_TIMER1_BASE + 0x54));
+ while (readl(DM_TIMER1_BASE + 0x10) & 1)
+ ;
+
+ writel(0x1, (DM_TIMER1_BASE + 0x38));
+
+ /* UARTs */
+ /* Note: The clock has been set to correct rate before this step */
+ writel(0x2, &cmalwon->uart0clkctrl);
+ while (readl(&cmalwon->uart0clkctrl) != 0x2)
+ ;
+
+ writel(0x2, &cmalwon->uart1clkctrl);
+ while (readl(&cmalwon->uart1clkctrl) != 0x2)
+ ;
+
+ writel(0x2, &cmalwon->uart2clkctrl);
+ while (readl(&cmalwon->uart2clkctrl) != 0x2)
+ ;
+
+ while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
+ ;
+
+ /* eFuse */
+ writel(0x2, CM_ALWON_CUST_EFUSE_CLKCTRL);
+ while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != 0x2)
+ ;
+
+ /* GPIO0 */
+ writel(0x2, &cmalwon->gpio0clkctrl);
+ while (readl(&cmalwon->gpio0clkctrl) != 0x2)
+ ;
+
+ writel((BIT(8)), &cmalwon->gpio0clkctrl);
+
+ /* SPI */
+ writel(0x2, &cmalwon->spiclkctrl);
+ while (readl(&cmalwon->spiclkctrl) != 0x2)
+ ;
+
+ /* I2C0 */
+ writel(0x2, &cmalwon->i2c0clkctrl);
+ while (readl(&cmalwon->i2c0clkctrl) != 0x2)
+ ;
+
+ /* Ethernet */
+ writel(0x2, &cmalwon->ethclkstctrl);
+ writel(0x2, &cmalwon->ethernet0clkctrl);
+ writel(0x2, &cmalwon->ethernet1clkctrl);
+
+ /* HSMMC */
+ writel(0x2, &cmalwon->sdioclkctrl);
+ while (readl(&cmalwon->sdioclkctrl) != 0x2)
+ ;
+
+ /*
+ * WDT
+ *
+ * For WDT to be functional, it needs to be first stopped by writing
+ * the pattern 0xAAAA followed by 0x5555 in the WDT start/stop register.
+ * After that a write-once register in Control module needs to
+ * be configured
+ * to unfreeze the timer.
+ * Note: It is important to stop the watchdog before unfreezing it
+ */
+ writel(0xAAAA, WDT_WSPR);
+ while (readl(WDT_WWPS) != 0x0)
+ ;
+ writel(0x5555, WDT_WSPR);
+ while (readl(WDT_WWPS) != 0x0)
+ ;
+
+ writel(0x2, WDT_UNFREEZE);
+}
+
+void pll_init(void)
+{
+ /* For future */
+ u32 clk_index = 0, sil_index = 0;
+
+ writel(0x2, INTCPS_SYSCONFIG);
+
+ /* Enable the control module */
+ writel(0x2, &cmalwon->controlclkctrl);
+
+ /* Fix ROM code bug - from TI-PSP-04.00.02.14 */
+ writel(0x0, CM_SYSCLK10_CLKSEL);
+
+ main_pll_init_ti816x(clk_index, sil_index);
+ ddr_pll_init_ti816x(clk_index, sil_index);
+
+ /*
+ * With clk freqs setup to desired values,
+ * enable the required peripherals
+ */
+ peripheral_enable();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index aa84e96..151fdf6 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -89,7 +89,9 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
{
enable_emif_clocks();
ddr_pll_config(pll);
+#ifndef CONFIG_TI816X
config_vtp(nr);
+#endif
config_cmd_ctrl(ctrl, nr);
config_ddr_data(data, nr);
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index ecb5901..5a96200 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -21,4 +21,8 @@
#include <asm/arch/clocks_am33xx.h>
+#ifdef CONFIG_TI81XX
+#include <asm/arch/clock_ti81xx.h>
+#endif
+
#endif
diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
new file mode 100644
index 0000000..f069922
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
@@ -0,0 +1,142 @@
+/*
+ * ti81xx.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef _CLOCK_TI81XX_H_
+#define _CLOCK_TI81XX_H_
+
+#define PRCM_MOD_EN 0x2
+
+#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
+#define CM_ALWON_BASE (PRCM_BASE + 0x1400)
+
+struct cm_def {
+ unsigned int resv0[2];
+ unsigned int l3fastclkstctrl;
+ unsigned int resv1[1];
+ unsigned int pciclkstctrl;
+ unsigned int resv2[1];
+ unsigned int ducaticlkstctrl;
+ unsigned int resv3[1];
+ unsigned int emif0clkctrl;
+ unsigned int emif1clkctrl;
+ unsigned int dmmclkctrl;
+ unsigned int fwclkctrl;
+ unsigned int resv4[10];
+ unsigned int usbclkctrl;
+ unsigned int resv5[1];
+ unsigned int sataclkctrl;
+ unsigned int resv6[4];
+ unsigned int ducaticlkctrl;
+ unsigned int pciclkctrl;
+};
+
+struct cm_alwon {
+ unsigned int l3slowclkstctrl;
+ unsigned int ethclkstctrl;
+ unsigned int l3medclkstctrl;
+ unsigned int mmu_clkstctrl;
+ unsigned int mmucfg_clkstctrl;
+ unsigned int ocmc0clkstctrl;
+#if defined(CONFIG_TI814X)
+ unsigned int vcpclkstctrl;
+#elif defined(CONFIG_TI816X)
+ unsigned int ocmc1clkstctrl;
+#endif
+ unsigned int mpuclkstctrl;
+ unsigned int sysclk4clkstctrl;
+ unsigned int sysclk5clkstctrl;
+ unsigned int sysclk6clkstctrl;
+ unsigned int rtcclkstctrl;
+ unsigned int l3fastclkstctrl;
+ unsigned int resv0[67];
+ unsigned int mcasp0clkctrl;
+ unsigned int mcasp1clkctrl;
+ unsigned int mcasp2clkctrl;
+ unsigned int mcbspclkctrl;
+ unsigned int uart0clkctrl;
+ unsigned int uart1clkctrl;
+ unsigned int uart2clkctrl;
+ unsigned int gpio0clkctrl;
+ unsigned int gpio1clkctrl;
+ unsigned int i2c0clkctrl;
+ unsigned int i2c1clkctrl;
+#if defined(CONFIG_TI814X)
+ unsigned int mcasp345clkctrl;
+ unsigned int atlclkctrl;
+ unsigned int mlbclkctrl;
+ unsigned int pataclkctrl;
+ unsigned int resv1[1];
+ unsigned int uart3clkctrl;
+ unsigned int uart4clkctrl;
+ unsigned int uart5clkctrl;
+#elif defined(CONFIG_TI816X)
+ unsigned int resv1[1];
+ unsigned int timer1clkctrl;
+ unsigned int timer2clkctrl;
+ unsigned int timer3clkctrl;
+ unsigned int timer4clkctrl;
+ unsigned int timer5clkctrl;
+ unsigned int timer6clkctrl;
+ unsigned int timer7clkctrl;
+#endif
+ unsigned int wdtimerclkctrl;
+ unsigned int spiclkctrl;
+ unsigned int mailboxclkctrl;
+ unsigned int spinboxclkctrl;
+ unsigned int mmudataclkctrl;
+ unsigned int resv2[2];
+ unsigned int mmucfgclkctrl;
+#if defined(CONFIG_TI814X)
+ unsigned int resv3[2];
+#elif defined(CONFIG_TI816X)
+ unsigned int resv3[1];
+ unsigned int sdioclkctrl;
+#endif
+ unsigned int ocmc0clkctrl;
+#if defined(CONFIG_TI814X)
+ unsigned int vcpclkctrl;
+#elif defined(CONFIG_TI816X)
+ unsigned int ocmc1clkctrl;
+#endif
+ unsigned int resv4[2];
+ unsigned int controlclkctrl;
+ unsigned int resv5[2];
+ unsigned int gpmcclkctrl;
+ unsigned int ethernet0clkctrl;
+ unsigned int ethernet1clkctrl;
+ unsigned int mpuclkctrl;
+#if defined(CONFIG_TI814X)
+ unsigned int debugssclkctrl;
+#elif defined(CONFIG_TI816X)
+ unsigned int resv6[1];
+#endif
+ unsigned int l3clkctrl;
+ unsigned int l4hsclkctrl;
+ unsigned int l4lsclkctrl;
+ unsigned int rtcclkctrl;
+ unsigned int tpccclkctrl;
+ unsigned int tptc0clkctrl;
+ unsigned int tptc1clkctrl;
+ unsigned int tptc2clkctrl;
+ unsigned int tptc3clkctrl;
+#if defined(CONFIG_TI814X)
+ unsigned int resv6[4];
+ unsigned int dcan01clkctrl;
+ unsigned int mmchs0clkctrl;
+ unsigned int mmchs1clkctrl;
+ unsigned int mmchs2clkctrl;
+ unsigned int custefuseclkctrl;
+#elif defined(CONFIG_TI816X)
+ unsigned int sr0clkctrl;
+ unsigned int sr1clkctrl;
+#endif
+};
+
+#endif /* _CLOCK_TI81XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index bb53a6a..374edbf 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -200,37 +200,46 @@ struct ddr_data_regs {
* correspond to DATA1 registers defined here.
*/
struct ddr_regs {
- unsigned int resv0[7];
- unsigned int cm0csratio; /* offset 0x01C */
+ unsigned int resv0[3];
+ unsigned int cm0config; /* offset 0x00C */
+ unsigned int cm0configclk; /* offset 0x010 */
unsigned int resv1[2];
+ unsigned int cm0csratio; /* offset 0x01C */
+ unsigned int resv2[2];
unsigned int cm0dldiff; /* offset 0x028 */
unsigned int cm0iclkout; /* offset 0x02C */
- unsigned int resv2[8];
+ unsigned int resv3[4];
+ unsigned int cm1config; /* offset 0x040 */
+ unsigned int cm1configclk; /* offset 0x044 */
+ unsigned int resv4[2];
unsigned int cm1csratio; /* offset 0x050 */
- unsigned int resv3[2];
+ unsigned int resv5[2];
unsigned int cm1dldiff; /* offset 0x05C */
unsigned int cm1iclkout; /* offset 0x060 */
- unsigned int resv4[8];
+ unsigned int resv6[4];
+ unsigned int cm2config; /* offset 0x074 */
+ unsigned int cm2configclk; /* offset 0x078 */
+ unsigned int resv7[2];
unsigned int cm2csratio; /* offset 0x084 */
- unsigned int resv5[2];
+ unsigned int resv8[2];
unsigned int cm2dldiff; /* offset 0x090 */
unsigned int cm2iclkout; /* offset 0x094 */
- unsigned int resv6[12];
+ unsigned int resv9[12];
unsigned int dt0rdsratio0; /* offset 0x0C8 */
- unsigned int resv7[4];
+ unsigned int resv10[4];
unsigned int dt0wdsratio0; /* offset 0x0DC */
- unsigned int resv8[4];
+ unsigned int resv11[4];
unsigned int dt0wiratio0; /* offset 0x0F0 */
- unsigned int resv9;
+ unsigned int resv12;
unsigned int dt0wimode0; /* offset 0x0F8 */
unsigned int dt0giratio0; /* offset 0x0FC */
- unsigned int resv10;
+ unsigned int resv13;
unsigned int dt0gimode0; /* offset 0x104 */
unsigned int dt0fwsratio0; /* offset 0x108 */
- unsigned int resv11[4];
+ unsigned int resv14[4];
unsigned int dt0dqoffset; /* offset 0x11C */
unsigned int dt0wrsratio0; /* offset 0x120 */
- unsigned int resv12[4];
+ unsigned int resv15[4];
unsigned int dt0rdelays0; /* offset 0x134 */
unsigned int dt0dldiff0; /* offset 0x138 */
};
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 5a27f9c..7f3b555 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -23,6 +23,8 @@
#include <asm/arch/omap.h>
#ifdef CONFIG_AM33XX
#include <asm/arch/hardware_am33xx.h>
+#elif defined(CONFIG_TI816X)
+#include <asm/arch/hardware_ti816x.h>
#elif defined(CONFIG_TI814X)
#include <asm/arch/hardware_ti814x.h>
#endif
@@ -67,15 +69,10 @@
/* DDR Base address */
#define DDR_CTRL_ADDR 0x44E10E04
#define DDR_CONTROL_BASE_ADDR 0x44E11404
-#define DDR_PHY_CMD_ADDR2 0x47C0C800
-#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
/* UART */
#define DEFAULT_UART_BASE UART0_BASE
-#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
-#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
-
/* GPMC Base address */
#define GPMC_BASE 0x50000000
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index fa02f19..553c3bd 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -43,8 +43,13 @@
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x44E12000
#define DDR_PHY_DATA_ADDR 0x44E120C8
+#define DDR_PHY_CMD_ADDR2 0x47C0C800
+#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
#define DDR_DATA_REGS_NR 2
+#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
+
/* CPSW Config space */
#define CPSW_MDIO_BASE 0x4A101000
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
index 8f9315c..e6cd3a3 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
@@ -43,8 +43,13 @@
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x47C0C400
#define DDR_PHY_DATA_ADDR 0x47C0C4C8
+#define DDR_PHY_CMD_ADDR2 0x47C0C800
+#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
#define DDR_DATA_REGS_NR 4
+#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
+
/* CPSW Config space */
#define CPSW_MDIO_BASE 0x4A100800
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
new file mode 100644
index 0000000..141b703
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
@@ -0,0 +1,57 @@
+/*
+ * hardware_ti816x.h
+ *
+ * TI816x hardware specific header
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ * Based on TI-PSP-04.00.02.14
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AM33XX_HARDWARE_TI816X_H
+#define __AM33XX_HARDWARE_TI816X_H
+
+/* Watchdog Timer */
+#define WDT_BASE 0x480C2000
+
+/* Control Module Base Address */
+#define CTRL_BASE 0x48140000
+
+/* PRCM Base Address */
+#define PRCM_BASE 0x48180000
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR 0x48198358
+#define VTP1_CTRL_ADDR 0x4819A358
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR 0x48198000
+#define DDR_PHY_DATA_ADDR 0x481980C8
+#define DDR_PHY_CMD_ADDR2 0x4819A000
+#define DDR_PHY_DATA_ADDR2 0x4819A0C8
+#define DDR_DATA_REGS_NR 4
+
+/* UART */
+#define UART0_BASE 0x48020000
+#define UART1_BASE 0x48022000
+#define UART2_BASE 0x48024000
+
+#define DDRPHY_0_CONFIG_BASE 0x48198000
+#define DDRPHY_1_CONFIG_BASE 0x4819A000
+#define DDRPHY_CONFIG_BASE ((emif == 0) ? \
+ DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
+
+/* RTC base address */
+#define RTC_BASE 0x480C0000
+
+#endif /* __AM33XX_HARDWARE_TI816X_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index 51ba791..724e252 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -27,6 +27,9 @@
#if defined(CONFIG_TI814X)
#undef MMC_CLOCK_REFERENCE
#define MMC_CLOCK_REFERENCE 192 /* MHz */
+#elif defined(CONFIG_TI816X)
+#undef MMC_CLOCK_REFERENCE
+#define MMC_CLOCK_REFERENCE 48 /* MHz */
#endif
#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index 1c6b65f..4caa4d8 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -23,6 +23,8 @@
#include <asm/arch/mux_am33xx.h>
#elif defined(CONFIG_TI814X)
#include <asm/arch/mux_ti814x.h>
+#elif defined(CONFIG_TI816X)
+#include <asm/arch/mux_ti816x.h>
#endif
struct module_pin_mux {
diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
new file mode 100644
index 0000000..e4e5a48
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
@@ -0,0 +1,363 @@
+/*
+ * mux_ti816x.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_TI816X_H_
+#define _MUX_TI816X_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset) \
+ __raw_writel(value, (CTRL_BASE + offset));
+
+#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */
+#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */
+#define PULLUDEN (0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
+#define MODE(val) (val) /* used for Readability */
+
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+ int pincntl1;
+ int pincntl2;
+ int pincntl3;
+ int pincntl4;
+ int pincntl5;
+ int pincntl6;
+ int pincntl7;
+ int pincntl8;
+ int pincntl9;
+ int pincntl10;
+ int pincntl11;
+ int pincntl12;
+ int pincntl13;
+ int pincntl14;
+ int pincntl15;
+ int pincntl16;
+ int pincntl17;
+ int pincntl18;
+ int pincntl19;
+ int pincntl20;
+ int pincntl21;
+ int pincntl22;
+ int pincntl23;
+ int pincntl24;
+ int pincntl25;
+ int pincntl26;
+ int pincntl27;
+ int pincntl28;
+ int pincntl29;
+ int pincntl30;
+ int pincntl31;
+ int pincntl32;
+ int pincntl33;
+ int pincntl34;
+ int pincntl35;
+ int pincntl36;
+ int pincntl37;
+ int pincntl38;
+ int pincntl39;
+ int pincntl40;
+ int pincntl41;
+ int pincntl42;
+ int pincntl43;
+ int pincntl44;
+ int pincntl45;
+ int pincntl46;
+ int pincntl47;
+ int pincntl48;
+ int pincntl49;
+ int pincntl50;
+ int pincntl51;
+ int pincntl52;
+ int pincntl53;
+ int pincntl54;
+ int pincntl55;
+ int pincntl56;
+ int pincntl57;
+ int pincntl58;
+ int pincntl59;
+ int pincntl60;
+ int pincntl61;
+ int pincntl62;
+ int pincntl63;
+ int pincntl64;
+ int pincntl65;
+ int pincntl66;
+ int pincntl67;
+ int pincntl68;
+ int pincntl69;
+ int pincntl70;
+ int pincntl71;
+ int pincntl72;
+ int pincntl73;
+ int pincntl74;
+ int pincntl75;
+ int pincntl76;
+ int pincntl77;
+ int pincntl78;
+ int pincntl79;
+ int pincntl80;
+ int pincntl81;
+ int pincntl82;
+ int pincntl83;
+ int pincntl84;
+ int pincntl85;
+ int pincntl86;
+ int pincntl87;
+ int pincntl88;
+ int pincntl89;
+ int pincntl90;
+ int pincntl91;
+ int pincntl92;
+ int pincntl93;
+ int pincntl94;
+ int pincntl95;
+ int pincntl96;
+ int pincntl97;
+ int pincntl98;
+ int pincntl99;
+ int pincntl100;
+ int pincntl101;
+ int pincntl102;
+ int pincntl103;
+ int pincntl104;
+ int pincntl105;
+ int pincntl106;
+ int pincntl107;
+ int pincntl108;
+ int pincntl109;
+ int pincntl110;
+ int pincntl111;
+ int pincntl112;
+ int pincntl113;
+ int pincntl114;
+ int pincntl115;
+ int pincntl116;
+ int pincntl117;
+ int pincntl118;
+ int pincntl119;
+ int pincntl120;
+ int pincntl121;
+ int pincntl122;
+ int pincntl123;
+ int pincntl124;
+ int pincntl125;
+ int pincntl126;
+ int pincntl127;
+ int pincntl128;
+ int pincntl129;
+ int pincntl130;
+ int pincntl131;
+ int pincntl132;
+ int pincntl133;
+ int pincntl134;
+ int pincntl135;
+ int pincntl136;
+ int pincntl137;
+ int pincntl138;
+ int pincntl139;
+ int pincntl140;
+ int pincntl141;
+ int pincntl142;
+ int pincntl143;
+ int pincntl144;
+ int pincntl145;
+ int pincntl146;
+ int pincntl147;
+ int pincntl148;
+ int pincntl149;
+ int pincntl150;
+ int pincntl151;
+ int pincntl152;
+ int pincntl153;
+ int pincntl154;
+ int pincntl155;
+ int pincntl156;
+ int pincntl157;
+ int pincntl158;
+ int pincntl159;
+ int pincntl160;
+ int pincntl161;
+ int pincntl162;
+ int pincntl163;
+ int pincntl164;
+ int pincntl165;
+ int pincntl166;
+ int pincntl167;
+ int pincntl168;
+ int pincntl169;
+ int pincntl170;
+ int pincntl171;
+ int pincntl172;
+ int pincntl173;
+ int pincntl174;
+ int pincntl175;
+ int pincntl176;
+ int pincntl177;
+ int pincntl178;
+ int pincntl179;
+ int pincntl180;
+ int pincntl181;
+ int pincntl182;
+ int pincntl183;
+ int pincntl184;
+ int pincntl185;
+ int pincntl186;
+ int pincntl187;
+ int pincntl188;
+ int pincntl189;
+ int pincntl190;
+ int pincntl191;
+ int pincntl192;
+ int pincntl193;
+ int pincntl194;
+ int pincntl195;
+ int pincntl196;
+ int pincntl197;
+ int pincntl198;
+ int pincntl199;
+ int pincntl200;
+ int pincntl201;
+ int pincntl202;
+ int pincntl203;
+ int pincntl204;
+ int pincntl205;
+ int pincntl206;
+ int pincntl207;
+ int pincntl208;
+ int pincntl209;
+ int pincntl210;
+ int pincntl211;
+ int pincntl212;
+ int pincntl213;
+ int pincntl214;
+ int pincntl215;
+ int pincntl216;
+ int pincntl217;
+ int pincntl218;
+ int pincntl219;
+ int pincntl220;
+ int pincntl221;
+ int pincntl222;
+ int pincntl223;
+ int pincntl224;
+ int pincntl225;
+ int pincntl226;
+ int pincntl227;
+ int pincntl228;
+ int pincntl229;
+ int pincntl230;
+ int pincntl231;
+ int pincntl232;
+ int pincntl233;
+ int pincntl234;
+ int pincntl235;
+ int pincntl236;
+ int pincntl237;
+ int pincntl238;
+ int pincntl239;
+ int pincntl240;
+ int pincntl241;
+ int pincntl242;
+ int pincntl243;
+ int pincntl244;
+ int pincntl245;
+ int pincntl246;
+ int pincntl247;
+ int pincntl248;
+ int pincntl249;
+ int pincntl250;
+ int pincntl251;
+ int pincntl252;
+ int pincntl253;
+ int pincntl254;
+ int pincntl255;
+ int pincntl256;
+ int pincntl257;
+ int pincntl258;
+ int pincntl259;
+ int pincntl260;
+ int pincntl261;
+ int pincntl262;
+ int pincntl263;
+ int pincntl264;
+ int pincntl265;
+ int pincntl266;
+ int pincntl267;
+ int pincntl268;
+ int pincntl269;
+ int pincntl270;
+ int pincntl271;
+ int pincntl272;
+ int pincntl273;
+ int pincntl274;
+ int pincntl275;
+ int pincntl276;
+ int pincntl277;
+ int pincntl278;
+ int pincntl279;
+ int pincntl280;
+ int pincntl281;
+ int pincntl282;
+ int pincntl283;
+ int pincntl284;
+ int pincntl285;
+ int pincntl286;
+ int pincntl287;
+ int pincntl288;
+ int pincntl289;
+ int pincntl290;
+ int pincntl291;
+ int pincntl292;
+ int pincntl293;
+ int pincntl294;
+ int pincntl295;
+ int pincntl296;
+ int pincntl297;
+ int pincntl298;
+ int pincntl299;
+ int pincntl300;
+ int pincntl301;
+ int pincntl302;
+ int pincntl303;
+ int pincntl304;
+ int pincntl305;
+ int pincntl306;
+ int pincntl307;
+ int pincntl308;
+ int pincntl309;
+ int pincntl310;
+ int pincntl311;
+ int pincntl312;
+ int pincntl313;
+ int pincntl314;
+ int pincntl315;
+ int pincntl316;
+ int pincntl317;
+ int pincntl318;
+ int pincntl319;
+ int pincntl320;
+ int pincntl321;
+ int pincntl322;
+ int pincntl323;
+};
+
+#endif /* endif _MUX_TI816X_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 4c23b27..6d7e8d6 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -23,6 +23,14 @@
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_SPL_H_
+#if defined(CONFIG_TI816X)
+#define BOOT_DEVICE_XIP 2
+#define BOOT_DEVICE_NAND 3
+#define BOOT_DEVICE_MMC1 6
+#define BOOT_DEVICE_MMC2 5
+#define BOOT_DEVICE_UART 0x43
+#define BOOT_DEVICE_MMC2_2 0xFF
+#else
#define BOOT_DEVICE_XIP 2
#define BOOT_DEVICE_NAND 5
#ifdef CONFIG_AM33XX
@@ -37,11 +45,12 @@
#define BOOT_DEVICE_USBETH 68
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
+#endif
#ifdef CONFIG_AM33XX
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
-#elif defined(CONFIG_TI814X)
+#elif defined(CONFIG_TI81XX)
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v4 2/3] Add TI816X support
2013-06-19 10:08 ` [U-Boot] [PATCH v4 2/3] Add TI816X support TENART Antoine
@ 2013-06-25 19:59 ` Tom Rini
2013-06-26 12:29 ` TENART Antoine
0 siblings, 1 reply; 9+ messages in thread
From: Tom Rini @ 2013-06-25 19:59 UTC (permalink / raw)
To: u-boot
On Wed, Jun 19, 2013 at 12:08:20PM +0200, TENART Antoine wrote:
[snip]
> +/* WDT related */
> +#define WDT_WDSC (WDT_BASE + 0x010)
> +#define WDT_WDST (WDT_BASE + 0x014)
> +#define WDT_WISR (WDT_BASE + 0x018)
> +#define WDT_WIER (WDT_BASE + 0x01C)
> +#define WDT_WWER (WDT_BASE + 0x020)
> +#define WDT_WCLR (WDT_BASE + 0x024)
> +#define WDT_WCRR (WDT_BASE + 0x028)
> +#define WDT_WLDR (WDT_BASE + 0x02C)
> +#define WDT_WTGR (WDT_BASE + 0x030)
> +#define WDT_WWPS (WDT_BASE + 0x034)
> +#define WDT_WDLY (WDT_BASE + 0x044)
> +#define WDT_WSPR (WDT_BASE + 0x048)
> +#define WDT_WIRQEOI (WDT_BASE + 0x050)
> +#define WDT_WIRQSTATRAW (WDT_BASE + 0x054)
> +#define WDT_WIRQSTAT (WDT_BASE + 0x058)
> +#define WDT_WIRQENSET (WDT_BASE + 0x05C)
> +#define WDT_WIRQENCLR (WDT_BASE + 0x060)
> +#define WDT_UNFREEZE (CTRL_BASE + 0x100)
This should be using a struct like the other platforms do for wdt.
[snip]
> +/* needed by config_dmm() */
> +void enable_dmm_clocks(void) {}
#ifndef the caller?
> +void ddr_pll_config(unsigned int pll)
> +{
> + writel(0x5, &(ddr_reg[pll])->cm0config);
Magic value (0x5).
[snip]
> + main_pll_ctrl &= 0xFFFFFFFB;
> + main_pll_ctrl |= 4;
More magic.
[snip]
> +static void peripheral_enable(void)
Lots more magic values in here.
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v4 2/3] Add TI816X support
2013-06-25 19:59 ` Tom Rini
@ 2013-06-26 12:29 ` TENART Antoine
0 siblings, 0 replies; 9+ messages in thread
From: TENART Antoine @ 2013-06-26 12:29 UTC (permalink / raw)
To: u-boot
> [snip]
>> +/* WDT related */
>> +#define WDT_WDSC (WDT_BASE + 0x010)
>> +#define WDT_WDST (WDT_BASE + 0x014)
>> +#define WDT_WISR (WDT_BASE + 0x018)
>> +#define WDT_WIER (WDT_BASE + 0x01C)
>> +#define WDT_WWER (WDT_BASE + 0x020)
>> +#define WDT_WCLR (WDT_BASE + 0x024)
>> +#define WDT_WCRR (WDT_BASE + 0x028)
>> +#define WDT_WLDR (WDT_BASE + 0x02C)
>> +#define WDT_WTGR (WDT_BASE + 0x030)
>> +#define WDT_WWPS (WDT_BASE + 0x034)
>> +#define WDT_WDLY (WDT_BASE + 0x044)
>> +#define WDT_WSPR (WDT_BASE + 0x048)
>> +#define WDT_WIRQEOI (WDT_BASE + 0x050)
>> +#define WDT_WIRQSTATRAW (WDT_BASE + 0x054)
>> +#define WDT_WIRQSTAT (WDT_BASE + 0x058)
>> +#define WDT_WIRQENSET (WDT_BASE + 0x05C)
>> +#define WDT_WIRQENCLR (WDT_BASE + 0x060)
>> +#define WDT_UNFREEZE (CTRL_BASE + 0x100)
>
> This should be using a struct like the other platforms do for wdt.
I'll do that and use the wd_timer structure.
>
> [snip]
>> +/* needed by config_dmm() */
>> +void enable_dmm_clocks(void) {}
>
> #ifndef the caller?
>
Yes.
>> +void ddr_pll_config(unsigned int pll)
>> +{
>> + writel(0x5,&(ddr_reg[pll])->cm0config);
>
> Magic value (0x5).
I'll fix it.
>
> [snip]
>> + main_pll_ctrl&= 0xFFFFFFFB;
>> + main_pll_ctrl |= 4;
>
> More magic.
This one is already explained in the beginning of the function. I'll put
a per instruction comment instead.
>
> [snip]
>> +static void peripheral_enable(void)
>
> Lots more magic values in here.
>
I'll remove the magic.
--
Antoine
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v4 3/3] Add TI816X evm board support
[not found] <1371636501-23411-1-git-send-email-atenart@adeneo-embedded.com>
2013-06-19 10:08 ` [U-Boot] [PATCH v4 1/3] Prepare for TI816X : reuse existing code from TI814X TENART Antoine
2013-06-19 10:08 ` [U-Boot] [PATCH v4 2/3] Add TI816X support TENART Antoine
@ 2013-06-19 10:08 ` TENART Antoine
2013-06-25 20:03 ` Tom Rini
2013-06-26 13:16 ` Lokesh Vutla
2 siblings, 2 replies; 9+ messages in thread
From: TENART Antoine @ 2013-06-19 10:08 UTC (permalink / raw)
To: u-boot
Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com>
---
MAINTAINERS | 4 +
board/ti/ti816x/Makefile | 47 ++++++++
board/ti/ti816x/evm.c | 249 ++++++++++++++++++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/ti816x_evm.h | 188 +++++++++++++++++++++++++++++++
5 files changed, 489 insertions(+)
create mode 100644 board/ti/ti816x/Makefile
create mode 100644 board/ti/ti816x/evm.c
create mode 100644 include/configs/ti816x_evm.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 7820375..38ff5c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -940,6 +940,10 @@ Lucas Stach <dev@lynxeye.de>
colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core)
+Antoine Tenart <atenart@adeneo-embedded.com>
+
+ TI816X ARM ARMV7 (TI816x Soc)
+
Nick Thompson <nick.thompson@gefanuc.com>
da830evm ARM926EJS (DA830/OMAP-L137)
diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
new file mode 100644
index 0000000..dc23d93
--- /dev/null
+++ b/board/ti/ti816x/Makefile
@@ -0,0 +1,47 @@
+#
+# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+# Antoine Tenart, <atenart@adeneo-embedded.com>
+#
+# Based on TI-PSP-04.00.02.14 :
+#
+# Copyright (C) 2009, Texas Instruments, Incorporated
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation version 2.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := evm.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
new file mode 100644
index 0000000..12e98d5
--- /dev/null
+++ b/board/ti/ti816x/evm.c
@@ -0,0 +1,249 @@
+/*
+ * evm.c
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+
+static struct module_pin_mux mmc_pin_mux[] = {
+ { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
+ { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { -1 },
+};
+
+const struct dmm_lisa_map_regs evm_lisa_map_regs = {
+ .dmm_lisa_map_0 = 0x00000000,
+ .dmm_lisa_map_1 = 0x00000000,
+ .dmm_lisa_map_2 = 0x80640300,
+ .dmm_lisa_map_3 = 0xC0640320,
+};
+
+/*
+ * DDR2 related definitions
+ */
+
+static struct ddr_data ddr2_data = {
+ .datardsratio0 = ((0x40<<10) | (0x40<<0)),
+ .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)),
+ .datawiratio0 = ((0x0<<10) | (0x0<<0)),
+ .datagiratio0 = ((0x0<<10) | (0x0<<0)),
+ .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)),
+ .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)),
+ .datauserank0delay = 0x1,
+ .datadldiff0 = 0x0, /* depend on cpu rev, set later */
+};
+
+static struct cmd_control ddr2_ctrl = {
+ .cmd0csratio = 0x80,
+ .cmd0dldiff = 0x04, /* reset value is 0x4 */
+ .cmd0iclkout = 0x00,
+
+ .cmd1csratio = 0x80,
+ .cmd1dldiff = 0x04,
+ .cmd1iclkout = 0x00,
+
+ .cmd2csratio = 0x80,
+ .cmd2dldiff = 0x04,
+ .cmd2iclkout = 0x00,
+
+};
+
+static struct emif_regs ddr2_emif0_regs = {
+ .sdram_config = 0x43801A3A,
+ .ref_ctrl = 0x10000C30,
+ .sdram_tim1 = 0x0AAB15E2,
+ .sdram_tim2 = 0x423631D2,
+ .sdram_tim3 = 0x0080032F,
+ .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
+};
+
+static struct emif_regs ddr2_emif1_regs = {
+ .sdram_config = 0x43801A3A,
+ .ref_ctrl = 0x10000C30,
+ .sdram_tim1 = 0x0AAB15E2,
+ .sdram_tim2 = 0x423631D2,
+ .sdram_tim3 = 0x0080032F,
+ .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
+};
+
+/*
+ * DDR3 related definitions
+ */
+
+#if defined(CONFIG_TI816X_DDR_PLL_400)
+#define RD_DQS 0x03B
+#define WR_DQS 0x0A6
+#define RD_DQS_GATE 0x12A
+#define EMIF_SDCFG 0x62A41032
+#define EMIF_SDREF 0x10000C30
+#define EMIF_TIM1 0x0CCCE524
+#define EMIF_TIM2 0x30308023
+#define EMIF_TIM3 0x009F82CF
+#define EMIF_PHYCFG 0x0000010B
+#elif defined(CONFIG_TI816X_DDR_PLL_531)
+#define RD_DQS 0x039
+#define WR_DQS 0x0B4
+#define RD_DQS_GATE 0x13D
+#define EMIF_SDCFG 0x62A51832
+#define EMIF_SDREF 0x1000102E
+#define EMIF_TIM1 0x0EF136AC
+#define EMIF_TIM2 0x30408063
+#define EMIF_TIM3 0x009F83AF
+#define EMIF_PHYCFG 0x0000010C
+#elif defined(CONFIG_TI816X_DDR_PLL_675)
+#define RD_DQS 0x039
+#define WR_DQS 0x091
+#define RD_DQS_GATE 0x196
+#define EMIF_SDCFG 0x62A63032
+#define EMIF_SDREF 0x10001491
+#define EMIF_TIM1 0x13358875
+#define EMIF_TIM2 0x5051806C
+#define EMIF_TIM3 0x009F84AF
+#define EMIF_PHYCFG 0x0000010F
+#elif defined(CONFIG_TI816X_DDR_PLL_796)
+#define RD_DQS 0x035
+#define WR_DQS 0x093
+#define RD_DQS_GATE 0x1B3
+#define EMIF_SDCFG 0x62A73832
+#define EMIF_SDREF 0x10001841
+#define EMIF_TIM1 0x1779C9FE
+#define EMIF_TIM2 0x50608074
+#define EMIF_TIM3 0x009F857F
+#define EMIF_PHYCFG 0x00000110
+#endif
+
+static struct ddr_data ddr3_data = {
+ .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
+ .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
+ .datawiratio0 = ((0x20<<10) | 0x20<<0),
+ .datagiratio0 = ((0x20<<10) | 0x20<<0),
+ .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
+ .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
+ .datauserank0delay = 0x1,
+ .datadldiff0 = 0x0, /* depend on cpu rev, set later */
+};
+
+static const struct cmd_control ddr3_ctrl = {
+ .cmd0csratio = 0x100,
+ .cmd0dldiff = 0x004, /* reset value is 0x4 */
+ .cmd0iclkout = 0x001,
+
+ .cmd1csratio = 0x100,
+ .cmd1dldiff = 0x004,
+ .cmd1iclkout = 0x001,
+
+ .cmd2csratio = 0x100,
+ .cmd2dldiff = 0x004,
+ .cmd2iclkout = 0x001,
+};
+
+static const struct emif_regs ddr3_emif0_regs = {
+ .sdram_config = EMIF_SDCFG,
+ .ref_ctrl = EMIF_SDREF,
+ .sdram_tim1 = EMIF_TIM1,
+ .sdram_tim2 = EMIF_TIM2,
+ .sdram_tim3 = EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
+};
+
+static const struct emif_regs ddr3_emif1_regs = {
+ .sdram_config = EMIF_SDCFG,
+ .ref_ctrl = EMIF_SDREF,
+ .sdram_tim1 = EMIF_TIM1,
+ .sdram_tim2 = EMIF_TIM2,
+ .sdram_tim3 = EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
+};
+#endif /* CONFIG_SPL_BUILD */
+
+
+void s_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_ARCH_CPU_INIT
+ /*
+ * Save the boot parameters passed by romcode.
+ * Do it first to prevent overwrites.
+ */
+ save_omap_boot_params();
+#endif
+
+ pll_init();
+
+ configure_module_pin_mux(mmc_pin_mux);
+
+ gd = &gdata;
+
+ preloader_console_init();
+
+#ifdef CONFIG_TI816X_EVM_DDR2
+ ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
+ ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
+ ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
+ ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
+
+ if (CONFIG_TI816X_USE_EMIF0) {
+ ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
+ (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
+ config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0);
+ }
+
+ if (CONFIG_TI816X_USE_EMIF1) {
+ ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
+ (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
+ config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1);
+ }
+#endif
+
+#ifdef CONFIG_TI816X_EVM_DDR3
+ ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
+
+ if (CONFIG_TI816X_USE_EMIF0)
+ config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
+
+ if (CONFIG_TI816X_USE_EMIF1)
+ config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 1);
+#endif
+
+ config_dmm(&evm_lisa_map_regs);
+#endif
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ return 0;
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 1e598cb..95e19a1 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -250,6 +250,7 @@ am335x_evm_uart4 arm armv7 am335x ti
am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6
am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT
ti814x_evm arm armv7 ti814x ti am33xx
+ti816x_evm arm armv7 ti816x ti am33xx
pcm051 arm armv7 pcm051 phytec am33xx pcm051
sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC
sama5d3xek_nandflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
new file mode 100644
index 0000000..93ad74c
--- /dev/null
+++ b/include/configs/ti816x_evm.h
@@ -0,0 +1,188 @@
+/*
+ * ti816x_evm.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef __CONFIG_TI816X_EVM_H
+#define __CONFIG_TI816X_EVM_H
+
+#define CONFIG_TI81XX
+#define CONFIG_TI816X
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_OMAP
+
+#define CONFIG_ARCH_CPU_INIT
+
+#include <asm/arch/omap.h>
+
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024))
+#define CONFIG_SYS_LONGHELP /* undef save memory */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "u-boot/ti816x# "
+#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG /* required for ramdisk support */
+
+#include <config_cmd_default.h> /* u-boot default commands */
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=yes\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc rescan 0;" \
+ "fatload mmc 0 0x81000000 uImage;" \
+ "bootm 0x81000000"
+
+#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
+
+/*
+ * Memtest works on 8 MB in DRAM after skipping 32MB
+ * from start addr of ram disk
+ */
+#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64*1024*1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ + (8*1024*1024))
+
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
+#define CONFIG_SYS_HZ 1000 /* 1ms clock */
+
+#define CONFIG_CMD_ASKEN
+#define CONFIG_CMD_ECHO
+#define CONFIG_OMAP_GPIO
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_FS_FAT
+
+/*
+ * Only one of the following two options (DDR3/DDR2) should be enabled
+ * CONFIG_TI816X_EVM_DDR2
+ * CONFIG_TI816X_EVM_DDR3
+ */
+#define CONFIG_TI816X_EVM_DDR3
+
+/*
+ * Supported values: 400, 531, 675 or 796 MHz
+ */
+#define CONFIG_TI816X_DDR_PLL_796
+
+#define CONFIG_TI816X_USE_EMIF0 1
+#define CONFIG_TI816X_USE_EMIF1 1
+
+
+#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
+#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
+#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
+#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
+#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
+
+#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
+ GENERATED_GBL_DATA_SIZE)
+
+/**
+ * Platform/Board specific defs
+ */
+#define CONFIG_SYS_CLK_FREQ 27000000
+#define CONFIG_SYS_TIMERBASE 0x4802E000
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+
+#undef CONFIG_NAND_OMAP_GPMC
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK (48000000)
+#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
+
+#define CONFIG_BAUDRATE 115200
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SERIAL1
+#define CONFIG_SERIAL2
+#define CONFIG_SERIAL3
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x40400000
+#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SYS_TEXT_BASE 0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+
+/* Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v4 3/3] Add TI816X evm board support
2013-06-19 10:08 ` [U-Boot] [PATCH v4 3/3] Add TI816X evm board support TENART Antoine
@ 2013-06-25 20:03 ` Tom Rini
2013-06-26 12:30 ` TENART Antoine
2013-06-26 13:16 ` Lokesh Vutla
1 sibling, 1 reply; 9+ messages in thread
From: Tom Rini @ 2013-06-25 20:03 UTC (permalink / raw)
To: u-boot
On Wed, Jun 19, 2013 at 12:08:21PM +0200, TENART Antoine wrote:
> Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com>
[snip]
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "verify=yes\0"
Do we really want that?
[snip]
> +/*
> + * Memtest works on 8 MB in DRAM after skipping 32MB
> + * from start addr of ram disk
> + */
> +#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64*1024*1024))
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
> + + (8*1024*1024))
mtest isn't on by default anymore, see doc/README.memory-test
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v4 3/3] Add TI816X evm board support
2013-06-25 20:03 ` Tom Rini
@ 2013-06-26 12:30 ` TENART Antoine
0 siblings, 0 replies; 9+ messages in thread
From: TENART Antoine @ 2013-06-26 12:30 UTC (permalink / raw)
To: u-boot
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> + "verify=yes\0"
>
> Do we really want that?
I don't think so. This will be removed.
>> +/*
>> + * Memtest works on 8 MB in DRAM after skipping 32MB
>> + * from start addr of ram disk
>> + */
>> +#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64*1024*1024))
>> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
>> + + (8*1024*1024))
>
> mtest isn't on by default anymore, see doc/README.memory-test
I'll remove that too.
--
Antoine
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v4 3/3] Add TI816X evm board support
2013-06-19 10:08 ` [U-Boot] [PATCH v4 3/3] Add TI816X evm board support TENART Antoine
2013-06-25 20:03 ` Tom Rini
@ 2013-06-26 13:16 ` Lokesh Vutla
1 sibling, 0 replies; 9+ messages in thread
From: Lokesh Vutla @ 2013-06-26 13:16 UTC (permalink / raw)
To: u-boot
Hi Antoine,
On Wednesday 19 June 2013 03:38 PM, TENART Antoine wrote:
> Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com>
> ---
> MAINTAINERS | 4 +
> board/ti/ti816x/Makefile | 47 ++++++++
> board/ti/ti816x/evm.c | 249 ++++++++++++++++++++++++++++++++++++++++++
> boards.cfg | 1 +
> include/configs/ti816x_evm.h | 188 +++++++++++++++++++++++++++++++
> 5 files changed, 489 insertions(+)
> create mode 100644 board/ti/ti816x/Makefile
> create mode 100644 board/ti/ti816x/evm.c
> create mode 100644 include/configs/ti816x_evm.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7820375..38ff5c3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -940,6 +940,10 @@ Lucas Stach <dev@lynxeye.de>
>
> colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core)
>
> +Antoine Tenart <atenart@adeneo-embedded.com>
> +
> + TI816X ARM ARMV7 (TI816x Soc)
> +
> Nick Thompson <nick.thompson@gefanuc.com>
>
> da830evm ARM926EJS (DA830/OMAP-L137)
> diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
> new file mode 100644
> index 0000000..dc23d93
> --- /dev/null
> +++ b/board/ti/ti816x/Makefile
> @@ -0,0 +1,47 @@
> +#
> +# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
> +# Antoine Tenart, <atenart@adeneo-embedded.com>
> +#
> +# Based on TI-PSP-04.00.02.14 :
> +#
> +# Copyright (C) 2009, Texas Instruments, Incorporated
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation version 2.
> +#
> +# This program is distributed "as is" WITHOUT ANY WARRANTY of any
> +# kind, whether express or implied; without even the implied warranty
> +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS := evm.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +
> +$(LIB): $(obj).depend $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +clean:
> + rm -f $(OBJS)
> +
> +distclean: clean
> + rm -f $(LIB) core *.bak $(obj).depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
> new file mode 100644
> index 0000000..12e98d5
> --- /dev/null
> +++ b/board/ti/ti816x/evm.c
> @@ -0,0 +1,249 @@
> +/*
> + * evm.c
> + *
> + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
> + * Antoine Tenart, <atenart@adeneo-embedded.com>
> + *
> + * This file is released under the terms of GPL v2 and any later version.
> + * See the file COPYING in the root directory of the source tree for details.
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <asm/cache.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/ddr_defs.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/arch/mmc_host_def.h>
> +#include <asm/arch/mem.h>
> +#include <asm/arch/mux.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_init(void)
> +{
> + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
> + return 0;
> +}
> +
> +#if defined(CONFIG_SPL_BUILD)
> +
> +static struct module_pin_mux mmc_pin_mux[] = {
> + { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
> + { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
> + { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
> + { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
> + { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
> + { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
> + { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
> + { -1 },
> +};
> +
> +const struct dmm_lisa_map_regs evm_lisa_map_regs = {
> + .dmm_lisa_map_0 = 0x00000000,
> + .dmm_lisa_map_1 = 0x00000000,
> + .dmm_lisa_map_2 = 0x80640300,
> + .dmm_lisa_map_3 = 0xC0640320,
> +};
> +
> +/*
> + * DDR2 related definitions
> + */
> +
> +static struct ddr_data ddr2_data = {
> + .datardsratio0 = ((0x40<<10) | (0x40<<0)),
> + .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)),
> + .datawiratio0 = ((0x0<<10) | (0x0<<0)),
> + .datagiratio0 = ((0x0<<10) | (0x0<<0)),
> + .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)),
> + .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)),
> + .datauserank0delay = 0x1,
> + .datadldiff0 = 0x0, /* depend on cpu rev, set later */
> +};
> +
> +static struct cmd_control ddr2_ctrl = {
> + .cmd0csratio = 0x80,
> + .cmd0dldiff = 0x04, /* reset value is 0x4 */
> + .cmd0iclkout = 0x00,
> +
> + .cmd1csratio = 0x80,
> + .cmd1dldiff = 0x04,
> + .cmd1iclkout = 0x00,
> +
> + .cmd2csratio = 0x80,
> + .cmd2dldiff = 0x04,
> + .cmd2iclkout = 0x00,
> +
> +};
> +
> +static struct emif_regs ddr2_emif0_regs = {
> + .sdram_config = 0x43801A3A,
> + .ref_ctrl = 0x10000C30,
> + .sdram_tim1 = 0x0AAB15E2,
> + .sdram_tim2 = 0x423631D2,
> + .sdram_tim3 = 0x0080032F,
> + .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
> +};
> +
> +static struct emif_regs ddr2_emif1_regs = {
> + .sdram_config = 0x43801A3A,
> + .ref_ctrl = 0x10000C30,
> + .sdram_tim1 = 0x0AAB15E2,
> + .sdram_tim2 = 0x423631D2,
> + .sdram_tim3 = 0x0080032F,
> + .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
> +};
> +
> +/*
> + * DDR3 related definitions
> + */
> +
> +#if defined(CONFIG_TI816X_DDR_PLL_400)
> +#define RD_DQS 0x03B
> +#define WR_DQS 0x0A6
> +#define RD_DQS_GATE 0x12A
> +#define EMIF_SDCFG 0x62A41032
> +#define EMIF_SDREF 0x10000C30
> +#define EMIF_TIM1 0x0CCCE524
> +#define EMIF_TIM2 0x30308023
> +#define EMIF_TIM3 0x009F82CF
> +#define EMIF_PHYCFG 0x0000010B
> +#elif defined(CONFIG_TI816X_DDR_PLL_531)
> +#define RD_DQS 0x039
> +#define WR_DQS 0x0B4
> +#define RD_DQS_GATE 0x13D
> +#define EMIF_SDCFG 0x62A51832
> +#define EMIF_SDREF 0x1000102E
> +#define EMIF_TIM1 0x0EF136AC
> +#define EMIF_TIM2 0x30408063
> +#define EMIF_TIM3 0x009F83AF
> +#define EMIF_PHYCFG 0x0000010C
> +#elif defined(CONFIG_TI816X_DDR_PLL_675)
> +#define RD_DQS 0x039
> +#define WR_DQS 0x091
> +#define RD_DQS_GATE 0x196
> +#define EMIF_SDCFG 0x62A63032
> +#define EMIF_SDREF 0x10001491
> +#define EMIF_TIM1 0x13358875
> +#define EMIF_TIM2 0x5051806C
> +#define EMIF_TIM3 0x009F84AF
> +#define EMIF_PHYCFG 0x0000010F
> +#elif defined(CONFIG_TI816X_DDR_PLL_796)
> +#define RD_DQS 0x035
> +#define WR_DQS 0x093
> +#define RD_DQS_GATE 0x1B3
> +#define EMIF_SDCFG 0x62A73832
> +#define EMIF_SDREF 0x10001841
> +#define EMIF_TIM1 0x1779C9FE
> +#define EMIF_TIM2 0x50608074
> +#define EMIF_TIM3 0x009F857F
> +#define EMIF_PHYCFG 0x00000110
> +#endif
> +
> +static struct ddr_data ddr3_data = {
> + .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
> + .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
> + .datawiratio0 = ((0x20<<10) | 0x20<<0),
> + .datagiratio0 = ((0x20<<10) | 0x20<<0),
> + .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
> + .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
> + .datauserank0delay = 0x1,
> + .datadldiff0 = 0x0, /* depend on cpu rev, set later */
> +};
> +
> +static const struct cmd_control ddr3_ctrl = {
> + .cmd0csratio = 0x100,
> + .cmd0dldiff = 0x004, /* reset value is 0x4 */
> + .cmd0iclkout = 0x001,
> +
> + .cmd1csratio = 0x100,
> + .cmd1dldiff = 0x004,
> + .cmd1iclkout = 0x001,
> +
> + .cmd2csratio = 0x100,
> + .cmd2dldiff = 0x004,
> + .cmd2iclkout = 0x001,
> +};
> +
> +static const struct emif_regs ddr3_emif0_regs = {
> + .sdram_config = EMIF_SDCFG,
> + .ref_ctrl = EMIF_SDREF,
> + .sdram_tim1 = EMIF_TIM1,
> + .sdram_tim2 = EMIF_TIM2,
> + .sdram_tim3 = EMIF_TIM3,
> + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
> +};
> +
> +static const struct emif_regs ddr3_emif1_regs = {
> + .sdram_config = EMIF_SDCFG,
> + .ref_ctrl = EMIF_SDREF,
> + .sdram_tim1 = EMIF_TIM1,
> + .sdram_tim2 = EMIF_TIM2,
> + .sdram_tim3 = EMIF_TIM3,
> + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
> +};
> +#endif /* CONFIG_SPL_BUILD */
> +
> +
> +void s_init(void)
> +{
> +#ifdef CONFIG_SPL_BUILD
> +#ifdef CONFIG_ARCH_CPU_INIT
> + /*
> + * Save the boot parameters passed by romcode.
> + * Do it first to prevent overwrites.
> + */
> + save_omap_boot_params();
> +#endif
> +
> + pll_init();
> +
> + configure_module_pin_mux(mmc_pin_mux);
> +
> + gd = &gdata;
> +
> + preloader_console_init();
> +
> +#ifdef CONFIG_TI816X_EVM_DDR2
> + ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
> + ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
> + ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
> + ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
> +
> + if (CONFIG_TI816X_USE_EMIF0) {
> + ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
> + (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
> + config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0);
> + }
> +
> + if (CONFIG_TI816X_USE_EMIF1) {
> + ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
> + (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
> + config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1);
> + }
> +#endif
> +
> +#ifdef CONFIG_TI816X_EVM_DDR3
> + ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
> +
> + if (CONFIG_TI816X_USE_EMIF0)
> + config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
> +
> + if (CONFIG_TI816X_USE_EMIF1)
> + config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 1);
> +#endif
> +
> + config_dmm(&evm_lisa_map_regs);
> +#endif
> +}
Please rebase your patches on top of the following series.
http://u-boot.10912.n7.nabble.com/PATCH-0-4-ARM-AM33xx-Cleanup-clocks-and-hwinit-tt157703.html
There are already s_init() function present commonly, you can reuse
these functions from the above series.
Thanks and regards,
Lokesh
> +
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
> +int board_mmc_init(bd_t *bis)
> +{
> + omap_mmc_init(0, 0, 0, -1, -1);
> + return 0;
> +}
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 1e598cb..95e19a1 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -250,6 +250,7 @@ am335x_evm_uart4 arm armv7 am335x ti
> am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6
> am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT
> ti814x_evm arm armv7 ti814x ti am33xx
> +ti816x_evm arm armv7 ti816x ti am33xx
> pcm051 arm armv7 pcm051 phytec am33xx pcm051
> sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC
> sama5d3xek_nandflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH
> diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
> new file mode 100644
> index 0000000..93ad74c
> --- /dev/null
> +++ b/include/configs/ti816x_evm.h
> @@ -0,0 +1,188 @@
> +/*
> + * ti816x_evm.h
> + *
> + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
> + * Antoine Tenart, <atenart@adeneo-embedded.com>
> + *
> + * This file is released under the terms of GPL v2 and any later version.
> + * See the file COPYING in the root directory of the source tree for details.
> + */
> +
> +#ifndef __CONFIG_TI816X_EVM_H
> +#define __CONFIG_TI816X_EVM_H
> +
> +#define CONFIG_TI81XX
> +#define CONFIG_TI816X
> +#define CONFIG_SYS_NO_FLASH
> +#define CONFIG_OMAP
> +
> +#define CONFIG_ARCH_CPU_INIT
> +
> +#include <asm/arch/omap.h>
> +
> +#define CONFIG_ENV_SIZE 0x2000
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024))
> +#define CONFIG_SYS_LONGHELP /* undef save memory */
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT "u-boot/ti816x# "
> +#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
> +
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG /* required for ramdisk support */
> +
> +#include <config_cmd_default.h> /* u-boot default commands */
> +
> +#define CONFIG_VERSION_VARIABLE
> +#define CONFIG_DISPLAY_CPUINFO
> +
> +#define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "verify=yes\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> + "mmc rescan 0;" \
> + "fatload mmc 0 0x81000000 uImage;" \
> + "bootm 0x81000000"
> +
> +#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
> +
> +/* Clock Defines */
> +#define V_OSCK 24000000 /* Clock output from T2 */
> +#define V_SCLK (V_OSCK >> 1)
> +
> +#define CONFIG_SYS_MAXARGS 32
> +#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
> + + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
> +
> +/*
> + * Memtest works on 8 MB in DRAM after skipping 32MB
> + * from start addr of ram disk
> + */
> +#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64*1024*1024))
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
> + + (8*1024*1024))
> +
> +#undef CONFIG_SYS_CLKS_IN_HZ
> +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
> +#define CONFIG_SYS_HZ 1000 /* 1ms clock */
> +
> +#define CONFIG_CMD_ASKEN
> +#define CONFIG_CMD_ECHO
> +#define CONFIG_OMAP_GPIO
> +#define CONFIG_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_OMAP_HSMMC
> +#define CONFIG_CMD_MMC
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_EXT2
> +
> +#define CONFIG_FS_FAT
> +
> +/*
> + * Only one of the following two options (DDR3/DDR2) should be enabled
> + * CONFIG_TI816X_EVM_DDR2
> + * CONFIG_TI816X_EVM_DDR3
> + */
> +#define CONFIG_TI816X_EVM_DDR3
> +
> +/*
> + * Supported values: 400, 531, 675 or 796 MHz
> + */
> +#define CONFIG_TI816X_DDR_PLL_796
> +
> +#define CONFIG_TI816X_USE_EMIF0 1
> +#define CONFIG_TI816X_USE_EMIF1 1
> +
> +
> +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
> +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
> +#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
> +#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
> +#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
> +
> +#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
> +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
> +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
> + GENERATED_GBL_DATA_SIZE)
> +
> +/**
> + * Platform/Board specific defs
> + */
> +#define CONFIG_SYS_CLK_FREQ 27000000
> +#define CONFIG_SYS_TIMERBASE 0x4802E000
> +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
> +
> +#undef CONFIG_NAND_OMAP_GPMC
> +
> +/*
> + * NS16550 Configuration
> + */
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE (-4)
> +#define CONFIG_SYS_NS16550_CLK (48000000)
> +#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
> +
> +#define CONFIG_BAUDRATE 115200
> +
> +/* allow overwriting serial config and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define CONFIG_SERIAL1
> +#define CONFIG_SERIAL2
> +#define CONFIG_SERIAL3
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_SYS_CONSOLE_INFO_QUIET
> +
> +#define CONFIG_ENV_IS_NOWHERE
> +
> +/* SPL */
> +/* Defines for SPL */
> +#define CONFIG_SPL
> +#define CONFIG_SPL_FRAMEWORK
> +#define CONFIG_SPL_TEXT_BASE 0x40400000
> +#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
> +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
> +
> +#define CONFIG_SPL_BSS_START_ADDR 0x80000000
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
> +
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
> +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
> +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
> +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SPL_FAT_SUPPORT
> +
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBDISK_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SPL_GPIO_SUPPORT
> +#define CONFIG_SPL_YMODEM_SUPPORT
> +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
> +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
> +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
> +
> +#define CONFIG_SPL_BOARD_INIT
> +
> +#define CONFIG_SYS_TEXT_BASE 0x80800000
> +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
> +
> +/* Since SPL did pll and ddr initialization for us,
> + * we don't need to do it twice.
> + */
> +#ifndef CONFIG_SPL_BUILD
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#endif
> +
> +/* Unsupported features */
> +#undef CONFIG_USE_IRQ
> +
> +#endif
>
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