From mboxrd@z Thu Jan 1 00:00:00 1970 From: Minkyu Kang Date: Thu, 27 Jun 2013 17:27:05 +0900 Subject: [U-Boot] [PATCH 4/4] EXYNOS: Move files from board/samsung to arch/arm. In-Reply-To: <1366869439-9695-5-git-send-email-rajeshwari.s@samsung.com> References: <1366869439-9695-1-git-send-email-rajeshwari.s@samsung.com> <1366869439-9695-5-git-send-email-rajeshwari.s@samsung.com> Message-ID: <51CBF759.2070505@samsung.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 25/04/13 14:57, Rajeshwari Shinde wrote: > This patch performs the following: > > 1) Convert the assembly code for memory and clock initialization to C code. > 2) Move the memory and clock init codes from board/samsung to arch/arm > 3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted > the common lowlevel_init from assembly to C-code > 4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5. > 5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already > done in _main. > 6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250. > > TEST: Tested SD-MMC boot on SMDK5250 and Origen. > Tested USB and SPI boot on SMDK5250 > Compile tested for SMDKV310. > > Signed-off-by: Hatim Ali > Signed-off-by: Rajeshwari Shinde > --- > arch/arm/cpu/armv7/exynos/Makefile | 14 +- > .../arm/cpu/armv7/exynos}/clock_init.h | 0 > arch/arm/cpu/armv7/exynos/clock_init_exynos4.c | 63 +++ > .../arm/cpu/armv7/exynos/clock_init_exynos5.c | 26 +- > arch/arm/cpu/armv7/exynos/common_setup.h | 44 ++ > .../arm/cpu/armv7/exynos}/dmc_common.c | 7 +- > .../arm/cpu/armv7/exynos}/dmc_init_ddr3.c | 17 +- > arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c | 294 ++++++++++++ > .../arm/cpu/armv7/exynos/exynos4_setup.h | 72 +++- > .../arm/cpu/armv7/exynos/exynos5_setup.h | 53 +-- > arch/arm/cpu/armv7/exynos/lowlevel_init.c | 72 +++ > .../arm/cpu/armv7/exynos}/spl_boot.c | 90 +++- > .../arm/cpu/armv7/exynos}/tzpc_init.c | 17 +- > arch/arm/include/asm/arch-exynos/spl.h | 1 + > arch/arm/include/asm/arch-exynos/tzpc.h | 28 ++ > board/samsung/origen/Makefile | 7 - > board/samsung/origen/lowlevel_init.S | 397 ----------------- > board/samsung/origen/mem_setup.S | 421 ------------------ > board/samsung/origen/mmc_boot.c | 58 --- > board/samsung/smdk5250/Makefile | 9 - > board/samsung/smdk5250/lowlevel_init.S | 2 + > board/samsung/smdkv310/Makefile | 10 +- > board/samsung/smdkv310/lowlevel_init.S | 470 -------------------- > board/samsung/smdkv310/mem_setup.S | 365 --------------- > board/samsung/smdkv310/mmc_boot.c | 60 --- > include/configs/exynos5250-dt.h | 12 +- > include/configs/origen.h | 9 +- > include/configs/smdkv310.h | 8 +- > spl/Makefile | 4 + > 29 files changed, 728 insertions(+), 1902 deletions(-) > rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/clock_init.h (100%) > create mode 100644 arch/arm/cpu/armv7/exynos/clock_init_exynos4.c > rename board/samsung/smdk5250/clock_init.c => arch/arm/cpu/armv7/exynos/clock_init_exynos5.c (97%) > create mode 100644 arch/arm/cpu/armv7/exynos/common_setup.h > rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/dmc_common.c (97%) > rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/dmc_init_ddr3.c (96%) > create mode 100644 arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c > rename board/samsung/origen/origen_setup.h => arch/arm/cpu/armv7/exynos/exynos4_setup.h (89%) > rename board/samsung/smdk5250/setup.h => arch/arm/cpu/armv7/exynos/exynos5_setup.h (93%) > create mode 100644 arch/arm/cpu/armv7/exynos/lowlevel_init.c > rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/spl_boot.c (61%) > rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/tzpc_init.c (81%) > delete mode 100644 board/samsung/origen/lowlevel_init.S > delete mode 100644 board/samsung/origen/mem_setup.S > delete mode 100644 board/samsung/origen/mmc_boot.c > delete mode 100644 board/samsung/smdkv310/lowlevel_init.S > delete mode 100644 board/samsung/smdkv310/mem_setup.S > delete mode 100644 board/samsung/smdkv310/mmc_boot.c > > diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile > index 9119961..c419248 100644 > --- a/arch/arm/cpu/armv7/exynos/Makefile > +++ b/arch/arm/cpu/armv7/exynos/Makefile > @@ -22,8 +22,18 @@ include $(TOPDIR)/config.mk > > LIB = $(obj)lib$(SOC).o > > -COBJS += clock.o power.o soc.o system.o pinmux.o > - > +COBJS-y += clock.o power.o soc.o system.o pinmux.o tzpc_init.o > + > +COBJS-$(CONFIG_EXYNOS5) += clock_init_exynos5.o > +COBJS-$(CONFIG_EXYNOS4210)+= clock_init_exynos4.o Do not need to init the clock always. > +ifdef CONFIG_SPL_BUILD > +COBJS-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o > +COBJS-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o > +COBJS-y += spl_boot.o > +COBJS-y += lowlevel_init.o > +endif > + > +COBJS := $(COBJS-y) > SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) > > diff --git a/board/samsung/smdk5250/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h > similarity index 100% > rename from board/samsung/smdk5250/clock_init.h > rename to arch/arm/cpu/armv7/exynos/clock_init.h > diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c > new file mode 100644 > index 0000000..509c344 > --- /dev/null > +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c > @@ -0,0 +1,63 @@ missing copyright. > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "common_setup.h" > +#include "exynos4_setup.h" > + > +/* > + * system_clock_init: Initialize core clock and bus clock. > + * void system_clock_init(void) > + */ > +void system_clock_init(void) > +{ > + struct exynos4_clock *clk = (struct exynos4_clock *)EXYNOS4_CLOCK_BASE; blank line here. > + writel(CLK_SRC_CPU_VAL, &clk->src_cpu); here. > + sdelay(0x10000); here. > + writel(CLK_SRC_TOP0_VAL, &clk->src_top0); > + writel(CLK_SRC_TOP1_VAL, &clk->src_top1); > + writel(CLK_SRC_DMC_VAL, &clk->src_dmc); > + writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus); > + writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus); > + writel(CLK_SRC_FSYS_VAL, &clk->src_fsys); > + writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0); > + writel(CLK_SRC_CAM_VAL, &clk->src_cam); > + writel(CLK_SRC_MFC_VAL, &clk->src_mfc); > + writel(CLK_SRC_G3D_VAL, &clk->src_g3d); > + writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0); here. > + sdelay(0x10000); here. > + writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); > + writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); > + writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0); > + writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1); > + writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus); > + writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus); > + writel(CLK_DIV_TOP_VAL, &clk->div_top); > + writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); > + writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); > + writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3); > + writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0); > + writel(CLK_DIV_CAM_VAL, &clk->div_cam); > + writel(CLK_DIV_MFC_VAL, &clk->div_mfc); > + writel(CLK_DIV_G3D_VAL, &clk->div_g3d); > + writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0); > + > + /* Set PLL locktime */ > + writel(PLL_LOCKTIME, &clk->apll_lock); > + writel(PLL_LOCKTIME, &clk->mpll_lock); > + writel(PLL_LOCKTIME, &clk->epll_lock); > + writel(PLL_LOCKTIME, &clk->vpll_lock); > + > + writel(APLL_CON1_VAL, &clk->apll_con1); > + writel(APLL_CON0_VAL, &clk->apll_con0); > + writel(MPLL_CON1_VAL, &clk->mpll_con1); > + writel(MPLL_CON0_VAL, &clk->mpll_con0); > + writel(EPLL_CON1_VAL, &clk->epll_con1); > + writel(EPLL_CON0_VAL, &clk->epll_con0); > + writel(VPLL_CON1_VAL, &clk->vpll_con1); > + writel(VPLL_CON0_VAL, &clk->vpll_con0); > + sdelay(0x30000); > +} > diff --git a/board/samsung/smdk5250/clock_init.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c > similarity index 97% > rename from board/samsung/smdk5250/clock_init.c > rename to arch/arm/cpu/armv7/exynos/clock_init_exynos5.c > index 5b9e82f..ffec5d0 100644 > --- a/board/samsung/smdk5250/clock_init.c > +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c > @@ -30,7 +30,7 @@ > #include > > #include "clock_init.h" > -#include "setup.h" > +#include "exynos5_setup.h" > > DECLARE_GLOBAL_DATA_PTR; > > @@ -210,10 +210,10 @@ struct mem_timings mem_timings[] = { > DMC_MEMCONTROL_BL_8 | > DMC_MEMCONTROL_PZQ_DISABLE | > DMC_MEMCONTROL_MRR_BYTE_7_0, > - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | > - DMC_MEMCONFIGx_CHIP_COL_10 | > - DMC_MEMCONFIGx_CHIP_ROW_15 | > - DMC_MEMCONFIGx_CHIP_BANK_8, > + .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED | what X means? > + DMC_MEMCONFIGX_CHIP_COL_10 | > + DMC_MEMCONFIGX_CHIP_ROW_15 | > + DMC_MEMCONFIGX_CHIP_BANK_8, > .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), > .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), > .prechconfig_tp_cnt = 0xff, > @@ -313,10 +313,10 @@ struct mem_timings mem_timings[] = { > DMC_MEMCONTROL_BL_8 | > DMC_MEMCONTROL_PZQ_DISABLE | > DMC_MEMCONTROL_MRR_BYTE_7_0, > - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | > - DMC_MEMCONFIGx_CHIP_COL_10 | > - DMC_MEMCONFIGx_CHIP_ROW_15 | > - DMC_MEMCONFIGx_CHIP_BANK_8, > + .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED | > + DMC_MEMCONFIGX_CHIP_COL_10 | > + DMC_MEMCONFIGX_CHIP_ROW_15 | > + DMC_MEMCONFIGX_CHIP_BANK_8, > .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), > .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), > .prechconfig_tp_cnt = 0xff, > @@ -373,7 +373,7 @@ struct arm_clk_ratios *get_arm_ratios(void) > int i; > > if (clock_get_mem_selection(&mem_type, &frequency_mhz, > - &arm_freq, &mem_manuf)) > + &arm_freq, &mem_manuf)) why did you use space here? > ; > for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); > i++, arm_ratio++) { > @@ -397,12 +397,12 @@ struct mem_timings *clock_get_mem_timings(void) > int i; > > if (!clock_get_mem_selection(&mem_type, &frequency_mhz, > - &arm_freq, &mem_manuf)) { > + &arm_freq, &mem_manuf)) { ditto. > for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); > i++, mem++) { > if (mem->mem_type == mem_type && > - mem->frequency_mhz == frequency_mhz && > - mem->mem_manuf == mem_manuf) > + mem->frequency_mhz == frequency_mhz && > + mem->mem_manuf == mem_manuf) ditto. > return mem; > } > } > diff --git a/arch/arm/cpu/armv7/exynos/common_setup.h b/arch/arm/cpu/armv7/exynos/common_setup.h > new file mode 100644 > index 0000000..a225f70 > --- /dev/null > +++ b/arch/arm/cpu/armv7/exynos/common_setup.h > @@ -0,0 +1,44 @@ > +/* > + * Common APIs for EXYNOS based board > + * > + * Copyright (C) 2013 Samsung Electronics missing authors. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +/* > + * Memory initialization > + * > + * @param reset Reset PHY during initialization. > + */ > +void mem_ctrl_init(int reset); > + > +/* > + * System Clock initialization > + */ Should be /* System..... */ > +void system_clock_init(void); > + > +/** /** ? > + * Init subsystems according to the reset status > + * > + * @return 0 for a normal boot, non-zero for a resume > + */ > +int do_lowlevel_init(void); > + > +void sdelay(unsigned long); > diff --git a/board/samsung/smdk5250/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c > similarity index 97% > rename from board/samsung/smdk5250/dmc_common.c > rename to arch/arm/cpu/armv7/exynos/dmc_common.c > index 109602a..645f57e 100644 > --- a/board/samsung/smdk5250/dmc_common.c > +++ b/arch/arm/cpu/armv7/exynos/dmc_common.c > @@ -26,7 +26,8 @@ > #include > > #include "clock_init.h" > -#include "setup.h" > +#include "common_setup.h" > +#include "exynos5_setup.h" > > #define ZQ_INIT_TIMEOUT 10000 > > @@ -175,7 +176,7 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc) > writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1); > } > > -void mem_ctrl_init() > +void mem_ctrl_init(int reset) > { > struct spl_machine_param *param = spl_get_machine_params(); > struct mem_timings *mem; > @@ -185,7 +186,7 @@ void mem_ctrl_init() > > /* If there are any other memory variant, add their init call below */ > if (param->mem_type == DDR_MODE_DDR3) { > - ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size); > + ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset); > if (ret) { > /* will hang if failed to init memory control */ > while (1) > diff --git a/board/samsung/smdk5250/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c > similarity index 96% > rename from board/samsung/smdk5250/dmc_init_ddr3.c > rename to arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c > index e050790..348bba9 100644 > --- a/board/samsung/smdk5250/dmc_init_ddr3.c > +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c > @@ -27,7 +27,8 @@ > #include > #include > #include > -#include "setup.h" > +#include "exynos5_setup.h" > +#include "common_setup.h" > #include "clock_init.h" > > #define RDLVL_COMPLETE_TIMEOUT 10000 > @@ -40,7 +41,8 @@ static void reset_phy_ctrl(void) > writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); > } > > -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) > +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, > + int reset) > { > unsigned int val; > struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; > @@ -51,7 +53,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) > phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE; > dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE; > > - reset_phy_ctrl(); > + if (reset) > + reset_phy_ctrl(); > > /* Set Impedance Output Driver */ > val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | > @@ -100,14 +103,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) > > /* Start DLL locking */ > writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), > - &phy0_ctrl->phy_con12); > + &phy0_ctrl->phy_con12); why? > writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), > - &phy1_ctrl->phy_con12); > + &phy1_ctrl->phy_con12); ditto. > > update_reset_dll(dmc, DDR_MODE_DDR3); > > writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), > - &dmc->concontrol); > + &dmc->concontrol); ditto. > > /* Memory Channel Inteleaving Size */ > writel(mem->iv_size, &dmc->ivcontrol); > @@ -119,7 +122,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) > > /* Precharge Configuration */ > writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, > - &dmc->prechconfig); > + &dmc->prechconfig); ditto. > > /* Power Down mode Configuration */ > writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | > diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c b/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c > new file mode 100644 > index 0000000..e69ed04 > --- /dev/null > +++ b/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c > @@ -0,0 +1,294 @@ > +/* > + * Memory setup for ORIGEN board based on EXYNOS4210 > + * > + * Copyright (C) 2011 Samsung Electronics missing authors. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include > +#include > +#include "common_setup.h" > +#include "exynos4_setup.h" > + > +#define SET_MIU > + > +#ifdef CONFIG_CLK_800_330_165 > +#define DRAM_CLK_330 > +#endif > +#ifdef CONFIG_CLK_1000_200_200 > +#define DRAM_CLK_200 > +#endif > +#ifdef CONFIG_CLK_1000_330_165 > +#define DRAM_CLK_330 > +#endif > +#ifdef CONFIG_CLK_1000_400_200 > +#define DRAM_CLK_400 > +#endif > + > +struct mem_timings mem = { > + .direct_cmd_msr = { > + 0x00020000, 0x00030000, 0x00010002, 0x00000328 > + }, > +#ifdef CONFIG_ORIGEN > + .timingref = 0x000000BB, > + .timingrow = 0x4046654f, > + .timingdata = 0x46400506, > + .timingpower = 0x52000A3C, > +#else > + .timingref = 0x000000BC, > +#ifdef DRAM_CLK_330 > + .timingrow = 0x3545548d, > + .timingdata = 0x45430506, > + .timingpower = 0x4439033c, > +#endif > +#ifdef DRAM_CLK_400 > + .timingrow = 0x45430506, > + .timingdata = 0x56500506, > + .timingpower = 0x5444033d, > +#endif > +#endif > + .zqcontrol = 0xE3855703, > + .control0 = 0x71101008, > + .control1 = 0xe0000086, > + .control2 = 0x00000000, > + .concontrol = 0x0fff301a, > + .prechconfig = 0xff000000, > + .memcontrol = 0x00312640, > +#ifdef CONFIG_MIU_LINEAR > + /* > + * Memory Configuration Chip 0 > + * Address Mapping: linear > + * Number of Column address Bits: 10 bits > + * Number of Rows Address Bits: 14 > + * Number of Banks: 8 > + */ > + .memconfig0 = 0x40e01323, > + /* > + * Memory Configuration Chip 1 > + * Address Mapping: Linear > + * Number of Column address Bits: 10 bits > + * Number of Rows Address Bits: 14 > + * Number of Banks: 8 > + */ > + .memconfig1 = 0x60e01323, > +#else > + /* > + * Memory Configuration Chip 0 > + * Address Mapping: Interleaved > + * Number of Column address Bits: 10 bits > + * Number of Rows Address Bits: 14 > + * Number of Banks: 8 > + */ > + .memconfig0 = 0x20e01323, > + /* > + * Memory Configuration Chip 1 > + * Address Mapping: Interleaved > + * Number of Column address Bits: 10 bits > + * Number of Rows Address Bits: 14 > + * Number of Banks: 8 > + */ > + .memconfig1 = 0x40e01323, > +#endif please fix these magic codes. > + .dll_resync = 3, > + .dll_on = 1, > +}; > + > +static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc) > +{ > + if (ctrl_no) { > + writel((mem.control1 | (1 << mem.dll_resync)), > + &dmc->phycontrol1); > + writel((mem.control1 | (0 << mem.dll_resync)), > + &dmc->phycontrol1); > + } else { > + writel((mem.control0 | (0 << mem.dll_on)), > + &dmc->phycontrol0); > + writel((mem.control0 | (1 << mem.dll_on)), > + &dmc->phycontrol0); > + } > +} > + > +static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip) > +{ > + int i; > + unsigned long mask = 0; > + > + if (chip) > + mask = DIRECT_CMD_CHIP1_SHIFT; > + > + for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { > + writel(mem.direct_cmd_msr[i] | mask, > + &dmc->directcmd); > + } > +} > + > +void mem_ctrl_init(int reset) > +{ > + struct exynos4_dmc *dmc0, *dmc1; > + /* > + * Async bridge configuration at CPU_core: > + * 1: half_sync > + * 0: full_sync > + */ > + writel(1, ASYNC_CONFIG); > +#ifdef SET_MIU > +#ifdef CONFIG_ORIGEN > + /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ > + writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE + > + APB_SFR_INTERLEAVE_CONF_OFFSET); > + /* Update MIU Configuration */ > + writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE + > + APB_SFR_ARBRITATION_CONF_OFFSET); > +#else > + writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE + > + APB_SFR_INTERLEAVE_CONF_OFFSET); > + writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE + > + ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET); > + writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE + > + ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET); > + writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE + > + ABP_SFR_SLV_ADDRMAP_CONF_OFFSET); > +#ifdef CONFIG_MIU_LINEAR > + writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE + > + ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET); > + writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE + > + ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET); > + writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE + > + ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET); > + writel(SLAVE1_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE + > + ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET); > + writel(APB_SFR_SLV_ADDR_MAP_CONF_VAL, EXYNOS4_MIU_BASE + > + ABP_SFR_SLV_ADDRMAP_CONF_OFFSET); > +#endif > +#endif > +#endif > + /* DREX0 */ > + dmc0 = (struct exynos4_dmc *)EXYNOS4_DMC0_BASE; > + dmc1 = (struct exynos4_dmc *)EXYNOS4_DMC1_BASE; > + /* > + * DLL Parameter Setting: > + * Termination: Enable R/W > + * Phase Delay for DQS Cleaning: 180' Shift > + */ > + writel(mem.control1, &dmc0->phycontrol1); > + writel(mem.control1, &dmc1->phycontrol1); > + > + /* > + * ZQ Calibration > + * Termination: Disable > + * Auto Calibration Start: Enable > + */ > + writel(mem.zqcontrol, &dmc0->phyzqcontrol); > + writel(mem.zqcontrol, &dmc1->phyzqcontrol); > + sdelay(0x100000); > + > + /* > + * Update DLL Information: > + * Force DLL Resyncronization > + */ > + phy_control_reset(1, dmc0); > + phy_control_reset(0, dmc0); > + phy_control_reset(1, dmc1); > + phy_control_reset(0, dmc1); > + > + /* Set DLL Parameters */ > + writel(mem.control1, &dmc0->phycontrol1); > + writel(mem.control1, &dmc1->phycontrol1); > + > + /* DLL Start */ > + writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc0->phycontrol0); > + writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc1->phycontrol0); > + > + writel(mem.control2, &dmc0->phycontrol2); > + writel(mem.control2, &dmc1->phycontrol2); > + > + /* Set Clock Ratio of Bus clock to Memory Clock */ > + writel(mem.concontrol, &dmc0->concontrol); > + writel(mem.concontrol, &dmc1->concontrol); > + > + /* > + * Memor Burst length: 8 > + * Number of chips: 2 > + * Memory Bus width: 32 bit > + * Memory Type: DDR3 > + * Additional Latancy for PLL: 1 Cycle > + */ > + writel(mem.memcontrol, &dmc0->memcontrol); > + writel(mem.memcontrol, &dmc1->memcontrol); > + > + writel(mem.memconfig0, &dmc0->memconfig0); > + writel(mem.memconfig1, &dmc0->memconfig1); > + writel(mem.memconfig0, &dmc1->memconfig0); > + writel(mem.memconfig1, &dmc1->memconfig1); > + > + /* Config Precharge Policy */ > + writel(mem.prechconfig, &dmc0->prechconfig); > + writel(mem.prechconfig, &dmc1->prechconfig); > + /* > + * TimingAref, TimingRow, TimingData, TimingPower Setting: > + * Values as per Memory AC Parameters > + */ > + writel(mem.timingref, &dmc0->timingref); > + writel(mem.timingrow, &dmc0->timingrow); > + writel(mem.timingdata, &dmc0->timingdata); > + writel(mem.timingpower, &dmc0->timingpower); > + > + writel(mem.timingref, &dmc1->timingref); > + writel(mem.timingrow, &dmc1->timingrow); > + writel(mem.timingdata, &dmc1->timingdata); > + writel(mem.timingpower, &dmc1->timingpower); > + > + /* Chip0: NOP Command: Assert and Hold CKE to high level */ > + writel(DIRECT_CMD_NOP, &dmc0->directcmd); > + writel(DIRECT_CMD_NOP, &dmc1->directcmd); > + sdelay(0x100000); > + > + /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ > + dmc_config_mrs(dmc0, 0); > + dmc_config_mrs(dmc1, 0); > + sdelay(0x100000); > + > + /* Chip0: ZQINIT */ > + writel(DIRECT_CMD_ZQ, &dmc0->directcmd); > + writel(DIRECT_CMD_ZQ, &dmc1->directcmd); > + sdelay(0x100000); > + > + writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc0->directcmd); > + writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc1->directcmd); > + sdelay(0x100000); > + > + /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ > + dmc_config_mrs(dmc0, 1); > + dmc_config_mrs(dmc1, 1); > + sdelay(0x100000); > + > + /* Chip1: ZQINIT */ > + writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc0->directcmd); > + writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc1->directcmd); > + sdelay(0x100000); > + > + phy_control_reset(1, dmc0); > + phy_control_reset(1, dmc1); > + sdelay(0x100000); > + > + /* turn on DREX0, DREX1 */ > + writel((mem.concontrol | AREF_EN) , &dmc0->concontrol); > + writel((mem.concontrol | AREF_EN), &dmc1->concontrol); > +} > diff --git a/board/samsung/origen/origen_setup.h b/arch/arm/cpu/armv7/exynos/exynos4_setup.h > similarity index 89% > rename from board/samsung/origen/origen_setup.h > rename to arch/arm/cpu/armv7/exynos/exynos4_setup.h > index 930b948..bfb31b8 100644 > --- a/board/samsung/origen/origen_setup.h > +++ b/arch/arm/cpu/armv7/exynos/exynos4_setup.h > @@ -1,5 +1,5 @@ > /* > - * Machine Specific Values for ORIGEN board based on S5PV310 > + * Machine Specific Values for EXYNOS4012 based board > * > * Copyright (C) 2011 Samsung Electronics > * > @@ -102,10 +102,6 @@ > /* Bus Configuration Register Address */ > #define ASYNC_CONFIG 0x10010350 > > -/* MIU Config Register Offsets*/ > -#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400 > -#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00 > - > /* Offset for inform registers */ > #define INFORM0_OFFSET 0x800 > #define INFORM1_OFFSET 0x804 > @@ -629,4 +625,70 @@ > * DECPROTXSET: 0xFF : Set Decode region to non-secure > */ > #define DECPROTXSET 0xFF > + > +/* DMC */ > +#define DIRECT_CMD_NOP 0x07000000 > +#define DIRECT_CMD_ZQ 0x0a000000 > +#define DIRECT_CMD_CHIP1_SHIFT (1 << 20) > +#define MEM_TIMINGS_MSR_COUNT 4 > +#define CTRL_START (1 << 0) > +#define CTRL_DLL_ON (1 << 1) > +#define AREF_EN (1 << 5) > +#define DRV_TYPE (1 << 6) > + > +struct mem_timings { > + unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; > + unsigned timingref; > + unsigned timingrow; > + unsigned timingdata; > + unsigned timingpower; > + unsigned zqcontrol; > + unsigned control0; > + unsigned control1; > + unsigned control2; > + unsigned concontrol; > + unsigned prechconfig; > + unsigned memcontrol; > + unsigned memconfig0; > + unsigned memconfig1; > + unsigned dll_resync; > + unsigned dll_on; > +}; > + > +/* MIU */ > +/* MIU Config Register Offsets*/ > +#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400 > +#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00 > +#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800 > +#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808 > +#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810 > +#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818 > +#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820 > +#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828 > +#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830 > + > +#ifdef CONFIG_ORIGEN > +/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ > +#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507 > +#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001 > +#endif > + > +#define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000 > +#define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff > +#define INTERLEAVE_ADDR_MAP_EN 0x00000001 > + > +#ifdef CONFIG_MIU_1BIT_INTERLEAVED > +/* Interleave_bit0: 0xC*/ > +#define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c > +#endif > +#ifdef CONFIG_MIU_2BIT_INTERLEAVED > +/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */ > +#define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c > +#endif > +#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000 > +#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff > +#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000 > +#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff > +/* Enable SME0 and SME1*/ > +#define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006 I wonder that all of these values are common of architecture? > #endif > diff --git a/board/samsung/smdk5250/setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h > similarity index 93% > rename from board/samsung/smdk5250/setup.h > rename to arch/arm/cpu/armv7/exynos/exynos5_setup.h > index 34d8bc3..8f36c16 100644 > --- a/board/samsung/smdk5250/setup.h > +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h > @@ -28,18 +28,6 @@ > #include > #include > > -/* TZPC : Register Offsets */ > -#define TZPC0_BASE 0x10100000 > -#define TZPC1_BASE 0x10110000 > -#define TZPC2_BASE 0x10120000 > -#define TZPC3_BASE 0x10130000 > -#define TZPC4_BASE 0x10140000 > -#define TZPC5_BASE 0x10150000 > -#define TZPC6_BASE 0x10160000 > -#define TZPC7_BASE 0x10170000 > -#define TZPC8_BASE 0x10180000 > -#define TZPC9_BASE 0x10190000 > - > /* APLL_CON1 */ > #define APLL_CON1_VAL (0x00203800) > > @@ -105,17 +93,17 @@ > #define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25) > > /* MEMCONFIG0 register bit fields */ > -#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) > -#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) > -#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) > -#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) > -#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0) > - > -#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16) > -#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0) > +#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12) > +#define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8) > +#define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4) > +#define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4) > +#define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0) > + > +#define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16) > +#define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0) > #define DMC_MEMBASECONFIG_VAL(x) ( \ > - DMC_MEMBASECONFIGx_CHIP_BASE(x) | \ > - DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \ > + DMC_MEMBASECONFIGX_CHIP_BASE(x) | \ > + DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \ > ) > > #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) > @@ -458,18 +446,6 @@ > /* CLK_GATE_IP_DISP1 */ > #define CLK_GATE_DP1_ALLOW (1 << 4) > > -/* > - * TZPC Register Value : > - * R0SIZE: 0x0 : Size of secured ram > - */ > -#define R0SIZE 0x0 > - > -/* > - * TZPC Decode Protection Register Value : > - * DECPROTXSET: 0xFF : Set Decode region to non-secure > - */ > -#define DECPROTXSET 0xFF > - > #define DDR3PHY_CTRL_PHY_RESET (1 << 0) > #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) > > @@ -537,9 +513,11 @@ enum { > * which the DMC uses to decide how to split a memory > * chunk into smaller chunks to support concurrent > * accesses; may vary across boards. > + * @param reset Reset DDR PHY during initialization. > * @return 0 if ok, SETUP_ERR_... if there is a problem > */ > -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size); > +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, > + int reset); > > /* > * Configure ZQ I/O interface > @@ -586,9 +564,4 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc); > * @param ddr_mode Type of DDR memory > */ > void update_reset_dll(struct exynos5_dmc *, enum ddr_mode); > - > -void sdelay(unsigned long); > -void mem_ctrl_init(void); > -void system_clock_init(void); > -void tzpc_init(void); > #endif > diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c > new file mode 100644 > index 0000000..44d6522 > --- /dev/null > +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c > @@ -0,0 +1,72 @@ > +/* > + * Lowlevel setup for EXYNOS5 based board > + * > + * Copyright (C) 2013 Samsung Electronics > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "common_setup.h" > + > +/* These are the things we can do during low-level init */ > +enum { > + DO_WAKEUP = 1 << 0, > + DO_CLOCKS = 1 << 1, > + DO_MEM_RESET = 1 << 2, > + DO_UART = 1 << 3, > +}; > + > +int do_lowlevel_init(void) > +{ > + uint32_t reset_status; > + int actions = 0; > + > + arch_cpu_init(); > + > + reset_status = get_reset_status(); > + > + switch (reset_status) { > + case S5P_CHECK_SLEEP: > + actions = DO_CLOCKS | DO_WAKEUP; > + break; > + case S5P_CHECK_DIDLE: > + case S5P_CHECK_LPA: > + actions = DO_WAKEUP; > + break; > + default: > + /* This is a normal boot (not a wake from sleep) */ > + actions = DO_CLOCKS | DO_MEM_RESET; > + } > + > + if (actions & DO_CLOCKS) { > + system_clock_init(); > + mem_ctrl_init(actions & DO_MEM_RESET); > + tzpc_init(); > + } > + > + return actions & DO_WAKEUP; > +} > diff --git a/board/samsung/smdk5250/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c > similarity index 61% > rename from board/samsung/smdk5250/spl_boot.c > rename to arch/arm/cpu/armv7/exynos/spl_boot.c > index c0bcf46..1a1d011 100644 > --- a/board/samsung/smdk5250/spl_boot.c > +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c > @@ -22,18 +22,19 @@ > > #include > #include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "common_setup.h" > > -enum boot_mode { > - BOOT_MODE_MMC = 4, > - BOOT_MODE_SERIAL = 20, > - /* Boot based on Operating Mode pin settings */ > - BOOT_MODE_OM = 32, > - BOOT_MODE_USB, /* Boot using USB download */ > -}; > +DECLARE_GLOBAL_DATA_PTR; > > - typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); > - typedef u32 (*usb_copy_func_t)(void); > +#define OM_STAT (0x1f << 1) > > +#ifdef CONFIG_USB_BOOTING > /* > * Set/clear program flow prediction and return the previous state. > */ > @@ -47,6 +48,7 @@ static int config_branch_prediction(int set_cr_z) > > return cr & CR_Z; > } > +#endif > > /* > * Copy U-boot from mmc to RAM: > @@ -55,52 +57,89 @@ static int config_branch_prediction(int set_cr_z) > */ > void copy_uboot_to_ram(void) > { > - spi_copy_func_t spi_copy; > - usb_copy_func_t usb_copy; > - > + enum boot_mode bootmode = BOOT_MODE_OM; > + u32 (*copy_bl2)(u32, u32, u32) = NULL; > + u32 offset = 0, size = 0; > +#ifdef CONFIG_USB_BOOTING > + u32 (*usb_copy)(void) = NULL; unrelated changes. > int is_cr_z_set; > unsigned int sec_boot_check; > - enum boot_mode bootmode = BOOT_MODE_OM; > - u32 (*copy_bl2)(u32, u32, u32); > > /* Read iRAM location to check for secondary USB boot mode */ > sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE); > if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT) > bootmode = BOOT_MODE_USB; > - > +#endif > if (bootmode == BOOT_MODE_OM) > - bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT; > + bootmode = readl(samsung_get_base_power()) & OM_STAT; > > switch (bootmode) { > +#ifdef CONFIG_SPI_BOOTING > case BOOT_MODE_SERIAL: > - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; > - spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, > - CONFIG_SYS_TEXT_BASE); > + offset = SPI_FLASH_UBOOT_POS; > + size = CONFIG_BL2_SIZE; > + copy_bl2 = (void *)*(u32 *)EXYNOS_COPY_SPI_FNPTR_ADDR; ditto. > break; > +#endif > case BOOT_MODE_MMC: > - copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; > - copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, > - CONFIG_SYS_TEXT_BASE); > + offset = BL2_START_OFFSET; > + size = BL2_SIZE_BLOC_COUNT; > + copy_bl2 = (void *)*(u32 *)COPY_BL2_FNPTR_ADDR; ditto. > break; > +#ifdef CONFIG_USB_BOOTING > case BOOT_MODE_USB: > /* > * iROM needs program flow prediction to be disabled > * before copy from USB device to RAM > */ > is_cr_z_set = config_branch_prediction(0); > - usb_copy = *(usb_copy_func_t *) > - EXYNOS_COPY_USB_FNPTR_ADDR; > + usb_copy = (void *)*(u32 *)EXYNOS_COPY_USB_FNPTR_ADDR; ditto. > usb_copy(); > config_branch_prediction(is_cr_z_set); > break; > +#endif > default: > break; > } > + > + if (copy_bl2) > + copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE); ditto. > +} > + > +void memzero(void *s, size_t n) > +{ > + char *ptr = s; > + size_t i; > + > + for (i = 0; i < n; i++) > + *ptr++ = '\0'; > } > > +/** > + * Set up the U-Boot global_data pointer > + * > + * This sets the address of the global data, and sets up basic values. > + * > + * @param gdp Value to give to gd > + */ > +static void setup_global_data(gd_t *gdp) > +{ > + gd = gdp; > + memzero((void *)gd, sizeof(gd_t)); > + gd->flags |= GD_FLG_RELOC; > + gd->baudrate = CONFIG_BAUDRATE; > + gd->have_console = 1; > +} > void board_init_f(unsigned long bootflag) > { > + __attribute__((aligned(8))) gd_t local_gd; > __attribute__((noreturn)) void (*uboot)(void); > + > + setup_global_data(&local_gd); > + > + if (do_lowlevel_init()) > + power_exit_wakeup(); > + > copy_uboot_to_ram(); > > /* Jump to U-Boot image */ > @@ -118,4 +157,5 @@ void board_init_r(gd_t *id, ulong dest_addr) > ; > } > > -void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {} > +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) > +{} > diff --git a/board/samsung/smdk5250/tzpc_init.c b/arch/arm/cpu/armv7/exynos/tzpc_init.c > similarity index 81% > rename from board/samsung/smdk5250/tzpc_init.c > rename to arch/arm/cpu/armv7/exynos/tzpc_init.c > index c833541..5204fb1 100644 > --- a/board/samsung/smdk5250/tzpc_init.c > +++ b/arch/arm/cpu/armv7/exynos/tzpc_init.c > @@ -22,19 +22,28 @@ > * MA 02111-1307 USA > */ > > +#include > #include > -#include"setup.h" > +#include > > /* Setting TZPC[TrustZone Protection Controller] */ > void tzpc_init(void) > { > struct exynos_tzpc *tzpc; > - unsigned int addr; > + unsigned int addr, start = 0, end = 0; > > - for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) { > + if (cpu_is_exynos5()) { > + start = TZPC0_BASE; > + end = TZPC9_BASE; > + } else if (cpu_is_exynos4()) { > + start = TZPC1_BASE; > + end = TZPC6_BASE; > + } > + > + for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) { > tzpc = (struct exynos_tzpc *)addr; > > - if (addr == TZPC0_BASE) > + if (addr == start) > writel(R0SIZE, &tzpc->r0size); > > writel(DECPROTXSET, &tzpc->decprot0set); > diff --git a/arch/arm/include/asm/arch-exynos/spl.h b/arch/arm/include/asm/arch-exynos/spl.h > index 46b25a6..461d716 100644 > --- a/arch/arm/include/asm/arch-exynos/spl.h > +++ b/arch/arm/include/asm/arch-exynos/spl.h > @@ -32,6 +32,7 @@ enum boot_mode { > * pin values are the same across Exynos4 and Exynos5. > */ > BOOT_MODE_MMC = 4, > + BOOT_MODE_EMMC = 8, /* EMMC4.4 */ > BOOT_MODE_SERIAL = 20, > /* Boot based on Operating Mode pin settings */ > BOOT_MODE_OM = 32, > diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h b/arch/arm/include/asm/arch-exynos/tzpc.h > index c5eb4b1..050ad70 100644 > --- a/arch/arm/include/asm/arch-exynos/tzpc.h > +++ b/arch/arm/include/asm/arch-exynos/tzpc.h > @@ -47,6 +47,34 @@ struct exynos_tzpc { > unsigned int pcellid2; > unsigned int pcellid3; > }; > + > +/* TZPC : Register Offsets */ > +#define TZPC0_BASE 0x10100000 > +#define TZPC1_BASE 0x10110000 > +#define TZPC2_BASE 0x10120000 > +#define TZPC3_BASE 0x10130000 > +#define TZPC4_BASE 0x10140000 > +#define TZPC5_BASE 0x10150000 > +#define TZPC6_BASE 0x10160000 > +#define TZPC7_BASE 0x10170000 > +#define TZPC8_BASE 0x10180000 > +#define TZPC9_BASE 0x10190000 > + > +#define TZPC_BASE_OFFSET 0x10000 > + > +/* > + * TZPC Register Value : > + * R0SIZE: 0x0 : Size of secured ram > + */ > +#define R0SIZE 0x0 > + > +/* > + * TZPC Decode Protection Register Value : > + * DECPROTXSET: 0xFF : Set Decode region to non-secure > + */ > +#define DECPROTXSET 0xFF > +void tzpc_init(void); > + > #endif > > #endif > diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile > index 3a885a5..877fb95 100644 > --- a/board/samsung/origen/Makefile > +++ b/board/samsung/origen/Makefile > @@ -24,17 +24,10 @@ include $(TOPDIR)/config.mk > > LIB = $(obj)lib$(BOARD).o > > -SOBJS := mem_setup.o > -SOBJS += lowlevel_init.o > - > ifndef CONFIG_SPL_BUILD > COBJS += origen.o > endif > > -ifdef CONFIG_SPL_BUILD > -COBJS += mmc_boot.o > -endif > - > SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) > > diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S > deleted file mode 100644 > index 9daa0da..0000000 > --- a/board/samsung/origen/lowlevel_init.S > +++ /dev/null > @@ -1,397 +0,0 @@ > -/* > - * Lowlevel setup for ORIGEN board based on EXYNOS4210 > - * > - * Copyright (C) 2011 Samsung Electronics > - * > - * See file CREDITS for list of people who contributed to this > - * project. > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - * > - * This program is distributed in the hope that it will be useful, > - * but WITHOUT ANY WARRANTY; without even the implied warranty of > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > - * GNU General Public License for more details. > - * > - * You should have received a copy of the GNU General Public License > - * along with this program; if not, write to the Free Software > - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > - * MA 02111-1307 USA > - */ > - > -#include > -#include > -#include > -#include "origen_setup.h" > -/* > - * Register usages: > - * > - * r5 has zero always > - * r7 has GPIO part1 base 0x11400000 > - * r6 has GPIO part2 base 0x11000000 > - */ > - > -_TEXT_BASE: > - .word CONFIG_SYS_TEXT_BASE > - > - .globl lowlevel_init > -lowlevel_init: > - push {lr} > - > - /* r5 has always zero */ > - mov r5, #0 > - ldr r7, =EXYNOS4_GPIO_PART1_BASE > - ldr r6, =EXYNOS4_GPIO_PART2_BASE > - > - /* check reset status */ > - ldr r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET) > - ldr r1, [r0] > - > - /* AFTR wakeup reset */ > - ldr r2, =S5P_CHECK_DIDLE > - cmp r1, r2 > - beq exit_wakeup > - > - /* LPA wakeup reset */ > - ldr r2, =S5P_CHECK_LPA > - cmp r1, r2 > - beq exit_wakeup > - > - /* Sleep wakeup reset */ > - ldr r2, =S5P_CHECK_SLEEP > - cmp r1, r2 > - beq wakeup_reset > - > - /* > - * If U-boot is already running in ram, no need to relocate U-Boot. > - * Memory controller must be configured before relocating U-Boot > - * in ram. > - */ > - ldr r0, =0x0ffffff /* r0 <- Mask Bits*/ > - bic r1, pc, r0 /* pc <- current addr of code */ > - /* r1 <- unmasked bits of pc */ > - ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */ > - bic r2, r2, r0 /* r2 <- unmasked bits of r2*/ > - cmp r1, r2 /* compare r1, r2 */ > - beq 1f /* r0 == r1 then skip sdram init */ > - > - /* init system clock */ > - bl system_clock_init > - > - /* Memory initialize */ > - bl mem_ctrl_asm_init > - > -1: > - /* for UART */ > - bl uart_asm_init > - bl tzpc_init > - pop {pc} > - > -wakeup_reset: > - bl system_clock_init > - bl mem_ctrl_asm_init > - bl tzpc_init > - > -exit_wakeup: > - /* Load return address and jump to kernel */ > - ldr r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET) > - > - /* r1 = physical address of exynos4210_cpu_resume function */ > - ldr r1, [r0] > - > - /* Jump to kernel*/ > - mov pc, r1 > - nop > - nop > - > -/* > - * system_clock_init: Initialize core clock and bus clock. > - * void system_clock_init(void) > - */ > -system_clock_init: > - push {lr} > - ldr r0, =EXYNOS4_CLOCK_BASE > - > - /* APLL(1), MPLL(1), CORE(0), HPM(0) */ > - ldr r1, =CLK_SRC_CPU_VAL > - ldr r2, =CLK_SRC_CPU_OFFSET > - str r1, [r0, r2] > - > - /* wait ?us */ > - mov r1, #0x10000 > -2: subs r1, r1, #1 > - bne 2b > - > - ldr r1, =CLK_SRC_TOP0_VAL > - ldr r2, =CLK_SRC_TOP0_OFFSET > - str r1, [r0, r2] > - > - ldr r1, =CLK_SRC_TOP1_VAL > - ldr r2, =CLK_SRC_TOP1_OFFSET > - str r1, [r0, r2] > - > - /* DMC */ > - ldr r1, =CLK_SRC_DMC_VAL > - ldr r2, =CLK_SRC_DMC_OFFSET > - str r1, [r0, r2] > - > - /*CLK_SRC_LEFTBUS */ > - ldr r1, =CLK_SRC_LEFTBUS_VAL > - ldr r2, =CLK_SRC_LEFTBUS_OFFSET > - str r1, [r0, r2] > - > - /*CLK_SRC_RIGHTBUS */ > - ldr r1, =CLK_SRC_RIGHTBUS_VAL > - ldr r2, =CLK_SRC_RIGHTBUS_OFFSET > - str r1, [r0, r2] > - > - /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ > - ldr r1, =CLK_SRC_FSYS_VAL > - ldr r2, =CLK_SRC_FSYS_OFFSET > - str r1, [r0, r2] > - > - /* UART[0:4] */ > - ldr r1, =CLK_SRC_PERIL0_VAL > - ldr r2, =CLK_SRC_PERIL0_OFFSET > - str r1, [r0, r2] > - > - /* CAM , FIMC 0-3 */ > - ldr r1, =CLK_SRC_CAM_VAL > - ldr r2, =CLK_SRC_CAM_OFFSET > - str r1, [r0, r2] > - > - /* MFC */ > - ldr r1, =CLK_SRC_MFC_VAL > - ldr r2, =CLK_SRC_MFC_OFFSET > - str r1, [r0, r2] > - > - /* G3D */ > - ldr r1, =CLK_SRC_G3D_VAL > - ldr r2, =CLK_SRC_G3D_OFFSET > - str r1, [r0, r2] > - > - /* LCD0 */ > - ldr r1, =CLK_SRC_LCD0_VAL > - ldr r2, =CLK_SRC_LCD0_OFFSET > - str r1, [r0, r2] > - > - /* wait ?us */ > - mov r1, #0x10000 > -3: subs r1, r1, #1 > - bne 3b > - > - /* CLK_DIV_CPU0 */ > - ldr r1, =CLK_DIV_CPU0_VAL > - ldr r2, =CLK_DIV_CPU0_OFFSET > - str r1, [r0, r2] > - > - /* CLK_DIV_CPU1 */ > - ldr r1, =CLK_DIV_CPU1_VAL > - ldr r2, =CLK_DIV_CPU1_OFFSET > - str r1, [r0, r2] > - > - /* CLK_DIV_DMC0 */ > - ldr r1, =CLK_DIV_DMC0_VAL > - ldr r2, =CLK_DIV_DMC0_OFFSET > - str r1, [r0, r2] > - > - /*CLK_DIV_DMC1 */ > - ldr r1, =CLK_DIV_DMC1_VAL > - ldr r2, =CLK_DIV_DMC1_OFFSET > - str r1, [r0, r2] > - > - /* CLK_DIV_LEFTBUS */ > - ldr r1, =CLK_DIV_LEFTBUS_VAL > - ldr r2, =CLK_DIV_LEFTBUS_OFFSET > - str r1, [r0, r2] > - > - /* CLK_DIV_RIGHTBUS */ > - ldr r1, =CLK_DIV_RIGHTBUS_VAL > - ldr r2, =CLK_DIV_RIGHTBUS_OFFSET > - str r1, [r0, r2] > - > - /* CLK_DIV_TOP */ > - ldr r1, =CLK_DIV_TOP_VAL > - ldr r2, =CLK_DIV_TOP_OFFSET > - str r1, [r0, r2] > - > - /* MMC[0:1] */ > - ldr r1, =CLK_DIV_FSYS1_VAL /* 800(MPLL) / (15 + 1) */ > - ldr r2, =CLK_DIV_FSYS1_OFFSET > - str r1, [r0, r2] > - > - /* MMC[2:3] */ > - ldr r1, =CLK_DIV_FSYS2_VAL /* 800(MPLL) / (15 + 1) */ > - ldr r2, =CLK_DIV_FSYS2_OFFSET > - str r1, [r0, r2] > - > - /* MMC4 */ > - ldr r1, =CLK_DIV_FSYS3_VAL /* 800(MPLL) / (15 + 1) */ > - ldr r2, =CLK_DIV_FSYS3_OFFSET > - str r1, [r0, r2] > - > - /* CLK_DIV_PERIL0: UART Clock Divisors */ > - ldr r1, =CLK_DIV_PERIL0_VAL > - ldr r2, =CLK_DIV_PERIL0_OFFSET > - str r1, [r0, r2] > - > - /* CAM, FIMC 0-3: CAM Clock Divisors */ > - ldr r1, =CLK_DIV_CAM_VAL > - ldr r2, =CLK_DIV_CAM_OFFSET > - str r1, [r0, r2] > - > - /* CLK_DIV_MFC: MFC Clock Divisors */ > - ldr r1, =CLK_DIV_MFC_VAL > - ldr r2, =CLK_DIV_MFC_OFFSET > - str r1, [r0, r2] > - > - /* CLK_DIV_G3D: G3D Clock Divisors */ > - ldr r1, =CLK_DIV_G3D_VAL > - ldr r2, =CLK_DIV_G3D_OFFSET > - str r1, [r0, r2] > - > - /* CLK_DIV_LCD0: LCD0 Clock Divisors */ > - ldr r1, =CLK_DIV_LCD0_VAL > - ldr r2, =CLK_DIV_LCD0_OFFSET > - str r1, [r0, r2] > - > - /* Set PLL locktime */ > - ldr r1, =PLL_LOCKTIME > - ldr r2, =APLL_LOCK_OFFSET > - str r1, [r0, r2] > - > - ldr r1, =PLL_LOCKTIME > - ldr r2, =MPLL_LOCK_OFFSET > - str r1, [r0, r2] > - > - ldr r1, =PLL_LOCKTIME > - ldr r2, =EPLL_LOCK_OFFSET > - str r1, [r0, r2] > - > - ldr r1, =PLL_LOCKTIME > - ldr r2, =VPLL_LOCK_OFFSET > - str r1, [r0, r2] > - > - /* APLL_CON1 */ > - ldr r1, =APLL_CON1_VAL > - ldr r2, =APLL_CON1_OFFSET > - str r1, [r0, r2] > - > - /* APLL_CON0 */ > - ldr r1, =APLL_CON0_VAL > - ldr r2, =APLL_CON0_OFFSET > - str r1, [r0, r2] > - > - /* MPLL_CON1 */ > - ldr r1, =MPLL_CON1_VAL > - ldr r2, =MPLL_CON1_OFFSET > - str r1, [r0, r2] > - > - /* MPLL_CON0 */ > - ldr r1, =MPLL_CON0_VAL > - ldr r2, =MPLL_CON0_OFFSET > - str r1, [r0, r2] > - > - /* EPLL */ > - ldr r1, =EPLL_CON1_VAL > - ldr r2, =EPLL_CON1_OFFSET > - str r1, [r0, r2] > - > - /* EPLL_CON0 */ > - ldr r1, =EPLL_CON0_VAL > - ldr r2, =EPLL_CON0_OFFSET > - str r1, [r0, r2] > - > - /* VPLL_CON1 */ > - ldr r1, =VPLL_CON1_VAL > - ldr r2, =VPLL_CON1_OFFSET > - str r1, [r0, r2] > - > - /* VPLL_CON0 */ > - ldr r1, =VPLL_CON0_VAL > - ldr r2, =VPLL_CON0_OFFSET > - str r1, [r0, r2] > - > - /* wait ?us */ > - mov r1, #0x30000 > -4: subs r1, r1, #1 > - bne 4b > - > - pop {pc} > -/* > - * uart_asm_init: Initialize UART in asm mode, 115200bps fixed. > - * void uart_asm_init(void) > - */ > - .globl uart_asm_init > -uart_asm_init: > - > - /* setup UART0-UART3 GPIOs (part1) */ > - mov r0, r7 > - ldr r1, =EXYNOS4_GPIO_A0_CON_VAL > - str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET] > - ldr r1, =EXYNOS4_GPIO_A1_CON_VAL > - str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET] > - > - ldr r0, =EXYNOS4_UART_BASE > - add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET > - > - ldr r1, =ULCON_VAL > - str r1, [r0, #ULCON_OFFSET] > - ldr r1, =UCON_VAL > - str r1, [r0, #UCON_OFFSET] > - ldr r1, =UFCON_VAL > - str r1, [r0, #UFCON_OFFSET] > - ldr r1, =UBRDIV_VAL > - str r1, [r0, #UBRDIV_OFFSET] > - ldr r1, =UFRACVAL_VAL > - str r1, [r0, #UFRACVAL_OFFSET] > - mov pc, lr > - nop > - nop > - nop > - > -/* Setting TZPC[TrustZone Protection Controller] */ > -tzpc_init: > - ldr r0, =TZPC0_BASE > - mov r1, #R0SIZE > - str r1, [r0] > - mov r1, #DECPROTXSET > - str r1, [r0, #TZPC_DECPROT0SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT1SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT2SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT3SET_OFFSET] > - > - ldr r0, =TZPC1_BASE > - str r1, [r0, #TZPC_DECPROT0SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT1SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT2SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT3SET_OFFSET] > - > - ldr r0, =TZPC2_BASE > - str r1, [r0, #TZPC_DECPROT0SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT1SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT2SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT3SET_OFFSET] > - > - ldr r0, =TZPC3_BASE > - str r1, [r0, #TZPC_DECPROT0SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT1SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT2SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT3SET_OFFSET] > - > - ldr r0, =TZPC4_BASE > - str r1, [r0, #TZPC_DECPROT0SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT1SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT2SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT3SET_OFFSET] > - > - ldr r0, =TZPC5_BASE > - str r1, [r0, #TZPC_DECPROT0SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT1SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT2SET_OFFSET] > - str r1, [r0, #TZPC_DECPROT3SET_OFFSET] > - > - mov pc, lr > diff --git a/board/samsung/origen/mem_setup.S b/board/samsung/origen/mem_setup.S > deleted file mode 100644 > index b49b193..0000000 > --- a/board/samsung/origen/mem_setup.S > +++ /dev/null > @@ -1,421 +0,0 @@ > -/* > - * Memory setup for ORIGEN board based on EXYNOS4210 > - * > - * Copyright (C) 2011 Samsung Electronics > - * > - * See file CREDITS for list of people who contributed to this > - * project. > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - * > - * This program is distributed in the hope that it will be useful, > - * but WITHOUT ANY WARRANTY; without even the implied warranty of > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > - * GNU General Public License for more details. > - * > - * You should have received a copy of the GNU General Public License > - * along with this program; if not, write to the Free Software > - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > - * MA 02111-1307 USA > - */ > - > -#include > -#include "origen_setup.h" > -#define SET_MIU > - > - .globl mem_ctrl_asm_init > -mem_ctrl_asm_init: > - /* > - * Async bridge configuration at CPU_core: > - * 1: half_sync > - * 0: full_sync > - */ > - ldr r0, =ASYNC_CONFIG > - mov r1, #1 > - str r1, [r0] > - > -#ifdef SET_MIU > - ldr r0, =EXYNOS4_MIU_BASE > - /* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */ > - ldr r1, =0x20001507 > - str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET] > - > - /* Update MIU Configuration */ > - ldr r1, =0x00000001 > - str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET] > -#endif > - /* DREX0 */ > - ldr r0, =EXYNOS4_DMC0_BASE > - > - /* > - * DLL Parameter Setting: > - * Termination: Enable R/W > - * Phase Delay for DQS Cleaning: 180' Shift > - */ > - ldr r1, =0xe0000086 > - str r1, [r0, #DMC_PHYCONTROL1] > - > - /* > - * ZQ Calibration > - * Termination: Disable > - * Auto Calibration Start: Enable > - */ > - ldr r1, =0xE3855703 > - str r1, [r0, #DMC_PHYZQCONTROL] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -1: subs r2, r2, #1 > - bne 1b > - > - /* > - * Update DLL Information: > - * Force DLL Resyncronization > - */ > - ldr r1, =0xe000008e > - str r1, [r0, #DMC_PHYCONTROL1] > - > - /* Reset Force DLL Resyncronization */ > - ldr r1, =0xe0000086 > - str r1, [r0, #DMC_PHYCONTROL1] > - > - /* Enable Differential DQS, DLL Off*/ > - ldr r1, =0x71101008 > - str r1, [r0, #DMC_PHYCONTROL0] > - > - /* Activate PHY DLL: DLL On */ > - ldr r1, =0x7110100A > - str r1, [r0, #DMC_PHYCONTROL0] > - > - /* Set DLL Parameters */ > - ldr r1, =0xe0000086 > - str r1, [r0, #DMC_PHYCONTROL1] > - > - /* DLL Start */ > - ldr r1, =0x7110100B > - str r1, [r0, #DMC_PHYCONTROL0] > - > - ldr r1, =0x00000000 > - str r1, [r0, #DMC_PHYCONTROL2] > - > - /* Set Clock Ratio of Bus clock to Memory Clock */ > - ldr r1, =0x0FFF301a > - str r1, [r0, #DMC_CONCONTROL] > - > - /* > - * Memor Burst length: 8 > - * Number of chips: 2 > - * Memory Bus width: 32 bit > - * Memory Type: DDR3 > - * Additional Latancy for PLL: 1 Cycle > - */ > - ldr r1, =0x00312640 > - str r1, [r0, #DMC_MEMCONTROL] > - > - /* > - * Memory Configuration Chip 0 > - * Address Mapping: Interleaved > - * Number of Column address Bits: 10 bits > - * Number of Rows Address Bits: 14 > - * Number of Banks: 8 > - */ > - ldr r1, =0x20e01323 > - str r1, [r0, #DMC_MEMCONFIG0] > - > - /* > - * Memory Configuration Chip 1 > - * Address Mapping: Interleaved > - * Number of Column address Bits: 10 bits > - * Number of Rows Address Bits: 14 > - * Number of Banks: 8 > - */ > - ldr r1, =0x40e01323 > - str r1, [r0, #DMC_MEMCONFIG1] > - > - /* Config Precharge Policy */ > - ldr r1, =0xff000000 > - str r1, [r0, #DMC_PRECHCONFIG] > - > - /* > - * TimingAref, TimingRow, TimingData, TimingPower Setting: > - * Values as per Memory AC Parameters > - */ > - ldr r1, =0x000000BB > - str r1, [r0, #DMC_TIMINGAREF] > - ldr r1, =0x4046654f > - str r1, [r0, #DMC_TIMINGROW] > - ldr r1, =0x46400506 > - str r1, [r0, #DMC_TIMINGDATA] > - ldr r1, =0x52000A3C > - str r1, [r0, #DMC_TIMINGPOWER] > - > - /* Chip0: NOP Command: Assert and Hold CKE to high level */ > - ldr r1, =0x07000000 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -2: subs r2, r2, #1 > - bne 2b > - > - /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ > - ldr r1, =0x00020000 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00030000 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00010002 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00000328 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -3: subs r2, r2, #1 > - bne 3b > - > - /* Chip0: ZQINIT */ > - ldr r1, =0x0a000000 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -4: subs r2, r2, #1 > - bne 4b > - > - /* Chip1: NOP Command: Assert and Hold CKE to high level */ > - ldr r1, =0x07100000 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -5: subs r2, r2, #1 > - bne 5b > - > - /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ > - ldr r1, =0x00120000 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00130000 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00110002 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00100328 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -6: subs r2, r2, #1 > - bne 6b > - > - /* Chip1: ZQINIT */ > - ldr r1, =0x0a100000 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -7: subs r2, r2, #1 > - bne 7b > - > - ldr r1, =0xe000008e > - str r1, [r0, #DMC_PHYCONTROL1] > - ldr r1, =0xe0000086 > - str r1, [r0, #DMC_PHYCONTROL1] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -8: subs r2, r2, #1 > - bne 8b > - > - /* DREX1 */ > - ldr r0, =EXYNOS4_DMC1_BASE @0x10410000 > - > - /* > - * DLL Parameter Setting: > - * Termination: Enable R/W > - * Phase Delay for DQS Cleaning: 180' Shift > - */ > - ldr r1, =0xe0000086 > - str r1, [r0, #DMC_PHYCONTROL1] > - > - /* > - * ZQ Calibration: > - * Termination: Disable > - * Auto Calibration Start: Enable > - */ > - ldr r1, =0xE3855703 > - str r1, [r0, #DMC_PHYZQCONTROL] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -1: subs r2, r2, #1 > - bne 1b > - > - /* > - * Update DLL Information: > - * Force DLL Resyncronization > - */ > - ldr r1, =0xe000008e > - str r1, [r0, #DMC_PHYCONTROL1] > - > - /* Reset Force DLL Resyncronization */ > - ldr r1, =0xe0000086 > - str r1, [r0, #DMC_PHYCONTROL1] > - > - /* Enable Differential DQS, DLL Off*/ > - ldr r1, =0x71101008 > - str r1, [r0, #DMC_PHYCONTROL0] > - > - /* Activate PHY DLL: DLL On */ > - ldr r1, =0x7110100A > - str r1, [r0, #DMC_PHYCONTROL0] > - > - /* Set DLL Parameters */ > - ldr r1, =0xe0000086 > - str r1, [r0, #DMC_PHYCONTROL1] > - > - /* DLL Start */ > - ldr r1, =0x7110100B > - str r1, [r0, #DMC_PHYCONTROL0] > - > - ldr r1, =0x00000000 > - str r1, [r0, #DMC_PHYCONTROL2] > - > - /* Set Clock Ratio of Bus clock to Memory Clock */ > - ldr r1, =0x0FFF301a > - str r1, [r0, #DMC_CONCONTROL] > - > - /* > - * Memor Burst length: 8 > - * Number of chips: 2 > - * Memory Bus width: 32 bit > - * Memory Type: DDR3 > - * Additional Latancy for PLL: 1 Cycle > - */ > - ldr r1, =0x00312640 > - str r1, [r0, #DMC_MEMCONTROL] > - > - /* > - * Memory Configuration Chip 0 > - * Address Mapping: Interleaved > - * Number of Column address Bits: 10 bits > - * Number of Rows Address Bits: 14 > - * Number of Banks: 8 > - */ > - ldr r1, =0x20e01323 > - str r1, [r0, #DMC_MEMCONFIG0] > - > - /* > - * Memory Configuration Chip 1 > - * Address Mapping: Interleaved > - * Number of Column address Bits: 10 bits > - * Number of Rows Address Bits: 14 > - * Number of Banks: 8 > - */ > - ldr r1, =0x40e01323 > - str r1, [r0, #DMC_MEMCONFIG1] > - > - /* Config Precharge Policy */ > - ldr r1, =0xff000000 > - str r1, [r0, #DMC_PRECHCONFIG] > - > - /* > - * TimingAref, TimingRow, TimingData, TimingPower Setting: > - * Values as per Memory AC Parameters > - */ > - ldr r1, =0x000000BB > - str r1, [r0, #DMC_TIMINGAREF] > - ldr r1, =0x4046654f > - str r1, [r0, #DMC_TIMINGROW] > - ldr r1, =0x46400506 > - str r1, [r0, #DMC_TIMINGDATA] > - ldr r1, =0x52000A3C > - str r1, [r0, #DMC_TIMINGPOWER] > - > - /* Chip0: NOP Command: Assert and Hold CKE to high level */ > - ldr r1, =0x07000000 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -2: subs r2, r2, #1 > - bne 2b > - > - /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ > - ldr r1, =0x00020000 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00030000 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00010002 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00000328 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -3: subs r2, r2, #1 > - bne 3b > - > - /* Chip 0: ZQINIT */ > - ldr r1, =0x0a000000 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -4: subs r2, r2, #1 > - bne 4b > - > - /* Chip1: NOP Command: Assert and Hold CKE to high level */ > - ldr r1, =0x07100000 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -5: subs r2, r2, #1 > - bne 5b > - > - /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ > - ldr r1, =0x00120000 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00130000 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00110002 > - str r1, [r0, #DMC_DIRECTCMD] > - ldr r1, =0x00100328 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -6: subs r2, r2, #1 > - bne 6b > - > - /* Chip1: ZQINIT */ > - ldr r1, =0x0a100000 > - str r1, [r0, #DMC_DIRECTCMD] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -7: subs r2, r2, #1 > - bne 7b > - > - ldr r1, =0xe000008e > - str r1, [r0, #DMC_PHYCONTROL1] > - ldr r1, =0xe0000086 > - str r1, [r0, #DMC_PHYCONTROL1] > - > - /* Wait ?us*/ > - mov r2, #0x100000 > -8: subs r2, r2, #1 > - bne 8b > - > - /* turn on DREX0, DREX1 */ > - ldr r0, =EXYNOS4_DMC0_BASE > - ldr r1, =0x0FFF303a > - str r1, [r0, #DMC_CONCONTROL] > - > - ldr r0, =EXYNOS4_DMC1_BASE > - ldr r1, =0x0FFF303a > - str r1, [r0, #DMC_CONCONTROL] > - > - mov pc, lr > diff --git a/board/samsung/origen/mmc_boot.c b/board/samsung/origen/mmc_boot.c > deleted file mode 100644 > index 072f161..0000000 > --- a/board/samsung/origen/mmc_boot.c > +++ /dev/null > @@ -1,58 +0,0 @@ > -/* > - * Copyright (C) 2011 Samsung Electronics > - * > - * See file CREDITS for list of people who contributed to this > - * project. > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - * > - * This program is distributed in the hope that it will be useful, > - * but WITHOUT ANY WARRANTY; without even the implied warranty of > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > - * GNU General Public License for more details. > - * > - * You should have received a copy of the GNU General Public License > - * along with this program; if not, write to the Free Software > - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > - * MA 02111-1307 USA > - */ > - > -#include > -#include > - > -/* > -* Copy U-boot from mmc to RAM: > -* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains > -* Pointer to API (Data transfer from mmc to ram) > -*/ > -void copy_uboot_to_ram(void) > -{ > - u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; > - > - copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); > -} > - > -void board_init_f(unsigned long bootflag) > -{ > - __attribute__((noreturn)) void (*uboot)(void); > - copy_uboot_to_ram(); > - > - /* Jump to U-Boot image */ > - uboot = (void *)CONFIG_SYS_TEXT_BASE; > - (*uboot)(); > - /* Never returns Here */ > -} > - > -/* Place Holders */ > -void board_init_r(gd_t *id, ulong dest_addr) > -{ > - /* Function attribute is no-return */ > - /* This Function never executes */ > - while (1) > - ; > -} > - > -void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {} > diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile > index 47c6a5a..97ff9d8 100644 > --- a/board/samsung/smdk5250/Makefile > +++ b/board/samsung/smdk5250/Makefile > @@ -24,21 +24,12 @@ include $(TOPDIR)/config.mk > > LIB = $(obj)lib$(BOARD).o > > -SOBJS := lowlevel_init.o > - > -COBJS := clock_init.o > -COBJS += dmc_common.o dmc_init_ddr3.o > -COBJS += tzpc_init.o > COBJS += smdk5250_spl.o > > ifndef CONFIG_SPL_BUILD > COBJS += smdk5250.o > endif > > -ifdef CONFIG_SPL_BUILD > -COBJS += spl_boot.o > -endif > - > SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) > > diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S > index bc6cb6f..edc565e 100644 > --- a/board/samsung/smdk5250/lowlevel_init.S > +++ b/board/samsung/smdk5250/lowlevel_init.S > @@ -75,12 +75,14 @@ lowlevel_init: > bl mem_ctrl_init > > 1: > + bl arch_cpu_init > bl tzpc_init > ldmia r13!, {ip,pc} > > wakeup_reset: > bl system_clock_init > bl mem_ctrl_init > + bl arch_cpu_init > bl tzpc_init > > exit_wakeup: > diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile > index 56e0c16..c4cd0a3 100644 > --- a/board/samsung/smdkv310/Makefile > +++ b/board/samsung/smdkv310/Makefile > @@ -24,18 +24,12 @@ include $(TOPDIR)/config.mk > > LIB = $(obj)lib$(BOARD).o > > -SOBJS := mem_setup.o > -SOBJS += lowlevel_init.o > ifndef CONFIG_SPL_BUILD > COBJS += smdkv310.o > endif > > -ifdef CONFIG_SPL_BUILD > -COBJS += mmc_boot.o > -endif > - > -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) > +SRCS := $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS)) > > ALL := $(obj).depend $(LIB) > > diff --git a/board/samsung/smdkv310/lowlevel_init.S b/board/samsung/smdkv310/lowlevel_init.S > deleted file mode 100644 > index 7a1ea98..0000000 > --- a/board/samsung/smdkv310/lowlevel_init.S > +++ /dev/null > @@ -1,470 +0,0 @@ > -/* > - * Lowlevel setup for SMDKV310 board based on EXYNOS4210 > - * > - * Copyright (C) 2011 Samsung Electronics > - * > - * See file CREDITS for list of people who contributed to this > - * project. > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - * > - * This program is distributed in the hope that it will be useful, > - * but WITHOUT ANY WARRANTY; without even the implied warranty of > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > - * GNU General Public License for more details. > - * > - * You should have received a copy of the GNU General Public License > - * along with this program; if not, write to the Free Software > - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > - * MA 02111-1307 USA > - */ > - > -#include > -#include > -#include > - > -/* > - * Register usages: > - * > - * r5 has zero always > - * r7 has GPIO part1 base 0x11400000 > - * r6 has GPIO part2 base 0x11000000 > - */ > - > -#define MEM_DLLl_ON > - > -_TEXT_BASE: > - .word CONFIG_SYS_TEXT_BASE > - > - .globl lowlevel_init > -lowlevel_init: > - push {lr} > - > - /* r5 has always zero */ > - mov r5, #0 > - ldr r7, =EXYNOS4_GPIO_PART1_BASE > - ldr r6, =EXYNOS4_GPIO_PART2_BASE > - > - /* check reset status */ > - ldr r0, =(EXYNOS4_POWER_BASE + 0x81C) @ INFORM7 > - ldr r1, [r0] > - > - /* AFTR wakeup reset */ > - ldr r2, =S5P_CHECK_DIDLE > - cmp r1, r2 > - beq exit_wakeup > - > - /* Sleep wakeup reset */ > - ldr r2, =S5P_CHECK_SLEEP > - cmp r1, r2 > - beq wakeup_reset > - > - /* > - * If U-boot is already running in ram, no need to relocate U-Boot. > - * Memory controller must be configured before relocating U-Boot > - * in ram. > - */ > - ldr r0, =0x00ffffff /* r0 <- Mask Bits*/ > - bic r1, pc, r0 /* pc <- current addr of code */ > - /* r1 <- unmasked bits of pc */ > - > - ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */ > - bic r2, r2, r0 /* r2 <- unmasked bits of r2*/ > - cmp r1, r2 /* compare r1, r2 */ > - beq 1f /* r0 == r1 then skip sdram init */ > - > - /* init system clock */ > - bl system_clock_init > - > - /* Memory initialize */ > - bl mem_ctrl_asm_init > - > -1: > - /* for UART */ > - bl uart_asm_init > - bl tzpc_init > - pop {pc} > - > -wakeup_reset: > - bl system_clock_init > - bl mem_ctrl_asm_init > - bl tzpc_init > - > -exit_wakeup: > - /* Load return address and jump to kernel */ > - ldr r0, =(EXYNOS4_POWER_BASE + 0x800) @ INFORM0 > - > - /* r1 = physical address of exynos4210_cpu_resume function */ > - ldr r1, [r0] > - > - /* Jump to kernel*/ > - mov pc, r1 > - nop > - nop > - > -/* > - * system_clock_init: Initialize core clock and bus clock. > - * void system_clock_init(void) > - */ > -system_clock_init: > - push {lr} > - ldr r0, =EXYNOS4_CLOCK_BASE > - > - /* APLL(1), MPLL(1), CORE(0), HPM(0) */ > - ldr r1, =0x0101 > - ldr r2, =0x14200 @CLK_SRC_CPU > - str r1, [r0, r2] > - > - /* wait ?us */ > - mov r1, #0x10000 > -2: subs r1, r1, #1 > - bne 2b > - > - ldr r1, =0x00 > - ldr r2, =0x0C210 @CLK_SRC_TOP0 > - str r1, [r0, r2] > - > - ldr r1, =0x00 > - ldr r2, =0x0C214 @CLK_SRC_TOP1_OFFSET > - str r1, [r0, r2] > - > - /* DMC */ > - ldr r1, =0x00 > - ldr r2, =0x10200 @CLK_SRC_DMC_OFFSET > - str r1, [r0, r2] > - > - /*CLK_SRC_LEFTBUS */ > - ldr r1, =0x00 > - ldr r2, =0x04200 @CLK_SRC_LEFTBUS_OFFSET > - str r1, [r0, r2] > - > - /*CLK_SRC_RIGHTBUS */ > - ldr r1, =0x00 > - ldr r2, =0x08200 @CLK_SRC_RIGHTBUS_OFFSET > - str r1, [r0, r2] > - > - /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ > - ldr r1, =0x066666 > - ldr r2, =0x0C240 @ CLK_SRC_FSYS > - str r1, [r0, r2] > - > - /* UART[0:4], PWM: SCLKMPLL(6) */ > - ldr r1, =0x06666666 > - ldr r2, =0x0C250 @CLK_SRC_PERIL0_OFFSET > - str r1, [r0, r2] > - > - /* wait ?us */ > - mov r1, #0x10000 > -3: subs r1, r1, #1 > - bne 3b > - > - /* > - * CLK_DIV_CPU0: > - * > - * PCLK_DBG_RATIO[20] 0x1 > - * ATB_RATIO[16] 0x3 > - * PERIPH_RATIO[12] 0x3 > - * COREM1_RATIO[8] 0x7 > - * COREM0_RATIO[4] 0x3 > - */ > - ldr r1, =0x0133730 > - ldr r2, =0x14500 @CLK_DIV_CPU0_OFFSET > - str r1, [r0, r2] > - > - /* CLK_DIV_CPU1: COPY_RATIO [0] 0x3 */ > - ldr r1, =0x03 > - ldr r2, =0x14504 @CLK_DIV_CPU1_OFFSET > - str r1, [r0, r2] > - > - /* > - * CLK_DIV_DMC0: > - * > - * CORE_TIMERS_RATIO[28] 0x1 > - * COPY2_RATIO[24] 0x3 > - * DMCP_RATIO[20] 0x1 > - * DMCD_RATIO[16] 0x1 > - * DMC_RATIO[12] 0x1 > - * DPHY_RATIO[8] 0x1 > - * ACP_PCLK_RATIO[4] 0x1 > - * ACP_RATIO[0] 0x3 > - */ > - ldr r1, =0x13111113 > - ldr r2, =0x010500 @CLK_DIV_DMC0_OFFSET > - str r1, [r0, r2] > - > - /* > - * CLK_DIV_DMC1: > - * > - * DPM_RATIO[24] 0x1 > - * DVSEM_RATIO[16] 0x1 > - * PWI_RATIO[8] 0x1 > - */ > - ldr r1, =0x01010100 > - ldr r2, =0x010504 @CLK_DIV_DMC1_OFFSET > - str r1, [r0, r2] > - > - /* > - * CLK_DIV_LEFRBUS: > - * > - * GPL_RATIO[4] 0x1 > - * GDL_RATIO[0] 0x3 > - */ > - ldr r1, =0x013 > - ldr r2, =0x04500 @CLK_DIV_LEFTBUS_OFFSET > - str r1, [r0, r2] > - > - /* > - * CLK_DIV_RIGHTBUS: > - * > - * GPR_RATIO[4] 0x1 > - * GDR_RATIO[0] 0x3 > - */ > - ldr r1, =0x013 > - ldr r2, =0x08500 @CLK_DIV_RIGHTBUS_OFFSET > - str r1, [r0, r2] > - > - /* > - * CLK_DIV_TOP: > - * > - * ONENAND_RATIO[16] 0x0 > - * ACLK_133_RATIO[12] 0x5 > - * ACLK_160_RATIO[8] 0x4 > - * ACLK_100_RATIO[4] 0x7 > - * ACLK_200_RATIO[0] 0x3 > - */ > - ldr r1, =0x05473 > - ldr r2, =0x0C510 @CLK_DIV_TOP_OFFSET > - str r1, [r0, r2] > - > - /* MMC[0:1] */ > - ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ > - ldr r2, =0x0C544 @ CLK_DIV_FSYS1 > - str r1, [r0, r2] > - > - /* MMC[2:3] */ > - ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ > - ldr r2, =0x0C548 @ CLK_DIV_FSYS2 > - str r1, [r0, r2] > - > - /* MMC4 */ > - ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */ > - ldr r2, =0x0C54C @ CLK_DIV_FSYS3 > - str r1, [r0, r2] > - > - /* wait ?us */ > - mov r1, #0x10000 > -4: subs r1, r1, #1 > - bne 4b > - > - /* > - * CLK_DIV_PERIL0: > - * > - * UART5_RATIO[20] 8 > - * UART4_RATIO[16] 8 > - * UART3_RATIO[12] 8 > - * UART2_RATIO[8] 8 > - * UART1_RATIO[4] 8 > - * UART0_RATIO[0] 8 > - */ > - ldr r1, =0x774777 > - ldr r2, =0x0C550 @CLK_DIV_PERIL0_OFFSET > - str r1, [r0, r2] > - > - /* SLIMBUS: ???, PWM */ > - ldr r1, =0x8 > - ldr r2, =0x0C55C @ CLK_DIV_PERIL3 > - str r1, [r0, r2] > - > - /* Set PLL locktime */ > - ldr r1, =0x01C20 > - ldr r2, =0x014000 @APLL_LOCK_OFFSET > - str r1, [r0, r2] > - ldr r1, =0x01C20 > - ldr r2, =0x014008 @MPLL_LOCK_OFFSET > - str r1, [r0, r2] > - ldr r1, =0x01C20 > - ldr r2, =0x0C010 @EPLL_LOCK_OFFSET > - str r1, [r0, r2] > - ldr r1, =0x01C20 > - ldr r2, =0x0C020 @VPLL_LOCK_OFFSET > - str r1, [r0, r2] > - > - /* > - * APLL_CON1: > - * > - * APLL_AFC_ENB[31] 0x1 > - * APLL_AFC[0] 0xC > - */ > - ldr r1, =0x8000000C > - ldr r2, =0x014104 @APLL_CON1_OFFSET > - str r1, [r0, r2] > - > - /* > - * APLL_CON0: > - * > - * APLL_MDIV[16] 0xFA > - * APLL_PDIV[8] 0x6 > - * APLL_SDIV[0] 0x1 > - */ > - ldr r1, =0x80FA0601 > - ldr r2, =0x014100 @APLL_CON0_OFFSET > - str r1, [r0, r2] > - > - /* > - * MPLL_CON1: > - * > - * MPLL_AFC_ENB[31] 0x1 > - * MPLL_AFC[0] 0x1C > - */ > - ldr r1, =0x0000001C > - ldr r2, =0x01410C @MPLL_CON1_OFFSET > - str r1, [r0, r2] > - > - /* > - * MPLL_CON0: > - * > - * MPLL_MDIV[16] 0xC8 > - * MPLL_PDIV[8] 0x6 > - * MPLL_SDIV[0] 0x1 > - */ > - ldr r1, =0x80C80601 > - ldr r2, =0x014108 @MPLL_CON0_OFFSET > - str r1, [r0, r2] > - > - /* EPLL */ > - ldr r1, =0x0 > - ldr r2, =0x0C114 @EPLL_CON1_OFFSET > - str r1, [r0, r2] > - > - /* > - * EPLL_CON0: > - * > - * EPLL_MDIV[16] 0x30 > - * EPLL_PDIV[8] 0x3 > - * EPLL_SDIV[0] 0x2 > - */ > - ldr r1, =0x80300302 > - ldr r2, =0x0C110 @EPLL_CON0_OFFSET > - str r1, [r0, r2] > - > - /* > - * VPLL_CON1: > - * > - * VPLL_MRR[24] 0x11 > - * VPLL_MFR[16] 0x0 > - * VPLL_K[0] 0x400 > - */ > - ldr r1, =0x11000400 > - ldr r2, =0x0C124 @VPLL_CON1_OFFSET > - str r1, [r0, r2] > - > - /* > - * VPLL_CON0: > - * > - * VPLL_MDIV[16] 0x35 > - * VPLL_PDIV[8] 0x3 > - * VPLL_SDIV[0] 0x2 > - */ > - ldr r1, =0x80350302 > - ldr r2, =0x0C120 @VPLL_CON0_OFFSET > - str r1, [r0, r2] > - > - /* wait ?us */ > - mov r1, #0x30000 > -3: subs r1, r1, #1 > - bne 3b > - > - pop {pc} > -/* > - * uart_asm_init: Initialize UART in asm mode, 115200bps fixed. > - * void uart_asm_init(void) > - */ > - .globl uart_asm_init > -uart_asm_init: > - > - /* setup UART0-UART3 GPIOs (part1) */ > - mov r0, r7 > - ldr r1, =0x22222222 > - str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET > - ldr r1, =0x00222222 > - str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET > - > - ldr r0, =EXYNOS4_UART_BASE > - add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET > - > - ldr r1, =0x3C5 > - str r1, [r0, #0x4] > - ldr r1, =0x111 > - str r1, [r0, #0x8] > - ldr r1, =0x3 > - str r1, [r0, #0x0] > - ldr r1, =0x35 > - str r1, [r0, #0x28] > - ldr r1, =0x4 > - str r1, [r0, #0x2c] > - > - mov pc, lr > - nop > - nop > - nop > - > -/* Setting TZPC[TrustZone Protection Controller] */ > -tzpc_init: > - ldr r0, =0x10110000 > - mov r1, #0x0 > - str r1, [r0] > - mov r1, #0xff > - str r1, [r0, #0x0804] > - str r1, [r0, #0x0810] > - str r1, [r0, #0x081C] > - str r1, [r0, #0x0828] > - > - ldr r0, =0x10120000 > - mov r1, #0x0 > - str r1, [r0] > - mov r1, #0xff > - str r1, [r0, #0x0804] > - str r1, [r0, #0x0810] > - str r1, [r0, #0x081C] > - str r1, [r0, #0x0828] > - > - ldr r0, =0x10130000 > - mov r1, #0x0 > - str r1, [r0] > - mov r1, #0xff > - str r1, [r0, #0x0804] > - str r1, [r0, #0x0810] > - str r1, [r0, #0x081C] > - str r1, [r0, #0x0828] > - > - ldr r0, =0x10140000 > - mov r1, #0x0 > - str r1, [r0] > - mov r1, #0xff > - str r1, [r0, #0x0804] > - str r1, [r0, #0x0810] > - str r1, [r0, #0x081C] > - str r1, [r0, #0x0828] > - > - ldr r0, =0x10150000 > - mov r1, #0x0 > - str r1, [r0] > - mov r1, #0xff > - str r1, [r0, #0x0804] > - str r1, [r0, #0x0810] > - str r1, [r0, #0x081C] > - str r1, [r0, #0x0828] > - > - ldr r0, =0x10160000 > - mov r1, #0x0 > - str r1, [r0] > - mov r1, #0xff > - str r1, [r0, #0x0804] > - str r1, [r0, #0x0810] > - str r1, [r0, #0x081C] > - str r1, [r0, #0x0828] > - > - mov pc, lr > diff --git a/board/samsung/smdkv310/mem_setup.S b/board/samsung/smdkv310/mem_setup.S > deleted file mode 100644 > index d3b6265..0000000 > --- a/board/samsung/smdkv310/mem_setup.S > +++ /dev/null > @@ -1,365 +0,0 @@ > -/* > - * Memory setup for SMDKV310 board based on EXYNOS4210 > - * > - * Copyright (C) 2011 Samsung Electronics > - * > - * See file CREDITS for list of people who contributed to this > - * project. > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - * > - * This program is distributed in the hope that it will be useful, > - * but WITHOUT ANY WARRANTY; without even the implied warranty of > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > - * GNU General Public License for more details. > - * > - * You should have received a copy of the GNU General Public License > - * along with this program; if not, write to the Free Software > - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > - * MA 02111-1307 USA > - */ > - > -#include > - > -#define SET_MIU > - > -#define MEM_DLL > - > -#ifdef CONFIG_CLK_800_330_165 > -#define DRAM_CLK_330 > -#endif > -#ifdef CONFIG_CLK_1000_200_200 > -#define DRAM_CLK_200 > -#endif > -#ifdef CONFIG_CLK_1000_330_165 > -#define DRAM_CLK_330 > -#endif > -#ifdef CONFIG_CLK_1000_400_200 > -#define DRAM_CLK_400 > -#endif > - > - .globl mem_ctrl_asm_init > -mem_ctrl_asm_init: > - > - /* > - * Async bridge configuration at CPU_core: > - * 1: half_sync > - * 0: full_sync > - */ > - ldr r0, =0x10010350 > - mov r1, #1 > - str r1, [r0] > - > -#ifdef SET_MIU > - ldr r0, =EXYNOS4_MIU_BASE @0x10600000 > -#ifdef CONFIG_MIU_1BIT_INTERLEAVED > - ldr r1, =0x0000000c > - str r1, [r0, #0x400] @MIU_INTLV_CONFIG > - ldr r1, =0x40000000 > - str r1, [r0, #0x808] @MIU_INTLV_START_ADDR > - ldr r1, =0xbfffffff > - str r1, [r0, #0x810] @MIU_INTLV_END_ADDR > - ldr r1, =0x00000001 > - str r1, [r0, #0x800] @MIU_MAPPING_UPDATE > -#endif > -#ifdef CONFIG_MIU_2BIT_INTERLEAVED > - ldr r1, =0x2000150c > - str r1, [r0, #0x400] @MIU_INTLV_CONFIG > - ldr r1, =0x40000000 > - str r1, [r0, #0x808] @MIU_INTLV_START_ADDR > - ldr r1, =0xbfffffff > - str r1, [r0, #0x810] @MIU_INTLV_END_ADDR > - ldr r1, =0x00000001 > - str r1, [r0, #0x800] @MIU_MAPPING_UPDATE > -#endif > -#ifdef CONFIG_MIU_LINEAR > - ldr r1, =0x40000000 > - str r1, [r0, #0x818] @MIU_SINGLE_MAPPING0_START_ADDR > - ldr r1, =0x7fffffff > - str r1, [r0, #0x820] @MIU_SINGLE_MAPPING0_END_ADDR > - ldr r1, =0x80000000 > - str r1, [r0, #0x828] @MIU_SINGLE_MAPPING1_START_ADDR > - ldr r1, =0xbfffffff > - str r1, [r0, #0x830] @MIU_SINGLE_MAPPING1_END_ADDR] > - ldr r1, =0x00000006 > - str r1, [r0, #0x800] @MIU_MAPPING_UPDATE > -#endif > -#endif > - /* DREX0 */ > - ldr r0, =EXYNOS4_DMC0_BASE @0x10400000 > - > - ldr r1, =0xe0000086 > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - > - ldr r1, =0xE3855703 > - str r1, [r0, #0x44] @DMC_PHYZQCONTROL > - > - mov r2, #0x100000 > -1: subs r2, r2, #1 > - bne 1b > - > - ldr r1, =0xe000008e > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - ldr r1, =0xe0000086 > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - > - ldr r1, =0x71101008 > - str r1, [r0, #0x18] @DMC_PHYCONTROL0 > - ldr r1, =0x7110100A > - str r1, [r0, #0x18] @DMC_PHYCONTROL0 > - ldr r1, =0xe0000086 > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - ldr r1, =0x7110100B > - str r1, [r0, #0x18] @DMC_PHYCONTROL0 > - > - ldr r1, =0x00000000 > - str r1, [r0, #0x20] @DMC_PHYCONTROL2 > - > - ldr r1, =0x0FFF301a > - str r1, [r0, #0x00] @DMC_CONCONTROL > - ldr r1, =0x00312640 > - str r1, [r0, #0x04] @DMC_MEMCONTROL] > - > -#ifdef CONFIG_MIU_LINEAR > - ldr r1, =0x40e01323 > - str r1, [r0, #0x08] @DMC_MEMCONFIG0 > - ldr r1, =0x60e01323 > - str r1, [r0, #0x0C] @DMC_MEMCONFIG1 > -#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */ > - ldr r1, =0x20e01323 > - str r1, [r0, #0x08] @DMC_MEMCONFIG0 > - ldr r1, =0x40e01323 > - str r1, [r0, #0x0C] @DMC_MEMCONFIG1 > -#endif > - > - ldr r1, =0xff000000 > - str r1, [r0, #0x14] @DMC_PRECHCONFIG > - > - ldr r1, =0x000000BC > - str r1, [r0, #0x30] @DMC_TIMINGAREF > - > -#ifdef DRAM_CLK_330 > - ldr r1, =0x3545548d > - str r1, [r0, #0x34] @DMC_TIMINGROW > - ldr r1, =0x45430506 > - str r1, [r0, #0x38] @DMC_TIMINGDATA > - ldr r1, =0x4439033c > - str r1, [r0, #0x3C] @DMC_TIMINGPOWER > -#endif > -#ifdef DRAM_CLK_400 > - ldr r1, =0x4046654f > - str r1, [r0, #0x34] @DMC_TIMINGROW > - ldr r1, =0x56500506 > - str r1, [r0, #0x38] @DMC_TIMINGDATA > - ldr r1, =0x5444033d > - str r1, [r0, #0x3C] @DMC_TIMINGPOWER > -#endif > - ldr r1, =0x07000000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -2: subs r2, r2, #1 > - bne 2b > - > - ldr r1, =0x00020000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00030000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00010002 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00000328 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -3: subs r2, r2, #1 > - bne 3b > - > - ldr r1, =0x0a000000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -4: subs r2, r2, #1 > - bne 4b > - > - ldr r1, =0x07100000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -5: subs r2, r2, #1 > - bne 5b > - > - ldr r1, =0x00120000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00130000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00110002 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00100328 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -6: subs r2, r2, #1 > - bne 6b > - > - ldr r1, =0x0a100000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -7: subs r2, r2, #1 > - bne 7b > - > - ldr r1, =0xe000008e > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - ldr r1, =0xe0000086 > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - > - mov r2, #0x100000 > -8: subs r2, r2, #1 > - bne 8b > - > - /* DREX1 */ > - ldr r0, =EXYNOS4_DMC1_BASE @0x10410000 > - > - ldr r1, =0xe0000086 > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - > - ldr r1, =0xE3855703 > - str r1, [r0, #0x44] @DMC_PHYZQCONTROL > - > - mov r2, #0x100000 > -1: subs r2, r2, #1 > - bne 1b > - > - ldr r1, =0xe000008e > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - ldr r1, =0xe0000086 > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - > - ldr r1, =0x71101008 > - str r1, [r0, #0x18] @DMC_PHYCONTROL0 > - ldr r1, =0x7110100A > - str r1, [r0, #0x18] @DMC_PHYCONTROL0 > - ldr r1, =0xe0000086 > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - ldr r1, =0x7110100B > - str r1, [r0, #0x18] @DMC_PHYCONTROL0 > - > - ldr r1, =0x00000000 > - str r1, [r0, #0x20] @DMC_PHYCONTROL2 > - > - ldr r1, =0x0FFF301a > - str r1, [r0, #0x00] @DMC_CONCONTROL > - ldr r1, =0x00312640 > - str r1, [r0, #0x04] @DMC_MEMCONTROL] > - > -#ifdef CONFIG_MIU_LINEAR > - ldr r1, =0x40e01323 > - str r1, [r0, #0x08] @DMC_MEMCONFIG0 > - ldr r1, =0x60e01323 > - str r1, [r0, #0x0C] @DMC_MEMCONFIG1 > -#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */ > - ldr r1, =0x20e01323 > - str r1, [r0, #0x08] @DMC_MEMCONFIG0 > - ldr r1, =0x40e01323 > - str r1, [r0, #0x0C] @DMC_MEMCONFIG1 > -#endif > - > - ldr r1, =0xff000000 > - str r1, [r0, #0x14] @DMC_PRECHCONFIG > - > - ldr r1, =0x000000BC > - str r1, [r0, #0x30] @DMC_TIMINGAREF > - > -#ifdef DRAM_CLK_330 > - ldr r1, =0x3545548d > - str r1, [r0, #0x34] @DMC_TIMINGROW > - ldr r1, =0x45430506 > - str r1, [r0, #0x38] @DMC_TIMINGDATA > - ldr r1, =0x4439033c > - str r1, [r0, #0x3C] @DMC_TIMINGPOWER > -#endif > -#ifdef DRAM_CLK_400 > - ldr r1, =0x4046654f > - str r1, [r0, #0x34] @DMC_TIMINGROW > - ldr r1, =0x56500506 > - str r1, [r0, #0x38] @DMC_TIMINGDATA > - ldr r1, =0x5444033d > - str r1, [r0, #0x3C] @DMC_TIMINGPOWER > -#endif > - > - ldr r1, =0x07000000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -2: subs r2, r2, #1 > - bne 2b > - > - ldr r1, =0x00020000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00030000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00010002 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00000328 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -3: subs r2, r2, #1 > - bne 3b > - > - ldr r1, =0x0a000000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -4: subs r2, r2, #1 > - bne 4b > - > - ldr r1, =0x07100000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -5: subs r2, r2, #1 > - bne 5b > - > - ldr r1, =0x00120000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00130000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00110002 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - ldr r1, =0x00100328 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -6: subs r2, r2, #1 > - bne 6b > - > - ldr r1, =0x0a100000 > - str r1, [r0, #0x10] @DMC_DIRECTCMD > - > - mov r2, #0x100000 > -7: subs r2, r2, #1 > - bne 7b > - > - ldr r1, =0xe000008e > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - ldr r1, =0xe0000086 > - str r1, [r0, #0x1C] @DMC_PHYCONTROL1 > - > - mov r2, #0x100000 > -8: subs r2, r2, #1 > - bne 8b > - > - /* turn on DREX0, DREX1 */ > - ldr r0, =0x10400000 @APB_DMC_0_BASE > - ldr r1, =0x0FFF303a > - str r1, [r0, #0x00] @DMC_CONCONTROL > - > - ldr r0, =0x10410000 @APB_DMC_1_BASE > - ldr r1, =0x0FFF303a > - str r1, [r0, #0x00] @DMC_CONCONTROL > - > - mov pc, lr > diff --git a/board/samsung/smdkv310/mmc_boot.c b/board/samsung/smdkv310/mmc_boot.c > deleted file mode 100644 > index d3fc18d..0000000 > --- a/board/samsung/smdkv310/mmc_boot.c > +++ /dev/null > @@ -1,60 +0,0 @@ > -/* > - * Copyright (C) 2011 Samsung Electronics > - * > - * See file CREDITS for list of people who contributed to this > - * project. > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - * > - * This program is distributed in the hope that it will be useful, > - * but WITHOUT ANY WARRANTY; without even the implied warranty of > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > - * GNU General Public License for more details. > - * > - * You should have received a copy of the GNU General Public License > - * along with this program; if not, write to the Free Software > - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > - * MA 02111-1307 USA > - */ > - > -#include > -#include > - > -/* > -* Copy U-boot from mmc to RAM: > -* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains > -* API (Data transfer from mmc to ram) > -*/ > -void copy_uboot_to_ram(void) > -{ > - u32 (*copy_bl2)(u32, u32, u32) = (void *)COPY_BL2_FNPTR_ADDR; > - > - copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); > -} > - > -void board_init_f(unsigned long bootflag) > -{ > - __attribute__((noreturn)) void (*uboot)(void); > - copy_uboot_to_ram(); > - > - /* Jump to U-Boot image */ > - uboot = (void *)CONFIG_SYS_TEXT_BASE; > - (*uboot)(); > - /* Never returns Here */ > -} > - > -/* Place Holders */ > -void board_init_r(gd_t *id, ulong dest_addr) > -{ > - /*Function attribute is no-return*/ > - /*This Function never executes*/ > - while (1) > - ; > -} > - > -void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) > -{ > -} > diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h > index 03f896a..740ad27 100644 > --- a/include/configs/exynos5250-dt.h > +++ b/include/configs/exynos5250-dt.h > @@ -93,8 +93,6 @@ > #define CONFIG_EXTRA_ENV_SETTINGS \ > EXYNOS_DEVICE_SETTINGS > > -#define TZPC_BASE_OFFSET 0x10000 > - > /* SD/MMC configuration */ > #define CONFIG_GENERIC_MMC > #define CONFIG_MMC > @@ -102,7 +100,7 @@ > #define CONFIG_S5P_SDHCI > > #define CONFIG_BOARD_EARLY_INIT_F > - > +#define CONFIG_SKIP_LOWLEVEL_INIT > /* PWM */ > #define CONFIG_PWM > > @@ -135,12 +133,14 @@ > #define CONFIG_USB_STORAGE > > /* USB boot mode */ > +#define CONFIG_USB_BOOTING > #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 > #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 > #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 > > /* MMC SPL */ > #define CONFIG_SPL > +#define CONFIG_SPL_LIBCOMMON_SUPPORT > #define COPY_BL2_FNPTR_ADDR 0x02020030 > > /* specific .lds file */ > @@ -220,15 +220,15 @@ > #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) > #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) > > -#define OM_STAT (0x1f << 1) > +#define CONFIG_SPI_BOOTING > #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 > #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) > > #define CONFIG_DOS_PARTITION > > -#define CONFIG_IRAM_STACK 0x02050000 > +#define CONFIG_IRAM_TOP 0x02050000 > > -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) > +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_TOP > > /* I2C */ > #define CONFIG_SYS_I2C_INIT_BOARD > diff --git a/include/configs/origen.h b/include/configs/origen.h > index da59d6d..9bb22ed 100644 > --- a/include/configs/origen.h > +++ b/include/configs/origen.h > @@ -68,6 +68,8 @@ > #define CONFIG_BAUDRATE 115200 > #define EXYNOS4_DEFAULT_UART_OFFSET 0x020000 > > +#define CONFIG_SKIP_LOWLEVEL_INIT > + > /* SD/MMC configuration */ > #define CONFIG_GENERIC_MMC > #define CONFIG_MMC > @@ -146,7 +148,11 @@ > #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) > #define CONFIG_DOS_PARTITION 1 > > -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" > +#define CONFIG_SPL_TEXT_BASE 0x02021410 > +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) > + > +#define CONFIG_SYS_INIT_SP_ADDR 0x02040000 > > /* U-boot copy size from boot Media to DRAM.*/ > #define COPY_BL2_SIZE 0x80000 > @@ -155,4 +161,5 @@ > > /* Enable devicetree support */ > #define CONFIG_OF_LIBFDT > + > #endif /* __CONFIG_H */ > diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h > index a5abe11..adbcf86 100644 > --- a/include/configs/smdkv310.h > +++ b/include/configs/smdkv310.h > @@ -58,6 +58,7 @@ > /* Handling Sleep Mode*/ > #define S5P_CHECK_SLEEP 0x00000BAD > #define S5P_CHECK_DIDLE 0xBAD00000 > +#define S5P_CHECK_LPA 0xABAD0000 > > /* Size of malloc() pool */ > #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) > @@ -94,6 +95,7 @@ > > /* MMC SPL */ > #define CONFIG_SPL > +#define CONFIG_SKIP_LOWLEVEL_INIT > #define COPY_BL2_FNPTR_ADDR 0x00002488 > > #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" > @@ -145,7 +147,11 @@ > #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) > #define CONFIG_DOS_PARTITION 1 > > -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" > +#define CONFIG_SPL_TEXT_BASE 0x02021410 > +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) > + > +#define CONFIG_SYS_INIT_SP_ADDR 0x02040000 > > /* U-boot copy size from boot Media to DRAM.*/ > #define COPY_BL2_SIZE 0x80000 > diff --git a/spl/Makefile b/spl/Makefile > index b5a8de7..cdbaa7f 100644 > --- a/spl/Makefile > +++ b/spl/Makefile > @@ -94,6 +94,10 @@ LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o > LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o > endif > > +ifeq ($(SOC),exynos) > +LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o > +endif > + > # Add GCC lib > ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") > PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o >