From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andreas Naumann Date: Thu, 04 Jul 2013 16:10:58 +0200 Subject: [U-Boot] dm3730: dpll5 init broken with 19.2MHz? Message-ID: <51D58272.904@andin.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, I have a custom OMAP37xx board running with a fairly uncommon 19.2MHz oscillator. The general clock setup seems fine so far, but the dpll5_init_34xx() used in prcm_init() for 36xx cpu-types gives me trouble in the form of numerous stack dumps in the kernel boot. Reason is: [ 3.396636] clock: dpll5_ck failed transition to 'locked' In an older U-Boot (2010.09) that I used before there was no such problem (and no such dpll5 setup i guess). So after commenting the line dpll5_init_34xx(0, clk_index); in arch/arm/cpu/armv7/omap3/clock.c, the kernel does not complain anymore, but one 1 of 3 boots has the ECHI USB not working, which makes me think, I probably have to do it right. So my question is, where do the per2_dpll_param values in lowlevel_init.S come from? How can I calculate them? thanks for any help, Andreas