From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andreas Naumann Date: Tue, 09 Jul 2013 10:08:10 +0200 Subject: [U-Boot] [RFC] ARM: omap3: Add option to disable errata workarounds. In-Reply-To: <1373356832-28983-1-git-send-email-anaumann@ultratronik.de> References: <1373356832-28983-1-git-send-email-anaumann@ultratronik.de> Message-ID: <51DBC4EA.4090104@andin.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear. So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism? regards, Andreas PS. Does anybody have the "ARM Core Cortex-A8 (AT400/AT401) errata" document to make sure my assumption above holds true? --- arch/arm/cpu/armv7/omap3/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index b72fadc..84045d8 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -236,8 +236,10 @@ void s_init(void) try_unlock_memory(); +#ifndef CONFIG_SYS_DISABLE_CORTEXA8_ERRATA_WORKAROUNDS /* Errata workarounds */ omap3_setup_aux_cr(); +#endif #ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ -- 1.8.3.1