* [U-Boot] [PATCH] arm: exynos: fix clock calculation
@ 2013-07-05 10:13 Minkyu Kang
2013-07-08 5:35 ` Rajeshwari Birje
2013-07-12 17:08 ` [U-Boot] [PATCH] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets Lukasz Majewski
0 siblings, 2 replies; 9+ messages in thread
From: Minkyu Kang @ 2013-07-05 10:13 UTC (permalink / raw)
To: u-boot
There are differnce with clock calcuation by cpu variations.
This patch will fix it according to user manual.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
arch/arm/cpu/armv7/exynos/clock.c | 37 +++++++++++++++++++++++++++++++++----
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index e1c4246..da43373 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -85,6 +85,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
{
unsigned long m, p, s = 0, mask, fout;
+ unsigned int div;
unsigned int freq;
/*
* APLL_CON: MIDV [25:16]
@@ -113,11 +114,39 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
fout = (m + k / 65536) * (freq / (p * (1 << s)));
} else if (pllreg == VPLL) {
k = k & 0xfff;
- /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 1024) * (freq / (p * (1 << s)));
+
+ /*
+ * Exynos4210
+ * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
+ *
+ * Exynos4412
+ * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
+ *
+ * Exynos5250
+ * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
+ */
+ if (proid_is_exynos4210())
+ div = 1024;
+ else if (proid_is_exynos4412())
+ div = 65535;
+ else if (proid_is_exynos5250())
+ div = 65536;
+ else
+ return 0;
+
+ fout = (m + k / div) * (freq / (p * (1 << s)));
} else {
- /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
- fout = m * (freq / (p * (1 << s)));
+ /*
+ * Exynos4210
+ * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
+ *
+ * Exynos4412 / Exynos5250
+ * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
+ */
+ if (proid_is_exynos4210())
+ fout = m * (freq / (p * (1 << s)));
+ else
+ fout = m * (freq / (p * (1 << (s - 1))));
}
return fout;
--
1.7.9.5
--
Thanks,
Minkyu Kang.
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH] arm: exynos: fix clock calculation
2013-07-05 10:13 [U-Boot] [PATCH] arm: exynos: fix clock calculation Minkyu Kang
@ 2013-07-08 5:35 ` Rajeshwari Birje
2013-07-09 7:37 ` [U-Boot] [PATCH v2] " Minkyu Kang
2013-07-12 17:08 ` [U-Boot] [PATCH] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets Lukasz Majewski
1 sibling, 1 reply; 9+ messages in thread
From: Rajeshwari Birje @ 2013-07-08 5:35 UTC (permalink / raw)
To: u-boot
Hi Minkyu Kang,
On Fri, Jul 5, 2013 at 3:43 PM, Minkyu Kang <mk7.kang@samsung.com> wrote:
> There are differnce with clock calcuation by cpu variations.
> This patch will fix it according to user manual.
>
> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 37 +++++++++++++++++++++++++++++++++----
> 1 file changed, 33 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index e1c4246..da43373 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -85,6 +85,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
> static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
> {
> unsigned long m, p, s = 0, mask, fout;
> + unsigned int div;
> unsigned int freq;
> /*
> * APLL_CON: MIDV [25:16]
> @@ -113,11 +114,39 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
> fout = (m + k / 65536) * (freq / (p * (1 << s)));
> } else if (pllreg == VPLL) {
> k = k & 0xfff;
> - /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
> - fout = (m + k / 1024) * (freq / (p * (1 << s)));
> +
> + /*
> + * Exynos4210
> + * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
> + *
> + * Exynos4412
> + * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
> + *
> + * Exynos5250
> + * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
> + */
> + if (proid_is_exynos4210())
> + div = 1024;
Cannot we remove these hard codings for div?
> + else if (proid_is_exynos4412())
> + div = 65535;
> + else if (proid_is_exynos5250())
> + div = 65536;
> + else
> + return 0;
> +
> + fout = (m + k / div) * (freq / (p * (1 << s)));
> } else {
> - /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
> - fout = m * (freq / (p * (1 << s)));
> + /*
> + * Exynos4210
> + * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
> + *
> + * Exynos4412 / Exynos5250
> + * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
> + */
> + if (proid_is_exynos4210())
> + fout = m * (freq / (p * (1 << s)));
> + else
> + fout = m * (freq / (p * (1 << (s - 1))));
> }
>
> return fout;
> --
> 1.7.9.5
>
> --
> Thanks,
> Minkyu Kang.
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v2] arm: exynos: fix clock calculation
2013-07-08 5:35 ` Rajeshwari Birje
@ 2013-07-09 7:37 ` Minkyu Kang
2013-07-09 7:56 ` Rajeshwari Birje
0 siblings, 1 reply; 9+ messages in thread
From: Minkyu Kang @ 2013-07-09 7:37 UTC (permalink / raw)
To: u-boot
There are differnce with clock calcuation by cpu variations.
This patch will fix it according to user manual.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
Changes for v2:
- remove hard-coded constants.
arch/arm/cpu/armv7/exynos/clock.c | 43 ++++++++++++++++++++++++++++++++-----
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index e1c4246..9f07181 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -27,6 +27,10 @@
#include <asm/arch/clk.h>
#include <asm/arch/periph.h>
+#define PLL_DIV_1024 1024
+#define PLL_DIV_65535 65535
+#define PLL_DIV_65536 65536
+
/* *
* This structure is to store the src bit, div bit and prediv bit
* positions of the peripheral clocks of the src and div registers
@@ -85,6 +89,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
{
unsigned long m, p, s = 0, mask, fout;
+ unsigned int div;
unsigned int freq;
/*
* APLL_CON: MIDV [25:16]
@@ -110,14 +115,42 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
if (pllreg == EPLL) {
k = k & 0xffff;
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 65536) * (freq / (p * (1 << s)));
+ fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
} else if (pllreg == VPLL) {
k = k & 0xfff;
- /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 1024) * (freq / (p * (1 << s)));
+
+ /*
+ * Exynos4210
+ * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
+ *
+ * Exynos4412
+ * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
+ *
+ * Exynos5250
+ * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
+ */
+ if (proid_is_exynos4210())
+ div = PLL_DIV_1024;
+ else if (proid_is_exynos4412())
+ div = PLL_DIV_65535;
+ else if (proid_is_exynos5250())
+ div = PLL_DIV_65536;
+ else
+ return 0;
+
+ fout = (m + k / div) * (freq / (p * (1 << s)));
} else {
- /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
- fout = m * (freq / (p * (1 << s)));
+ /*
+ * Exynos4210
+ * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
+ *
+ * Exynos4412 / Exynos5250
+ * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
+ */
+ if (proid_is_exynos4210())
+ fout = m * (freq / (p * (1 << s)));
+ else
+ fout = m * (freq / (p * (1 << (s - 1))));
}
return fout;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v2] arm: exynos: fix clock calculation
2013-07-09 7:37 ` [U-Boot] [PATCH v2] " Minkyu Kang
@ 2013-07-09 7:56 ` Rajeshwari Birje
2013-07-10 4:43 ` Minkyu Kang
0 siblings, 1 reply; 9+ messages in thread
From: Rajeshwari Birje @ 2013-07-09 7:56 UTC (permalink / raw)
To: u-boot
Looks fine to me.
Acked-by: Rajeshwari Shinde<rajeshwari.s@samsung.com>
On Tue, Jul 9, 2013 at 1:07 PM, Minkyu Kang <mk7.kang@samsung.com> wrote:
> There are differnce with clock calcuation by cpu variations.
> This patch will fix it according to user manual.
>
> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
> Changes for v2:
> - remove hard-coded constants.
>
> arch/arm/cpu/armv7/exynos/clock.c | 43 ++++++++++++++++++++++++++++++++-----
> 1 file changed, 38 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index e1c4246..9f07181 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -27,6 +27,10 @@
> #include <asm/arch/clk.h>
> #include <asm/arch/periph.h>
>
> +#define PLL_DIV_1024 1024
> +#define PLL_DIV_65535 65535
> +#define PLL_DIV_65536 65536
> +
> /* *
> * This structure is to store the src bit, div bit and prediv bit
> * positions of the peripheral clocks of the src and div registers
> @@ -85,6 +89,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
> static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
> {
> unsigned long m, p, s = 0, mask, fout;
> + unsigned int div;
> unsigned int freq;
> /*
> * APLL_CON: MIDV [25:16]
> @@ -110,14 +115,42 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
> if (pllreg == EPLL) {
> k = k & 0xffff;
> /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
> - fout = (m + k / 65536) * (freq / (p * (1 << s)));
> + fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
> } else if (pllreg == VPLL) {
> k = k & 0xfff;
> - /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
> - fout = (m + k / 1024) * (freq / (p * (1 << s)));
> +
> + /*
> + * Exynos4210
> + * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
> + *
> + * Exynos4412
> + * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
> + *
> + * Exynos5250
> + * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
> + */
> + if (proid_is_exynos4210())
> + div = PLL_DIV_1024;
> + else if (proid_is_exynos4412())
> + div = PLL_DIV_65535;
> + else if (proid_is_exynos5250())
> + div = PLL_DIV_65536;
> + else
> + return 0;
> +
> + fout = (m + k / div) * (freq / (p * (1 << s)));
> } else {
> - /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
> - fout = m * (freq / (p * (1 << s)));
> + /*
> + * Exynos4210
> + * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
> + *
> + * Exynos4412 / Exynos5250
> + * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
> + */
> + if (proid_is_exynos4210())
> + fout = m * (freq / (p * (1 << s)));
> + else
> + fout = m * (freq / (p * (1 << (s - 1))));
> }
>
> return fout;
> --
> 1.7.9.5
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v2] arm: exynos: fix clock calculation
2013-07-09 7:56 ` Rajeshwari Birje
@ 2013-07-10 4:43 ` Minkyu Kang
0 siblings, 0 replies; 9+ messages in thread
From: Minkyu Kang @ 2013-07-10 4:43 UTC (permalink / raw)
To: u-boot
On 09/07/13 16:56, Rajeshwari Birje wrote:
> Looks fine to me.
>
> Acked-by: Rajeshwari Shinde<rajeshwari.s@samsung.com>
>
> On Tue, Jul 9, 2013 at 1:07 PM, Minkyu Kang <mk7.kang@samsung.com> wrote:
>> There are differnce with clock calcuation by cpu variations.
>> This patch will fix it according to user manual.
>>
>> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> ---
>> Changes for v2:
>> - remove hard-coded constants.
>>
>> arch/arm/cpu/armv7/exynos/clock.c | 43 ++++++++++++++++++++++++++++++++-----
>> 1 file changed, 38 insertions(+), 5 deletions(-)
>>
applied to u-boot-samsung.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.
2013-07-05 10:13 [U-Boot] [PATCH] arm: exynos: fix clock calculation Minkyu Kang
2013-07-08 5:35 ` Rajeshwari Birje
@ 2013-07-12 17:08 ` Lukasz Majewski
2013-07-13 9:28 ` Minkyu Kang
` (2 more replies)
1 sibling, 3 replies; 9+ messages in thread
From: Lukasz Majewski @ 2013-07-12 17:08 UTC (permalink / raw)
To: u-boot
Provide proper setting for the APLL fout frequency calculation for
Exynos4 based targets (especially Exynos4210 - Trats board).
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
---
arch/arm/cpu/armv7/exynos/clock.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 9f07181..5a5cfa1 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -141,18 +141,17 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
fout = (m + k / div) * (freq / (p * (1 << s)));
} else {
/*
- * Exynos4210
+ * Exynos4412 / Exynos5250
* FOUT = MDIV * FIN / (PDIV * 2^SDIV)
*
- * Exynos4412 / Exynos5250
+ * Exynos4210
* FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
*/
if (proid_is_exynos4210())
- fout = m * (freq / (p * (1 << s)));
- else
fout = m * (freq / (p * (1 << (s - 1))));
+ else
+ fout = m * (freq / (p * (1 << s)));
}
-
return fout;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.
2013-07-12 17:08 ` [U-Boot] [PATCH] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets Lukasz Majewski
@ 2013-07-13 9:28 ` Minkyu Kang
2013-07-16 0:52 ` Simon Glass
2013-07-16 14:37 ` [U-Boot] " Tom Rini
2 siblings, 0 replies; 9+ messages in thread
From: Minkyu Kang @ 2013-07-13 9:28 UTC (permalink / raw)
To: u-boot
Dear Tom,
Please apply this patch to u-boot directly.
I wish that this fix will be merged before release.
On 13 July 2013 02:08, Lukasz Majewski <l.majewski@samsung.com> wrote:
> Provide proper setting for the APLL fout frequency calculation for
> Exynos4 based targets (especially Exynos4210 - Trats board).
>
>
> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
> Cc: Minkyu Kang <mk7.kang@samsung.com>
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Thanks for patch.
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.
2013-07-12 17:08 ` [U-Boot] [PATCH] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets Lukasz Majewski
2013-07-13 9:28 ` Minkyu Kang
@ 2013-07-16 0:52 ` Simon Glass
2013-07-16 14:37 ` [U-Boot] " Tom Rini
2 siblings, 0 replies; 9+ messages in thread
From: Simon Glass @ 2013-07-16 0:52 UTC (permalink / raw)
To: u-boot
On Fri, Jul 12, 2013 at 11:08 AM, Lukasz Majewski <l.majewski@samsung.com>wrote:
> Provide proper setting for the APLL fout frequency calculation for
> Exynos4 based targets (especially Exynos4210 - Trats board).
>
>
> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
> Cc: Minkyu Kang <mk7.kang@samsung.com>
>
This also fixes booting on snow.
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index 9f07181..5a5cfa1 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -141,18 +141,17 @@ static int exynos_get_pll_clk(int pllreg, unsigned
> int r, unsigned int k)
> fout = (m + k / div) * (freq / (p * (1 << s)));
> } else {
> /*
> - * Exynos4210
> + * Exynos4412 / Exynos5250
> * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
> *
> - * Exynos4412 / Exynos5250
> + * Exynos4210
> * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
> */
> if (proid_is_exynos4210())
> - fout = m * (freq / (p * (1 << s)));
> - else
> fout = m * (freq / (p * (1 << (s - 1))));
> + else
> + fout = m * (freq / (p * (1 << s)));
> }
> -
> return fout;
> }
>
> --
> 1.7.10.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 9+ messages in thread* [U-Boot] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.
2013-07-12 17:08 ` [U-Boot] [PATCH] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets Lukasz Majewski
2013-07-13 9:28 ` Minkyu Kang
2013-07-16 0:52 ` Simon Glass
@ 2013-07-16 14:37 ` Tom Rini
2 siblings, 0 replies; 9+ messages in thread
From: Tom Rini @ 2013-07-16 14:37 UTC (permalink / raw)
To: u-boot
On Fri, Jul 12, 2013 at 07:08:25PM +0200, ??ukasz Majewski wrote:
> Provide proper setting for the APLL fout frequency calculation for
> Exynos4 based targets (especially Exynos4210 - Trats board).
>
>
> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
> Cc: Minkyu Kang <mk7.kang@samsung.com>
> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20130716/66563353/attachment.pgp>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2013-07-16 14:37 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-07-05 10:13 [U-Boot] [PATCH] arm: exynos: fix clock calculation Minkyu Kang
2013-07-08 5:35 ` Rajeshwari Birje
2013-07-09 7:37 ` [U-Boot] [PATCH v2] " Minkyu Kang
2013-07-09 7:56 ` Rajeshwari Birje
2013-07-10 4:43 ` Minkyu Kang
2013-07-12 17:08 ` [U-Boot] [PATCH] arm:exynos:fix: Fix clock calculation for Exynos4210 based targets Lukasz Majewski
2013-07-13 9:28 ` Minkyu Kang
2013-07-16 0:52 ` Simon Glass
2013-07-16 14:37 ` [U-Boot] " Tom Rini
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox