[U-Boot] [PATCH 1/7] omap5: add qspi support

Sourav Poddar
2013-07-11T06:17:52Z

On Wednesday 10 July 2013 07:10 PM, Lokesh Vutla wrote:
> On Wednesday 10 July 2013 04:55 PM, Sourav Poddar wrote:
>> From: Matt Porter<mporter@ti.com>
>>
>> Add QSPI definitions and clock configuration support.
>>
>> Signed-off-by: Matt Porter<mporter@ti.com>
>> Signed-off-by: Sourav Poddar<sourav.poddar@ti.com>
>> ---
>> arch/arm/cpu/armv7/omap5/hw_data.c | 7 ++++++-
>> arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 +
>> arch/arm/include/asm/arch-omap5/omap.h | 3 +++
>> arch/arm/include/asm/arch-omap5/spl.h | 1 +
>> arch/arm/include/asm/omap_common.h | 1 +
>> 5 files changed, 12 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
>> index 9374c6a..046ce44 100644
>> --- a/arch/arm/cpu/armv7/omap5/hw_data.c
>> +++ b/arch/arm/cpu/armv7/omap5/hw_data.c
>> @@ -186,7 +186,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
>>
>> static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
>> {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
>> - {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
>> + {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
>> {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
>> {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
>> {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
>> @@ -423,6 +423,7 @@ void enable_basic_clocks(void)
>> (*prcm)->cm_wkup_wdtimer2_clkctrl,
>> (*prcm)->cm_l4per_uart3_clkctrl,
>> (*prcm)->cm_l4per_i2c1_clkctrl,
>> + (*prcm)->cm_l4per_qspi_clkctrl,
> Keep this also under CONFIG_TI_QSPI because we should enable QSPI clocks
> only if support is available.
>
Ok.
> Thanks,
> Lokesh
>> 0
>> };
>>
>> @@ -451,6 +452,10 @@ void enable_basic_clocks(void)
>> clk_modules_explicit_en_essential,
>> 1);
>>
>> +#ifdef CONFIG_TI_QSPI
>> + setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
>> +#endif
>> +
>> /* Enable SCRM OPT clocks for PER and CORE dpll */
>> setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
>> OPTFCLKEN_SCRM_PER_MASK);
>> diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
>> index 331117c..debc56b 100644
>> --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
>> +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
>> @@ -926,6 +926,7 @@ struct prcm_regs const dra7xx_prcm = {
>> .cm_l4per_gpio8_clkctrl = 0x4a009818,
>> .cm_l4per_mmcsd3_clkctrl = 0x4a009820,
>> .cm_l4per_mmcsd4_clkctrl = 0x4a009828,
>> + .cm_l4per_qspi_clkctrl = 0x4a009838,
>> .cm_l4per_uart1_clkctrl = 0x4a009840,
>> .cm_l4per_uart2_clkctrl = 0x4a009848,
>> .cm_l4per_uart3_clkctrl = 0x4a009850,
>> diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
>> index e7d79fc..d2c4930 100644
>> --- a/arch/arm/include/asm/arch-omap5/omap.h
>> +++ b/arch/arm/include/asm/arch-omap5/omap.h
>> @@ -67,6 +67,9 @@
>> /* GPMC */
>> #define OMAP54XX_GPMC_BASE 0x50000000
>>
>> +/* QSPI */
>> +#define QSPI_BASE 0x4B300000
>> +
>> /*
>> * Hardware Register Details
>> */
>> diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h
>> index d4d353c..8905cb8 100644
>> --- a/arch/arm/include/asm/arch-omap5/spl.h
>> +++ b/arch/arm/include/asm/arch-omap5/spl.h
>> @@ -31,6 +31,7 @@
>> #define BOOT_DEVICE_MMC1 5
>> #define BOOT_DEVICE_MMC2 6
>> #define BOOT_DEVICE_MMC2_2 7
>> +#define BOOT_DEVICE_SPI 10
>>
>> #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
>> #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
>> diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
>> index fa28358..c8d4619 100644
>> --- a/arch/arm/include/asm/omap_common.h
>> +++ b/arch/arm/include/asm/omap_common.h
>> @@ -279,6 +279,7 @@ struct prcm_regs {
>> u32 cm_l4per_mmcsd4_clkctrl;
>> u32 cm_l4per_msprohg_clkctrl;
>> u32 cm_l4per_slimbus2_clkctrl;
>> + u32 cm_l4per_qspi_clkctrl;
>> u32 cm_l4per_uart1_clkctrl;
>> u32 cm_l4per_uart2_clkctrl;
>> u32 cm_l4per_uart3_clkctrl;
>>