From mboxrd@z Thu Jan  1 00:00:00 1970
From: Nishanth Menon <menon.nishanth@gmail.com>
Date: Wed, 10 Jul 2013 18:58:53 -0500
Subject: [U-Boot] [PATCH 3/7] dra7xx_evm: add SPL API, QSPI,
 and serial flash support
In-Reply-To: <51DD65EF.1030501@ti.com>
References: <1373455541-8184-1-git-send-email-sourav.poddar@ti.com>
	<1373455541-8184-4-git-send-email-sourav.poddar@ti.com>
	<51DD65EF.1030501@ti.com>
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[...]
>> diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
>> index 338a241..2441c55 100644
>> --- a/board/ti/dra7xx/mux_data.h
>> +++ b/board/ti/dra7xx/mux_data.h
>> @@ -53,5 +53,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
>>   	{UART1_RTSN, (IEN | PTU | PDIS | M3)},	/* UART1_RTSN */
>>   	{I2C1_SDA, (IEN | PTU | PDIS | M0)},	/* I2C1_SDA */
>>   	{I2C1_SCL, (IEN | PTU | PDIS | M0)},	/* I2C1_SCL */
>> +	{GPMC_A13, (IEN | PDIS | M1)},	/* QSPI1_RTCLK */
>> +	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
>> +	{GPMC_A15, (IEN | PDIS | M1)},	/* QSPI1_D[2] */
>> +	{GPMC_A16, (IEN | PDIS | M1)},	/* QSPI1_D[1] */
>> +	{GPMC_A17, (IEN | PDIS | M1)},	/* QSPI1_D[0] */
>> +	{GPMC_A18, (IEN | PDIS | M1)},	/* QSPI1_SCLK */
>> +	{GPMC_A3, (IEN | PDIS | M1)},	/* QSPI1_CS2 */
>> +	{GPMC_A4, (IEN | PDIS | M1)},	/* QSPI1_CS3 */
>> +	{GPMC_CS2, (IEN | PTU | PDIS | M1)},	/* QSPI1_CS0 */
>> +	{GPMC_CS3, (IEN | PTU | PDIS | M1)},	/* QSPI1_CS1*/
Just a nitpick - Could someone audit this to ensure that only input/full 
duplex pins are set to IEN(Input Enable)?
Chip select (CS), SCLK, RTCLK dont seem to be candidates for input to DRA.

---
Regards,
Nishanth Menon