From mboxrd@z Thu Jan 1 00:00:00 1970 From: Troy Kisky Date: Mon, 15 Jul 2013 14:18:24 -0700 Subject: [U-Boot] [PATCH] net: fec: Avoid MX28 bus sync issue In-Reply-To: <20130715222043.0e81e9f3@lilith> References: <1373583784-7129-1-git-send-email-marex@denx.de> <51E0BEBB.3070400@boundarydevices.com> <20130715154153.7578a3b8@lilith> <51E433EA.1070309@boundarydevices.com> <20130715222043.0e81e9f3@lilith> Message-ID: <51E46720.1080001@boundarydevices.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 7/15/2013 1:20 PM, Albert ARIBAUD wrote: > Hi Troy, > > On Mon, 15 Jul 2013 10:39:54 -0700, Troy Kisky > wrote: > >>> Besides, Marek and I had in fact investigated barriers, adding some as >>> I did in times past in mvgbe.c, and fiddling with the one already in >>> dcache_flush_range(). None of this had any effect. >> You tried adding a dsb() to dcache_flush_range()? >> That should have fixed the problem as well. > There already was a memory barrier -- the only one kind known bu > ARM926J-S, which is a write buffer(s) drain -- and no, it should not > have fixed the problem (and did not), because the issue is not about > pushing the transactions out of the CPU soon enough; it is about having > the EMI perform them before it passes our 'go' command to the ENET DMA. > Thanks for straightening me out. My back just popped a couple of times. Troy