From: Stephen Warren <swarren@wwwdotorg.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific
Date: Thu, 18 Jul 2013 22:42:16 -0600 [thread overview]
Message-ID: <51E8C3A8.3050003@wwwdotorg.org> (raw)
In-Reply-To: <20130719023843.GA14413@mithrandir>
On 07/18/2013 08:38 PM, Thierry Reding wrote:
> On Thu, Jul 18, 2013 at 03:19:18PM -0600, Stephen Warren wrote:
>> On 07/18/2013 01:13 PM, Thierry Reding wrote:
>>> From: Thierry Reding <treding@nvidia.com>
>>>
>>> Currently all Tegra SoCs are assumed to have 32 byte cache
>>> lines. This isn't true for Tegra114, however, which uses 4
>>> Cortex-A15 cores and therefore uses a cache line size of 64
>>> bytes. Move the cache line size setting to the per-SoC common
>>> configuration file.
>>
>> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by:
>> Stephen Warren <swarren@nvidia.com>
>
> Do these apply to patch 2 of this series as well?
Yes, the whole series.
next prev parent reply other threads:[~2013-07-19 4:42 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-18 19:13 [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific Thierry Reding
2013-07-18 19:13 ` [U-Boot] [PATCH 2/2] ARM: tegra: Enable data cache on Dalmore Thierry Reding
2013-07-18 21:19 ` [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific Stephen Warren
2013-07-19 2:38 ` Thierry Reding
2013-07-19 4:42 ` Stephen Warren [this message]
2013-08-14 16:05 ` Stephen Warren
2013-08-14 16:30 ` Tom Warren
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