From: Troy Kisky <troy.kisky@boundarydevices.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030
Date: Fri, 19 Jul 2013 14:34:55 -0700 [thread overview]
Message-ID: <51E9B0FF.40102@boundarydevices.com> (raw)
In-Reply-To: <CAOMZO5DvVEk+oF90yoHCNC1fx_Pp1jnFD9bTWD_WbU2=1C9V6A@mail.gmail.com>
On 7/19/2013 2:00 PM, Fabio Estevam wrote:
> Hi Troy,
>
> On Wed, Jul 17, 2013 at 4:46 PM, Troy Kisky
> <troy.kisky@boundarydevices.com> wrote:
>> The old value of 0x000e0030 will cause ethernet
>> timeout issues on the sabrelite and possibly other
>> boards using the KSZ9021.
>> I have no explanation as to why.
>>
>> But this is a correct change, the TRM will be updated
>> to show that 00b is the only valid setting for bits
>> 19-18 of DRAM_RESET.
>>
>> My thanks go to Liu Hui(Jason) for this information.
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> Should this go into 2013.07?
>
If not too late. It only affect Nitrogen6x, at least until Sabrelite is
combined with it.
And Sabrelite is already using this value.
Troy
next prev parent reply other threads:[~2013-07-19 21:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-17 19:46 [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030 Troy Kisky
2013-07-19 21:00 ` Fabio Estevam
2013-07-19 21:34 ` Troy Kisky [this message]
2013-07-19 21:50 ` Tom Rini
2013-07-19 22:04 ` Fabio Estevam
2013-07-20 16:01 ` Stefano Babic
2013-07-20 16:14 ` Tom Rini
2013-07-19 21:54 ` Fabio Estevam
2013-07-22 6:27 ` Dirk Behme
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