From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Sat, 20 Jul 2013 18:01:56 +0200 Subject: [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030 In-Reply-To: <20130719215049.GO18359@bill-the-cat> References: <1374090375-21216-1-git-send-email-troy.kisky@boundarydevices.com> <51E9B0FF.40102@boundarydevices.com> <20130719215049.GO18359@bill-the-cat> Message-ID: <51EAB474.9070007@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Tom, Am 19/07/2013 23:50, schrieb Tom Rini: > On Fri, Jul 19, 2013 at 02:34:55PM -0700, Troy Kisky wrote: >> On 7/19/2013 2:00 PM, Fabio Estevam wrote: >>> Hi Troy, >>> >>> On Wed, Jul 17, 2013 at 4:46 PM, Troy Kisky >>> wrote: >>>> The old value of 0x000e0030 will cause ethernet >>>> timeout issues on the sabrelite and possibly other >>>> boards using the KSZ9021. >>>> I have no explanation as to why. >>>> >>>> But this is a correct change, the TRM will be updated >>>> to show that 00b is the only valid setting for bits >>>> 19-18 of DRAM_RESET. >>>> >>>> My thanks go to Liu Hui(Jason) for this information. >>>> >>>> Signed-off-by: Troy Kisky >>> Should this go into 2013.07? >>> >> >> If not too late. It only affect Nitrogen6x, at least until Sabrelite >> is combined with it. >> And Sabrelite is already using this value. > > Whose acks should I wait for on this? Acked-by: Stefano Babic