From: Dirk Behme <dirk.behme@de.bosch.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030
Date: Mon, 22 Jul 2013 08:27:59 +0200 [thread overview]
Message-ID: <51ECD0EF.3030703@de.bosch.com> (raw)
In-Reply-To: <1374090375-21216-1-git-send-email-troy.kisky@boundarydevices.com>
On 17.07.2013 21:46, Troy Kisky wrote:
> The old value of 0x000e0030 will cause ethernet
> timeout issues on the sabrelite and possibly other
> boards using the KSZ9021.
> I have no explanation as to why.
>
> But this is a correct change, the TRM will be updated
> to show that 00b is the only valid setting for bits
> 19-18 of DRAM_RESET.
>
> My thanks go to Liu Hui(Jason) for this information.
>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Thanks
Dirk
> ---
> board/boundary/nitrogen6x/ddr-setup.cfg | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg
> index c315812..e5f8add 100644
> --- a/board/boundary/nitrogen6x/ddr-setup.cfg
> +++ b/board/boundary/nitrogen6x/ddr-setup.cfg
> @@ -74,7 +74,7 @@ DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
> DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
> DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
>
> -DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030
> +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
> DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
> DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
prev parent reply other threads:[~2013-07-22 6:27 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-17 19:46 [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030 Troy Kisky
2013-07-19 21:00 ` Fabio Estevam
2013-07-19 21:34 ` Troy Kisky
2013-07-19 21:50 ` Tom Rini
2013-07-19 22:04 ` Fabio Estevam
2013-07-20 16:01 ` Stefano Babic
2013-07-20 16:14 ` Tom Rini
2013-07-19 21:54 ` Fabio Estevam
2013-07-22 6:27 ` Dirk Behme [this message]
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