From: Sean Anderson <seanga2@gmail.com>
To: Weijie Gao <weijie.gao@mediatek.com>, u-boot@lists.denx.de
Cc: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,
Lukasz Majewski <lukma@denx.de>
Subject: Re: [PATCH 23/31] clk: mediatek: add support to configure clock driver parent
Date: Sat, 13 Aug 2022 00:18:05 -0400 [thread overview]
Message-ID: <51eddb1d-c9d5-34d5-cedf-07acd9ae34a5@gmail.com> (raw)
In-Reply-To: <239a96b2760e0a014b9046cd94b7760317c24511.1659581119.git.weijie.gao@mediatek.com>
On 8/3/22 11:36 PM, Weijie Gao wrote:
> This patch adds support for a clock node to configure its parent clock
> where possible.
>
> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
> ---
> drivers/clk/mediatek/clk-mtk.c | 79 ++++++++++++++++++++--------------
> drivers/clk/mediatek/clk-mtk.h | 2 +
> 2 files changed, 48 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> index d99ea55df0..908ed2b4ba 100644
> --- a/drivers/clk/mediatek/clk-mtk.c
> +++ b/drivers/clk/mediatek/clk-mtk.c
> @@ -42,20 +42,14 @@
> * the accurate frequency.
> */
> static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
> - const struct driver *drv)
> + struct udevice *pdev)
> {
> struct clk parent = { .id = id, };
>
> - if (drv) {
> - struct udevice *dev;
> -
> - if (uclass_get_device_by_driver(UCLASS_CLK, drv, &dev))
> - return -ENODEV;
> -
> - parent.dev = dev;
> - } else {
> + if (pdev)
> + parent.dev = pdev;
> + else
> parent.dev = clk->dev;
> - }
>
> return clk_get_rate(&parent);
You must call clk_request(parent) before calling clk_get_rate.
> }
> @@ -296,7 +290,7 @@ static ulong mtk_topckgen_get_factor_rate(struct clk
> *clk, u32 off)
> switch (fdiv->flags & CLK_PARENT_MASK) {
> case CLK_PARENT_APMIXED:
> rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
> - DM_DRIVER_GET(mtk_clk_apmixedsys));
> + priv->parent);
> break;
> case CLK_PARENT_TOPCKGEN:
> rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
> @@ -322,9 +316,18 @@ static ulong mtk_topckgen_get_mux_rate(struct clk *clk,
> u32 off)
>
> if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL)
> flag = 1;
> - if (mux->parent[index] > 0 || flag == 1)
> - return mtk_clk_find_parent_rate(clk, mux->parent[index],
> - NULL);
> + if (mux->parent[index] > 0 || flag == 1) {
> + switch (mux->flags & CLK_PARENT_MASK) {
> + case CLK_PARENT_APMIXED:
> + return mtk_clk_find_parent_rate(clk, mux->parent[index],
> + priv->parent);
> + break;
> + default:
> + return mtk_clk_find_parent_rate(clk, mux->parent[index],
> + NULL);
> + break;
> + }
> + }
>
> return priv->tree->xtal_rate;
> }
> @@ -343,7 +346,7 @@ static ulong mtk_topckgen_get_rate(struct clk *clk)
> priv->tree->muxes_offs);
> }
>
> -static int mtk_topckgen_enable(struct clk *clk)
> +static int mtk_clk_mux_enable(struct clk *clk)
> {
> struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
> const struct mtk_composite *mux;
> @@ -376,7 +379,7 @@ static int mtk_topckgen_enable(struct clk *clk)
> return 0;
> }
>
> -static int mtk_topckgen_disable(struct clk *clk)
> +static int mtk_clk_mux_disable(struct clk *clk)
> {
> struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
> const struct mtk_composite *mux;
> @@ -402,7 +405,7 @@ static int mtk_topckgen_disable(struct clk *clk)
> return 0;
> }
>
> -static int mtk_topckgen_set_parent(struct clk *clk, struct clk *parent)
> +static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent)
> {
> struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
>
> @@ -474,19 +477,7 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk)
> struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
> const struct mtk_gate *gate = &priv->gates[clk->id];
>
> - switch (gate->flags & CLK_PARENT_MASK) {
> - case CLK_PARENT_APMIXED:
> - return mtk_clk_find_parent_rate(clk, gate->parent,
> - DM_DRIVER_GET(mtk_clk_apmixedsys));
> - break;
> - case CLK_PARENT_TOPCKGEN:
> - return mtk_clk_find_parent_rate(clk, gate->parent,
> - DM_DRIVER_GET(mtk_clk_topckgen));
> - break;
> -
> - default:
> - return priv->tree->xtal_rate;
> - }
> + return mtk_clk_find_parent_rate(clk, gate->parent, priv->parent);
> }
>
> const struct clk_ops mtk_clk_apmixedsys_ops = {
> @@ -497,10 +488,10 @@ const struct clk_ops mtk_clk_apmixedsys_ops = {
> };
>
> const struct clk_ops mtk_clk_topckgen_ops = {
> - .enable = mtk_topckgen_enable,
> - .disable = mtk_topckgen_disable,
> + .enable = mtk_clk_mux_enable,
> + .disable = mtk_clk_mux_disable,
> .get_rate = mtk_topckgen_get_rate,
> - .set_parent = mtk_topckgen_set_parent,
> + .set_parent = mtk_common_clk_set_parent,
> };
>
> const struct clk_ops mtk_clk_gate_ops = {
> @@ -513,11 +504,22 @@ int mtk_common_clk_init(struct udevice *dev,
> const struct mtk_clk_tree *tree)
> {
> struct mtk_clk_priv *priv = dev_get_priv(dev);
> + struct udevice *parent;
> + int ret;
>
> priv->base = dev_read_addr_ptr(dev);
> if (!priv->base)
> return -ENOENT;
>
> + ret = uclass_get_device_by_phandle(UCLASS_CLK, dev, "clock-parent",
> &parent);
> + if (ret || !parent) {
> + ret = uclass_get_device_by_driver(UCLASS_CLK,
> + DM_DRIVER_GET(mtk_clk_apmixedsys), &parent);
> + if (ret || !parent)
> + return -ENOENT;
> + }
> +
> + priv->parent = parent;
> priv->tree = tree;
>
> return 0;
> @@ -528,11 +530,22 @@ int mtk_common_clk_gate_init(struct udevice *dev,
> const struct mtk_gate *gates)
> {
> struct mtk_cg_priv *priv = dev_get_priv(dev);
> + struct udevice *parent;
> + int ret;
>
> priv->base = dev_read_addr_ptr(dev);
> if (!priv->base)
> return -ENOENT;
>
> + ret = uclass_get_device_by_phandle(UCLASS_CLK, dev, "clock-parent",
> &parent);
Why not just use clk_get?
> + if (ret || !parent) {
> + ret = uclass_get_device_by_driver(UCLASS_CLK,
> + DM_DRIVER_GET(mtk_clk_topckgen), &parent);
> + if (ret || !parent)
> + return -ENOENT;
> + }
> +
> + priv->parent = parent;
> priv->tree = tree;
> priv->gates = gates;
>
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 0ab6912bf0..7955d469db 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -203,11 +203,13 @@ struct mtk_clk_tree {
> };
>
> struct mtk_clk_priv {
> + struct udevice *parent;
> void __iomem *base;
> const struct mtk_clk_tree *tree;
> };
>
> struct mtk_cg_priv {
> + struct udevice *parent;
> void __iomem *base;
> const struct mtk_clk_tree *tree;
> const struct mtk_gate *gates;
>
--Sean
next prev parent reply other threads:[~2022-08-13 4:18 UTC|newest]
Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-04 3:34 [PATCH 00/31] Add support for MediaTek MT7981/MT7986 SoCs Weijie Gao
2022-08-04 3:34 ` [PATCH 01/31] arm: mediatek: add support for MediaTek MT7986 SoC Weijie Gao
2022-08-04 8:37 ` Daniel Golle
2022-08-04 8:50 ` Weijie Gao
2022-08-05 8:43 ` Weijie Gao
2022-08-06 16:09 ` Daniel Golle
2022-08-08 1:37 ` Weijie Gao
2022-08-04 3:34 ` [PATCH 02/31] arm: mediatek: add support for MediaTek MT7981 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 2:17 ` Weijie Gao
2022-08-08 19:26 ` Simon Glass
2022-08-04 3:35 ` [PATCH 03/31] board: mediatek: add MT7986 reference boards Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-09 9:10 ` Daniel Golle
2022-08-12 11:02 ` Weijie Gao
2022-08-12 11:29 ` Daniel Golle
2022-08-04 3:35 ` [PATCH 04/31] board: mediatek: add MT7981 " Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:35 ` [PATCH 05/31] mmc: mediatek: add support for MediaTek MT7891/MT7986 SoCs Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 2:22 ` Weijie Gao
2022-08-11 5:50 ` jh80.chung
2022-08-04 3:35 ` [PATCH 06/31] net: mediatek: use a struct to cover variations of all SoCs Weijie Gao
2022-08-04 13:56 ` Simon Glass
2022-08-08 2:28 ` Weijie Gao
2022-08-04 3:35 ` [PATCH 07/31] net: mediatek: stop using bitfileds for DMA descriptors Weijie Gao
2022-08-04 13:56 ` Simon Glass
2022-08-06 17:50 ` Ramon Fried
2022-08-08 2:29 ` Weijie Gao
2022-08-04 3:35 ` [PATCH 08/31] net: mediatek: add support for PDMA v2 Weijie Gao
2022-08-04 13:56 ` Simon Glass
2022-08-06 17:49 ` Ramon Fried
2022-08-04 3:35 ` [PATCH 09/31] net: mediatek: add support for MediaTek MT7981/MT7986 Weijie Gao
2022-08-06 17:48 ` Ramon Fried
2022-08-04 3:35 ` [PATCH 10/31] serial: mtk: add support for using dynamic baud clock souce Weijie Gao
2022-08-04 13:56 ` Simon Glass
2022-08-08 2:36 ` Weijie Gao
2022-08-08 19:26 ` Simon Glass
2022-08-04 3:35 ` [PATCH 11/31] arm: dts: mt7622: force high-speed mode for uart Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:35 ` [PATCH 12/31] pwm: mtk: add support for MediaTek MT7986 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:35 ` [PATCH 13/31] pwm: mtk: add support for MediaTek MT7981 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:35 ` [PATCH 14/31] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:35 ` [PATCH 15/31] watchdog: mediatek: add support for MediaTek MT7986 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 16/31] spi: add support for MediaTek spi-mem controller Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 17/31] i2c: add support for MediaTek I2C interface Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:00 ` Weijie Gao
2022-08-10 11:12 ` Heiko Schocher
2022-08-10 11:24 ` Michael Nazzareno Trimarchi
2022-08-12 9:46 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 18/31] arm: dts: mt7622: add i2c support Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 19/31] dt-bindings: pinctrl: mediatek: add a header for common pinconf parameters Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 20/31] pinctrl: mediatek: add pinctrl driver for MT7981 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 21/31] pinctrl: mediatek: add pinctrl driver for MT7986 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 22/31] clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:01 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 23/31] clk: mediatek: add support to configure clock driver parent Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-13 4:18 ` Sean Anderson [this message]
2022-08-23 10:43 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 24/31] clk: mediatek: add infrasys clock mux support Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-13 4:21 ` Sean Anderson
2022-08-17 8:00 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:10 ` Weijie Gao
2022-08-13 4:25 ` Sean Anderson
2022-08-17 8:08 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 26/31] clk: mediatek: add clock driver support for MediaTek MT7986 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:13 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 27/31] clk: mediatek: add clock driver support for MediaTek MT7981 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:18 ` Weijie Gao
2022-08-13 4:31 ` Sean Anderson
2022-08-17 8:16 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 28/31] tools: mtk_image: split gfh header verification into a new function Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 29/31] tools: mtk_image: split the code of generating NAND header into a new file Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:23 ` Weijie Gao
2022-08-05 18:26 ` Daniel Golle
2022-08-08 3:26 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 30/31] tools: mtk_image: add support for nand headers used by newer chips Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:31 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 31/31] MAINTAINERS: update maintainer for MediaTek ARM platform Weijie Gao
2022-08-04 13:57 ` Simon Glass
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