* [U-Boot] [PATCH v4 0/8] am335x: NOR support
@ 2013-07-18 19:12 Tom Rini
2013-07-18 19:12 ` [U-Boot] [PATCH v4 1/8] am335x_evm: Drop useless CONFIG_ENV_IS_NOWHERE Tom Rini
` (8 more replies)
0 siblings, 9 replies; 18+ messages in thread
From: Tom Rini @ 2013-07-18 19:12 UTC (permalink / raw)
To: u-boot
Hey all,
This series adds NOR support to am335x_evm, along with a few generic
changes to make gpmc clearer (for per-board things like different NOR
chips, etc). This series depends on the last go-round of the am335x
falcon mode docs as that adds the README that I add more content to.
And while I say this in 3/8, to be clear, I expect to drop 3/8 in favor
of Justin Waters' way of doing this instead, I just include this here for
completeness and will get it all happy together when I assemble things
in u-boot-ti.
The big changes in v4 are:
- Apply again to master which includes a few non-trivial updates, so the
linker script got re-synced.
- After checking what's going on, and testing with NAND again, we can be
common with gpmc_cfg->irqstatus/enable, and only set documented bits
in gpmc_cfg->config
--
Tom
^ permalink raw reply [flat|nested] 18+ messages in thread* [U-Boot] [PATCH v4 1/8] am335x_evm: Drop useless CONFIG_ENV_IS_NOWHERE 2013-07-18 19:12 [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini @ 2013-07-18 19:12 ` Tom Rini 2013-07-18 19:12 ` [U-Boot] [PATCH v4 2/8] am335x_evm: Update SPI_BOOT support, add MTDPARTS info Tom Rini ` (7 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Tom Rini @ 2013-07-18 19:12 UTC (permalink / raw) To: u-boot We always set a CONFIG_ENV_IS_...somewhere... so drop the initial define of NOWHERE. Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com> --- include/configs/am335x_evm.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 0f12c75..ea8669a 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -306,8 +306,6 @@ #define CONFIG_ENV_OVERWRITE 1 #define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_ENV_IS_NOWHERE - /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK @@ -467,7 +465,6 @@ * 0x442000 - 0x800000 : Userland */ #if defined(CONFIG_SPI_BOOT) -# undef CONFIG_ENV_IS_NOWHERE # define CONFIG_ENV_IS_IN_SPI_FLASH # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED # define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ @@ -515,7 +512,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #if !defined(CONFIG_SPI_BOOT) -#undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 2/8] am335x_evm: Update SPI_BOOT support, add MTDPARTS info 2013-07-18 19:12 [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini 2013-07-18 19:12 ` [U-Boot] [PATCH v4 1/8] am335x_evm: Drop useless CONFIG_ENV_IS_NOWHERE Tom Rini @ 2013-07-18 19:12 ` Tom Rini 2013-07-18 19:13 ` [U-Boot] [PATCH v4 3/8] am335x_evm: Only set CONFIG_NAND when !CONFIG_SPI_BOOT Tom Rini ` (6 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Tom Rini @ 2013-07-18 19:12 UTC (permalink / raw) To: u-boot - Style cleanup (# define -> #define) - Due to ROM issues, redudant loading isn't feasible, so drop. - Given extra space, increase max size of U-Boot to 512KiB - Correct env size to match usage (we had not re-defined ENV_SIZE). - Given extra space, keep env size as 128KiB, add redundant environment. Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com> --- Changes in v2: - Correct physmap -> m25p80 in mtdparts (Peter K). - Style fixups, drop redundant SPL space, add redundant environment. --- include/configs/am335x_evm.h | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ea8669a..cc2da92 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -367,7 +367,7 @@ #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SPL_MUSB_NEW_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" @@ -453,22 +453,27 @@ #endif /* - * Default to using SPI for environment, etc. We have multiple copies - * of SPL as the ROM will check these locations. - * 0x0 - 0x20000 : First copy of SPL - * 0x20000 - 0x40000 : Second copy of SPL - * 0x40000 - 0x60000 : Third copy of SPL - * 0x60000 - 0x80000 : Fourth copy of SPL - * 0x80000 - 0xDF000 : U-Boot - * 0xDF000 - 0xE0000 : U-Boot Environment - * 0xE0000 - 0x442000 : Linux Kernel + * Default to using SPI for environment, etc. + * 0x000000 - 0x020000 : SPL (128KiB) + * 0x020000 - 0x0A0000 : U-Boot (512KiB) + * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) + * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) + * 0x0E0000 - 0x442000 : Linux Kernel * 0x442000 - 0x800000 : Userland */ #if defined(CONFIG_SPI_BOOT) -# define CONFIG_ENV_IS_IN_SPI_FLASH -# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ -# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor0=m25p80-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \ + "512k(u-boot),128k(u-boot-env1)," \ + "128k(u-boot-env2),3464k(kernel)," \ + "-(rootfs)" #endif /* SPI support */ /* Unsupported features */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 3/8] am335x_evm: Only set CONFIG_NAND when !CONFIG_SPI_BOOT 2013-07-18 19:12 [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini 2013-07-18 19:12 ` [U-Boot] [PATCH v4 1/8] am335x_evm: Drop useless CONFIG_ENV_IS_NOWHERE Tom Rini 2013-07-18 19:12 ` [U-Boot] [PATCH v4 2/8] am335x_evm: Update SPI_BOOT support, add MTDPARTS info Tom Rini @ 2013-07-18 19:13 ` Tom Rini 2013-07-18 19:13 ` [U-Boot] [PATCH v4 4/8] am335x_evm: Rework board_is_foo() checks Tom Rini ` (5 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Tom Rini @ 2013-07-18 19:13 UTC (permalink / raw) To: u-boot Due to hardware design the board supported by the am335x_evm config cannot have both NAND and SPI (or NOR) enabled at the same time due to conflicts. Disable the NAND SW stack when we know we can't have it present. Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Cc: Justin Waters <justin.waters@timesys.com> Signed-off-by: Tom Rini <trini@ti.com> --- Changes in v4: - Rework location, and note that when merged this should be dropped in favor of Justin Waters' approach in his series Changes in v2: - Reword commit message --- include/configs/am335x_evm.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index cc2da92..c00a97f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -42,6 +42,10 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 +#if !defined(CONFIG_SPI_BOOT) +#define CONFIG_NAND +#endif + /* commands to include */ #include <config_cmd_default.h> @@ -231,7 +235,9 @@ /* USB Device Firmware Update support */ #define CONFIG_DFU_FUNCTION #define CONFIG_DFU_MMC +#ifdef CONFIG_NAND #define CONFIG_DFU_NAND +#endif #define CONFIG_CMD_DFU #define DFU_ALT_INFO_MMC \ "boot part 0 1;" \ @@ -372,11 +378,13 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT +#ifdef CONFIG_NAND #define CONFIG_SPL_NAND_AM33XX_BCH #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC +#endif #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) @@ -497,7 +505,6 @@ #define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC -#define CONFIG_NAND /* NAND support */ #ifdef CONFIG_NAND #define CONFIG_CMD_NAND @@ -516,11 +523,9 @@ /* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#if !defined(CONFIG_SPI_BOOT) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ #endif -#endif #endif /* ! __CONFIG_AM335X_EVM_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 4/8] am335x_evm: Rework board_is_foo() checks 2013-07-18 19:12 [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini ` (2 preceding siblings ...) 2013-07-18 19:13 ` [U-Boot] [PATCH v4 3/8] am335x_evm: Only set CONFIG_NAND when !CONFIG_SPI_BOOT Tom Rini @ 2013-07-18 19:13 ` Tom Rini 2013-07-18 19:13 ` [U-Boot] [PATCH v4 5/8] am33xx: Correct gpmc_cfg->irqstatus/enable Tom Rini ` (4 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Tom Rini @ 2013-07-18 19:13 UTC (permalink / raw) To: u-boot We rework the various board_is_foo() checks to take a pointer to struct am335x_baseboard_id rather than using a local copy in board.c. This allows us to make use of the same checks in mux.c as well as fixing problems when this code could be running from read-only memory. Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com> --- Changes in v2: - Fix checkpatch warnings --- board/ti/am335x/board.c | 80 ++++++++++++++++------------------------------- board/ti/am335x/board.h | 31 ++++++++++++++++++ board/ti/am335x/mux.c | 10 +++--- 3 files changed, 63 insertions(+), 58 deletions(-) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index fdbe26c..a645d30 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -48,43 +48,10 @@ static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -static struct am335x_baseboard_id __attribute__((section (".data"))) header; - -static inline int board_is_bone(void) -{ - return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); -} - -static inline int board_is_bone_lt(void) -{ - return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); -} - -static inline int board_is_evm_sk(void) -{ - return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); -} - -static inline int board_is_idk(void) -{ - return !strncmp(header.config, "SKU#02", 6); -} - -static int __maybe_unused board_is_gp_evm(void) -{ - return !strncmp("A33515BB", header.name, 8); -} - -int board_is_evm_15_or_later(void) -{ - return (!strncmp("A33515BB", header.name, 8) && - strncmp("1.5", header.version, 3) <= 0); -} - /* * Read header information from EEPROM into global structure. */ -static int read_eeprom(void) +static int read_eeprom(struct am335x_baseboard_id *header) { /* Check if baseboard eeprom is available */ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { @@ -94,28 +61,28 @@ static int read_eeprom(void) } /* read the eeprom using i2c */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, - sizeof(header))) { + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, + sizeof(struct am335x_baseboard_id))) { puts("Could not read the EEPROM; something fundamentally" " wrong on the I2C bus.\n"); return -EIO; } - if (header.magic != 0xEE3355AA) { + if (header->magic != 0xEE3355AA) { /* * read the eeprom using i2c again, * but use only a 1 byte address */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, - (uchar *)&header, sizeof(header))) { + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct am335x_baseboard_id))) { puts("Could not read the EEPROM; something " "fundamentally wrong on the I2C bus.\n"); return -EIO; } - if (header.magic != 0xEE3355AA) { + if (header->magic != 0xEE3355AA) { printf("Incorrect magic number (0x%x) in EEPROM\n", - header.magic); + header->magic); return -EINVAL; } } @@ -289,12 +256,14 @@ int spl_start_uboot(void) */ void s_init(void) { +#ifdef CONFIG_SPL_BUILD + struct am335x_baseboard_id header; + /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. */ -#ifdef CONFIG_SPL_BUILD save_omap_boot_params(); #endif @@ -343,11 +312,11 @@ void s_init(void) /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - if (read_eeprom() < 0) + if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); enable_board_pin_mux(&header); - if (board_is_evm_sk()) { + if (board_is_evm_sk(&header)) { /* * EVM SK 1.2A and later use gpio0_7 to enable DDR3. * This is safe enough to do on older revs. @@ -356,15 +325,15 @@ void s_init(void) gpio_direction_output(GPIO_DDR_VTT_EN, 1); } - if (board_is_evm_sk()) + if (board_is_evm_sk(&header)) config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); - else if (board_is_bone_lt()) + else if (board_is_bone_lt(&header)) config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, &ddr3_beagleblack_emif_reg_data, 0); - else if (board_is_evm_15_or_later()) + else if (board_is_evm_15_or_later(&header)) config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); else @@ -378,10 +347,6 @@ void s_init(void) */ int board_init(void) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - if (read_eeprom() < 0) - puts("Could not get board ID.\n"); - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; gpmc_init(); @@ -394,6 +359,10 @@ int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG char safe_string[HDR_NAME_LEN + 1]; + struct am335x_baseboard_id header; + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); /* Now set variables based on the header. */ strncpy(safe_string, (char *)header.name, sizeof(header.name)); @@ -457,6 +426,7 @@ int board_eth_init(bd_t *bis) int rv, n = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; + __maybe_unused struct am335x_baseboard_id header; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); @@ -478,7 +448,11 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_DRIVER_TI_CPSW - if (board_is_bone() || board_is_bone_lt() || board_is_idk()) { + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + if (board_is_bone(&header) || board_is_bone_lt(&header) || + board_is_idk(&header)) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; @@ -507,7 +481,7 @@ int board_eth_init(bd_t *bis) #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 #define AR8051_RGMII_TX_CLK_DLY 0x100 - if (board_is_evm_sk() || board_is_gp_evm()) { + if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { const char *devname; devname = miiphy_get_current_dev(); diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h index 48e112e..36ccaec 100644 --- a/board/ti/am335x/board.h +++ b/board/ti/am335x/board.h @@ -37,6 +37,37 @@ struct am335x_baseboard_id { char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; }; +static inline int board_is_bone(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BONE", HDR_NAME_LEN); +} + +static inline int board_is_bone_lt(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN); +} + +static inline int board_is_evm_sk(struct am335x_baseboard_id *header) +{ + return !strncmp("A335X_SK", header->name, HDR_NAME_LEN); +} + +static inline int board_is_idk(struct am335x_baseboard_id *header) +{ + return !strncmp(header->config, "SKU#02", 6); +} + +static inline int board_is_gp_evm(struct am335x_baseboard_id *header) +{ + return !strncmp("A33515BB", header->name, HDR_NAME_LEN); +} + +static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header) +{ + return (board_is_gp_evm(header) && + strncmp("1.5", header->version, 3) <= 0); +} + /* * We have three pin mux functions that must exist. We must be able to enable * uart0, for initial output and i2c0 to read the main EEPROM. We then have a diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 0283708..2e09d98 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -262,13 +262,13 @@ static unsigned short detect_daughter_board_profile(void) void enable_board_pin_mux(struct am335x_baseboard_id *header) { /* Do board-specific muxes. */ - if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) { + if (board_is_bone(header)) { /* Beaglebone pinmux */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(mmc1_pin_mux); - } else if (!strncmp(header->config, "SKU#01", 6)) { + } else if (board_is_gp_evm(header)) { /* General Purpose EVM */ unsigned short profile = detect_daughter_board_profile(); configure_module_pin_mux(rgmii1_pin_mux); @@ -283,7 +283,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } - } else if (!strncmp(header->config, "SKU#02", 6)) { + } else if (board_is_idk(header)) { /* * Industrial Motor Control (IDK) * note: IDK console is on UART3 by default. @@ -292,13 +292,13 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) */ configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_no_cd_pin_mux); - } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) { + } else if (board_is_evm_sk(header)) { /* Starter Kit EVM */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux_sk_evm); - } else if (!strncmp(header->name, "A335BNLT", HDR_NAME_LEN)) { + } else if (board_is_bone_lt(header)) { /* Beaglebone LT pinmux */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 5/8] am33xx: Correct gpmc_cfg->irqstatus/enable 2013-07-18 19:12 [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini ` (3 preceding siblings ...) 2013-07-18 19:13 ` [U-Boot] [PATCH v4 4/8] am335x_evm: Rework board_is_foo() checks Tom Rini @ 2013-07-18 19:13 ` Tom Rini 2013-07-18 19:13 ` [U-Boot] [PATCH v4 6/8] am335x_evm: Add support for the NOR module on the memory cape Tom Rini ` (3 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Tom Rini @ 2013-07-18 19:13 UTC (permalink / raw) To: u-boot Based on our usage of the GPMC, either with NOR or NAND we do not need to be setting the irqstatus or irqenable bits and should clear them like we have historically. Signed-off-by: Tom Rini <trini@ti.com> --- arch/arm/cpu/armv7/am33xx/mem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index 45f5426..160edd8 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -77,8 +77,8 @@ void gpmc_init(void) /* global settings */ writel(0x00000008, &gpmc_cfg->sysconfig); - writel(0x00000100, &gpmc_cfg->irqstatus); - writel(0x00000100, &gpmc_cfg->irqenable); + writel(0x00000000, &gpmc_cfg->irqstatus); + writel(0x00000000, &gpmc_cfg->irqenable); writel(0x00000012, &gpmc_cfg->config); /* * Disable the GPMC0 config set by ROM code -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 6/8] am335x_evm: Add support for the NOR module on the memory cape 2013-07-18 19:12 [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini ` (4 preceding siblings ...) 2013-07-18 19:13 ` [U-Boot] [PATCH v4 5/8] am33xx: Correct gpmc_cfg->irqstatus/enable Tom Rini @ 2013-07-18 19:13 ` Tom Rini 2013-07-18 19:13 ` [U-Boot] [PATCH v4 7/8] am335x_evm: Add support to boot from NOR Tom Rini ` (2 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Tom Rini @ 2013-07-18 19:13 UTC (permalink / raw) To: u-boot From: Steve Kipisz <s-kipisz2@ti.com> This patch adds support for the NOR module that attaches to the memory cape for a Beaglebone board. This does not add booting support; only support so that you can boot from SD/MMC and see the NOR module so that it can be programmed. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> [trini: Clean up config changes slightly] Signed-off-by: Tom Rini <trini@ti.com> --- Changes in v4: - Split clearing of gpmc_cfg->irqstatus/irqenable into a separate patch Changes in v3: - Reword comment in <asm/arch-am33xx/mem.h> to explain why STNOR values belong in here. Changes in v2: - Move GPMC config portion into board.c Signed-off-by: Tom Rini <trini@ti.com> --- arch/arm/cpu/armv7/am33xx/mem.c | 4 +++ arch/arm/include/asm/arch-am33xx/mem.h | 9 ++++++ board/ti/am335x/board.c | 13 ++++++++ board/ti/am335x/mux.c | 53 ++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/am335x_evm.h | 28 +++++++++++++++++ 6 files changed, 108 insertions(+) diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index 160edd8..ea44f87 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -79,7 +79,11 @@ void gpmc_init(void) writel(0x00000008, &gpmc_cfg->sysconfig); writel(0x00000000, &gpmc_cfg->irqstatus); writel(0x00000000, &gpmc_cfg->irqenable); +#ifdef CONFIG_NOR + writel(0x00000200, &gpmc_cfg->config); +#else writel(0x00000012, &gpmc_cfg->config); +#endif /* * Disable the GPMC0 config set by ROM code */ diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index c3bf74e..9ece266 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -46,6 +46,7 @@ * * Currently valid part Names are (PART): * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL */ #define GPMC_SIZE_256M 0x0 #define GPMC_SIZE_128M 0x8 @@ -61,6 +62,14 @@ #define M_NAND_GPMC_CONFIG6 0x16000f80 #define M_NAND_GPMC_CONFIG7 0x00000008 +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + /* max number of GPMC Chip Selects */ #define GPMC_MAX_CS 8 /* max number of GPMC regs */ diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index a645d30..7bcaa98 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -27,6 +27,7 @@ #include <asm/arch/gpio.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> #include <asm/io.h> #include <asm/emif.h> #include <asm/gpio.h> @@ -347,10 +348,22 @@ void s_init(void) */ int board_init(void) { +#ifdef CONFIG_NOR + const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; +#endif + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; gpmc_init(); +#ifdef CONFIG_NOR + /* Reconfigure CS0 for NOR instead of NAND. */ + enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0], + CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M); +#endif + return 0; } diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 2e09d98..187468e 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -190,6 +190,56 @@ static struct module_pin_mux nand_pin_mux[] = { {-1}, }; +#if defined(CONFIG_NOR) +static struct module_pin_mux bone_norcape_pin_mux[] = { + {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */ + {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */ + {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */ + {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */ + {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */ + {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */ + {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */ + {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */ + {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */ + {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */ + {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */ + {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */ + {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */ + {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */ + {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */ + {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */ + {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */ + {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */ + {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */ + {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */ + {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */ + {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */ + {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */ + {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */ + {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */ + {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */ + {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */ + {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */ + {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */ + {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */ + {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */ + {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */ + {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */ + {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */ + {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */ + {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */ + + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */ + {-1}, +}; +#endif + + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -268,6 +318,9 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(mmc1_pin_mux); +#if defined(CONFIG_NOR) + configure_module_pin_mux(bone_norcape_pin_mux); +#endif } else if (board_is_gp_evm(header)) { /* General Purpose EVM */ unsigned short profile = detect_daughter_board_profile(); diff --git a/boards.cfg b/boards.cfg index 4e556e0..58ed412 100644 --- a/boards.cfg +++ b/boards.cfg @@ -242,6 +242,7 @@ vexpress_ca15_tc2 arm armv7 vexpress armltd vexpress_ca5x2 arm armv7 vexpress armltd vexpress_ca9x4 arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1 +am335x_evm_nor arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NOR am335x_evm_spiboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2 am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index c00a97f..155f5d9 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -528,4 +528,32 @@ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ #endif +/* + * NOR Size = 16 MiB + * Number of Sectors/Blocks = 128 + * Sector Size = 128 KiB + * Word length = 16 bits + * Default layout: + * 0x000000 - 0x07FFFF : U-Boot (512 KiB) + * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB) + * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB) + * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB) + * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) + */ +#if defined(CONFIG_NOR) +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_FLASH +#endif /* NOR support */ + #endif /* ! __CONFIG_AM335X_EVM_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 7/8] am335x_evm: Add support to boot from NOR. 2013-07-18 19:12 [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini ` (5 preceding siblings ...) 2013-07-18 19:13 ` [U-Boot] [PATCH v4 6/8] am335x_evm: Add support for the NOR module on the memory cape Tom Rini @ 2013-07-18 19:13 ` Tom Rini 2013-07-18 19:21 ` Albert ARIBAUD 2013-07-18 19:13 ` [U-Boot] [PATCH v4 8/8] board/ti/am335x/README: Document NOR programming Tom Rini 2013-07-30 13:28 ` [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini 8 siblings, 1 reply; 18+ messages in thread From: Tom Rini @ 2013-07-18 19:13 UTC (permalink / raw) To: u-boot From: Steve Kipisz <s-kipisz2@ti.com> NOR requires that s_init be within the first 4KiB of the image so that we can perform the rest of the required pinmuxing to talk with the rest of NOR that we are found on. When NOR_BOOT is set we save our environment in NOR at 512KiB and a redundant copy at 768KiB. We avoid using SPL for this case and u-boot.bin is written directly to the start of NOR. We enclose the DMM-related parts of arch/arm/cpu/armv7/am33xx/emif4.c with TI81xx checks as at this time U-Boot does not discard unused sections in the main build and this code relies on functions specific to (and only provided in) ti81xx-related code. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Tom Rini <trini@ti.com> --- Changes in v4: - Rebase to current. Note that the asm statements seemingly conflict with the save_omap_boot_params call, but I don't see why. Changes in v3: - Explain TI81xx changes Changes in v2: - Reword commit message slightly --- arch/arm/cpu/armv7/am33xx/board.c | 2 +- arch/arm/cpu/armv7/am33xx/emif4.c | 6 +- board/ti/am335x/Makefile | 2 +- board/ti/am335x/board.c | 33 +++++++++-- board/ti/am335x/mux.c | 6 +- board/ti/am335x/u-boot.lds | 117 +++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/am335x_evm.h | 26 ++++++++- 8 files changed, 182 insertions(+), 11 deletions(-) create mode 100644 board/ti/am335x/u-boot.lds diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index b935a29..3085292 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -150,7 +150,7 @@ int arch_misc_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) void rtc32k_enable(void) { struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index aa84e96..370230b 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -43,9 +43,11 @@ void dram_init_banksize(void) } -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) +#ifdef CONFIG_TI81XX static struct dmm_lisa_map_regs *hw_lisa_map_regs = (struct dmm_lisa_map_regs *)DMM_BASE; +#endif static struct vtp_reg *vtpreg[2] = { (struct vtp_reg *)VTP0_CTRL_ADDR, (struct vtp_reg *)VTP1_CTRL_ADDR}; @@ -53,6 +55,7 @@ static struct vtp_reg *vtpreg[2] = { static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; #endif +#ifdef CONFIG_TI81XX void config_dmm(const struct dmm_lisa_map_regs *regs) { enable_dmm_clocks(); @@ -67,6 +70,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs) writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); } +#endif static void config_vtp(int nr) { diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile index 67a87a1..1795e3e 100644 --- a/board/ti/am335x/Makefile +++ b/board/ti/am335x/Makefile @@ -18,7 +18,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -ifdef CONFIG_SPL_BUILD +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y) COBJS := mux.o endif diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 7bcaa98..81ab04a 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -91,7 +91,7 @@ static int read_eeprom(struct am335x_baseboard_id *header) return 0; } -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) static const struct ddr_data ddr2_data = { .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | (MT47H128M16RT25E_RD_DQS<<20) | @@ -257,10 +257,28 @@ int spl_start_uboot(void) */ void s_init(void) { -#ifdef CONFIG_SPL_BUILD - struct am335x_baseboard_id header; + __maybe_unused struct am335x_baseboard_id header; /* + * The ROM will only have set up sufficient pinmux to allow for the + * first 4KiB NOR to be read, we must finish doing what we know of + * the NOR mux in this space in order to continue. + */ +#ifdef CONFIG_NOR_BOOT + asm("stmfd sp!, {r2 - r4}"); + asm("movw r4, #0x8A4"); + asm("movw r3, #0x44E1"); + asm("orr r4, r4, r3, lsl #16"); + asm("mov r2, #9"); + asm("mov r3, #8"); + asm("gpmc_mux: str r2, [r4], #4"); + asm("subs r3, r3, #1"); + asm("bne gpmc_mux"); + asm("ldmfd sp!, {r2 - r4}"); +#endif + +#ifdef CONFIG_SPL_BUILD + /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. @@ -278,7 +296,7 @@ void s_init(void) while (readl(&wdtimer->wdtwwps) != 0x0) ; -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) /* Setup the PLLs and the clocks for the peripherals */ pll_init(); @@ -306,9 +324,16 @@ void s_init(void) uart_soft_reset(); +#if defined(CONFIG_NOR_BOOT) + /* We want our console now. */ + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; +#else gd = &gdata; preloader_console_init(); +#endif /* Initalize the board header */ enable_i2c0_pin_mux(); diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 187468e..5b7ed63 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -190,7 +190,7 @@ static struct module_pin_mux nand_pin_mux[] = { {-1}, }; -#if defined(CONFIG_NOR) +#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) static struct module_pin_mux bone_norcape_pin_mux[] = { {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */ {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */ @@ -317,8 +317,10 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); +#ifndef CONFIG_NOR configure_module_pin_mux(mmc1_pin_mux); -#if defined(CONFIG_NOR) +#endif +#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) configure_module_pin_mux(bone_norcape_pin_mux); #endif } else if (board_is_gp_evm(header)) { diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds new file mode 100644 index 0000000..a173f62 --- /dev/null +++ b/board/ti/am335x/u-boot.lds @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + board/ti/am335x/libam335x.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/boards.cfg b/boards.cfg index 58ed412..1d72319 100644 --- a/boards.cfg +++ b/boards.cfg @@ -243,6 +243,7 @@ vexpress_ca5x2 arm armv7 vexpress armltd vexpress_ca9x4 arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1 am335x_evm_nor arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NOR +am335x_evm_norboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT am335x_evm_spiboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2 am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 155f5d9..2a74a56 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -40,9 +40,12 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +/* Custom script for NOR */ +#define CONFIG_SYS_LDSCRIPT "board/ti/am335x/u-boot.lds" + #define CONFIG_SYS_CACHELINE_SIZE 64 -#if !defined(CONFIG_SPI_BOOT) +#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) #define CONFIG_NAND #endif @@ -312,6 +315,7 @@ #define CONFIG_ENV_OVERWRITE 1 #define CONFIG_SYS_CONSOLE_INFO_QUIET +#ifndef CONFIG_NOR_BOOT /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK @@ -385,6 +389,7 @@ #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #endif +#endif #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) @@ -413,14 +418,18 @@ * header. That is 0x800FFFC0--0x80100000 should not be used for any * other needs. */ +#ifdef CONFIG_NOR_BOOT +#define CONFIG_SYS_TEXT_BASE 0x08000000 +#else #define CONFIG_SYS_TEXT_BASE 0x80800000 +#endif #define CONFIG_SYS_SPL_MALLOC_START 0x80a08000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) #define CONFIG_SKIP_LOWLEVEL_INIT #endif @@ -552,6 +561,19 @@ #define CONFIG_SYS_FLASH_BASE (0x08000000) #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#ifdef CONFIG_NOR_BOOT +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */ +#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */ +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ + "512k(u-boot)," \ + "128k(u-boot-env1)," \ + "128k(u-boot-env2)," \ + "4m(kernel),-(rootfs)" +#endif #define CONFIG_MTD_DEVICE #define CONFIG_CMD_FLASH #endif /* NOR support */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 7/8] am335x_evm: Add support to boot from NOR. 2013-07-18 19:13 ` [U-Boot] [PATCH v4 7/8] am335x_evm: Add support to boot from NOR Tom Rini @ 2013-07-18 19:21 ` Albert ARIBAUD 2013-07-18 19:47 ` Tom Rini 0 siblings, 1 reply; 18+ messages in thread From: Albert ARIBAUD @ 2013-07-18 19:21 UTC (permalink / raw) To: u-boot Hi Tom, On Thu, 18 Jul 2013 15:13:04 -0400, Tom Rini <trini@ti.com> wrote: > Changes in v4: > - Rebase to current. Note that the asm statements seemingly conflict > with the save_omap_boot_params call, but I don't see why. How exactly does the conflict manifest itself? Amicalement, -- Albert. ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 7/8] am335x_evm: Add support to boot from NOR. 2013-07-18 19:21 ` Albert ARIBAUD @ 2013-07-18 19:47 ` Tom Rini 0 siblings, 0 replies; 18+ messages in thread From: Tom Rini @ 2013-07-18 19:47 UTC (permalink / raw) To: u-boot On Thu, Jul 18, 2013 at 09:21:33PM +0200, Albert ARIBAUD wrote: > Hi Tom, > > On Thu, 18 Jul 2013 15:13:04 -0400, Tom Rini <trini@ti.com> wrote: > > > Changes in v4: > > - Rebase to current. Note that the asm statements seemingly conflict > > with the save_omap_boot_params call, but I don't see why. > > How exactly does the conflict manifest itself? What I end up seeing (and I didn't get a debugger attached) was that the i2c init fails (one of the i2c error messages is sent out), so i2c probe fails so we can't init the hardware. And it's left in such a bizarro state that trying to boot again via UART instead for example still fails that way, a power cycle is required to clear things out. -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20130718/cbade3a9/attachment.pgp> ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 8/8] board/ti/am335x/README: Document NOR programming 2013-07-18 19:12 [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini ` (6 preceding siblings ...) 2013-07-18 19:13 ` [U-Boot] [PATCH v4 7/8] am335x_evm: Add support to boot from NOR Tom Rini @ 2013-07-18 19:13 ` Tom Rini 2013-07-30 13:28 ` [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini 8 siblings, 0 replies; 18+ messages in thread From: Tom Rini @ 2013-07-18 19:13 UTC (permalink / raw) To: u-boot The Beaglebone White may be populated with a memory cape that has a NOR module. Document how to program it. Signed-off-by: Tom Rini <trini@ti.com> --- board/ti/am335x/README | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/board/ti/am335x/README b/board/ti/am335x/README index 6d45352..67b5246 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -38,6 +38,29 @@ U-Boot # nand write 81000000 0 260000 U-Boot # load mmc 0 ${loadaddr} uImage U-Boot # nand write ${loadaddr} kernel 500000 +NOR +=== + +The Beaglebone White can be equiped with a "memory cape" that in turn can +have a NOR module plugged into it. In this case it is then possible to +program and boot from NOR. Note that due to how U-Boot is architectured we +must build a specific version of U-Boot that knows we have NOR flash. This +build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot' +build that will assume that the environment is on NOR rather than NAND. In +the following example we assume that and SD card has been populated with +MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the +'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a +binary must be written to the start of NOR, with no header or similar +prepended. In the following example we use a size of 512KiB (0x80000) +as that is how much space we set aside before the environment, as per +the config file. + +U-Boot # mmc rescan +U-Boot # load mmc 0 ${loadaddr} u-boot.bin +U-Boot # protect off 08000000 +80000 +U-Boot # erase 08000000 +80000 +U-Boot # cp.b ${loadaddr} 08000000 ${filesize} + Falcon Mode =========== -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 0/8] am335x: NOR support 2013-07-18 19:12 [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini ` (7 preceding siblings ...) 2013-07-18 19:13 ` [U-Boot] [PATCH v4 8/8] board/ti/am335x/README: Document NOR programming Tom Rini @ 2013-07-30 13:28 ` Tom Rini 2013-08-13 14:57 ` Mark Jackson 8 siblings, 1 reply; 18+ messages in thread From: Tom Rini @ 2013-07-30 13:28 UTC (permalink / raw) To: u-boot On Thu, Jul 18, 2013 at 03:12:57PM -0400, Tom Rini wrote: > Hey all, > > This series adds NOR support to am335x_evm, along with a few generic > changes to make gpmc clearer (for per-board things like different NOR > chips, etc). This series depends on the last go-round of the am335x > falcon mode docs as that adds the README that I add more content to. > And while I say this in 3/8, to be clear, I expect to drop 3/8 in favor > of Justin Waters' way of doing this instead, I just include this here for > completeness and will get it all happy together when I assemble things > in u-boot-ti. > > The big changes in v4 are: > - Apply again to master which includes a few non-trivial updates, so the > linker script got re-synced. > - After checking what's going on, and testing with NAND again, we can be > common with gpmc_cfg->irqstatus/enable, and only set documented bits > in gpmc_cfg->config Applied to u-boot-ti/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20130730/992f69de/attachment.pgp> ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 0/8] am335x: NOR support 2013-07-30 13:28 ` [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini @ 2013-08-13 14:57 ` Mark Jackson 2013-08-13 15:00 ` Tom Rini 0 siblings, 1 reply; 18+ messages in thread From: Mark Jackson @ 2013-08-13 14:57 UTC (permalink / raw) To: u-boot On 30/07/13 14:28, Tom Rini wrote: > On Thu, Jul 18, 2013 at 03:12:57PM -0400, Tom Rini wrote: > >> Hey all, >> >> This series adds NOR support to am335x_evm, along with a few generic >> changes to make gpmc clearer (for per-board things like different NOR >> chips, etc). This series depends on the last go-round of the am335x >> falcon mode docs as that adds the README that I add more content to. >> And while I say this in 3/8, to be clear, I expect to drop 3/8 in favor >> of Justin Waters' way of doing this instead, I just include this here for >> completeness and will get it all happy together when I assemble things >> in u-boot-ti. >> >> The big changes in v4 are: >> - Apply again to master which includes a few non-trivial updates, so the >> linker script got re-synced. >> - After checking what's going on, and testing with NAND again, we can be >> common with gpmc_cfg->irqstatus/enable, and only set documented bits >> in gpmc_cfg->config > > Applied to u-boot-ti/master, thanks! I'm now rebasing our NanoBone code onto the TI uboot code, but I'm coming up with the original issue [1] of having to not check for the R_ARM_RELATIVE relocations again. If I patch config.mk again, the code all compiles. I've tested "make am335x_evm_norboot" and that works. I've attached my custom patchset ... can you tell me what I'm doing wrong ? [1] http://lists.denx.de/pipermail/u-boot/2013-July/158592.html Cheers Mark J. --- board/newflow/nanobone/Makefile | 38 +++++ board/newflow/nanobone/board.c | 295 +++++++++++++++++++++++++++++++++++ board/newflow/nanobone/mux.c | 195 +++++++++++++++++++++++ board/newflow/nanobone/u-boot.lds | 110 +++++++++++++ boards.cfg | 2 + include/configs/nanobone.h | 308 +++++++++++++++++++++++++++++++++++++ 6 files changed, 948 insertions(+) create mode 100644 board/newflow/nanobone/Makefile create mode 100644 board/newflow/nanobone/board.c create mode 100644 board/newflow/nanobone/mux.c create mode 100644 board/newflow/nanobone/u-boot.lds create mode 100644 include/configs/nanobone.h diff --git a/board/newflow/nanobone/Makefile b/board/newflow/nanobone/Makefile new file mode 100644 index 0000000..3dbeeda --- /dev/null +++ b/board/newflow/nanobone/Makefile @@ -0,0 +1,38 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y) +COBJS := mux.o +endif + +COBJS += board.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/newflow/nanobone/board.c b/board/newflow/nanobone/board.c new file mode 100644 index 0000000..6ccda1b --- /dev/null +++ b/board/newflow/nanobone/board.c @@ -0,0 +1,295 @@ +/* + * board.c + * + * Board functions for Newflow NanoBone board + * + * Copyright (C) 2013, Newflow Ltd - http://www.newflow.co.uk/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* NOR Flash config */ +#define NOR_CS 0 +#define NOR_BASE 0x08000000 +#define NOR_SIZE GPMC_SIZE_128M +static u32 gpmc_nor_config[GPMC_MAX_REG] = { + 0x00001200, + 0x00101000, + 0x00030301, + 0x10041004, + 0x010f1010, + 0x08070280, + 0 +}; + +/* FRAM config */ +#define FRAM_CS 1 +#define FRAM_BASE 0x1c000000 +#define FRAM_SIZE GPMC_SIZE_16M +static u32 gpmc_fram_config[GPMC_MAX_REG] = { + 0x00001200, + 0x00101000, + 0x00020201, + 0x0f030f03, + 0x010d1010, + 0x000301c0, + 0 +}; + +static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; +#if defined(CONFIG_SPL_BUILD) || (CONFIG_NOR_BOOT) +//static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; +#endif + +/* MII mode defines */ +#define PORT1_MII_MODE_ENABLE 0x0 +#define PORT2_MII_MODE_ENABLE 0x0 + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41J128MJT125_RD_DQS, + .datawdsratio0 = MT41J128MJT125_WR_DQS, + .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, + .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41J128MJT125_RATIO, + .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, + + .cmd1csratio = MT41J128MJT125_RATIO, + .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, + + .cmd2csratio = MT41J128MJT125_RATIO, + .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41J128MJT125_EMIF_SDCFG, + .ref_ctrl = MT41J128MJT125_EMIF_SDREF, + .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, + .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, + .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, + .zq_config = MT41J128MJT125_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +#endif /* CONFIG_SPL_BUILD */ + +/* + * early system init of muxing and clocks. + */ +void s_init(void) +{ + /* + * The ROM will only have set up sufficient pinmux to allow for the + * first 4KiB NOR to be read, we must finish doing what we know of + * the NOR mux in this space in order to continue. + */ +#ifdef CONFIG_NOR_BOOT + asm("stmfd sp!, {r2 - r4}"); + asm("movw r4, #0x8A4"); + asm("movw r3, #0x44E1"); + asm("orr r4, r4, r3, lsl #16"); + asm("mov r2, #9"); + asm("mov r3, #8"); + asm("gpmc_mux: str r2, [r4], #4"); + asm("subs r3, r3, #1"); + asm("bne gpmc_mux"); + asm("ldmfd sp!, {r2 - r4}"); +#endif + + /* + * Save the boot parameters passed from romcode. + * We cannot delay the saving further than this, + * to prevent overwrites. + */ +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + save_omap_boot_params(); +#endif + + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + /* Setup the PLLs and the clocks for the peripherals */ + pll_init(); + + /* Enable RTC32K clock */ + rtc32k_enable(); + + enable_board_pin_mux(); + + uart_soft_reset(); + +#if defined(CONFIG_NOR_BOOT) + /* We want our console now. */ + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; +#else + gd = &gdata; + + preloader_console_init(); +#endif + + config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif /* CONFIG_SPL_BUILD */ +} + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + //i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + + gpmc_init(); + + /* enable NOR flash chip select */ + enable_gpmc_cs_config(gpmc_nor_config, &gpmc_cfg->cs[NOR_CS], + NOR_BASE, NOR_SIZE); + /* enable FRAM chip select */ + enable_gpmc_cs_config(gpmc_fram_config, &gpmc_cfg->cs[FRAM_CS], + FRAM_BASE, FRAM_SIZE); + + return 0; +} + +int board_late_init(void) +{ + setenv("board_name", "nanobone"); + setenv("board_rev", "0002"); + + return 0; +} + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xff; + mac_addr[1] = (mac_hi & 0xff00) >> 8; + mac_addr[2] = (mac_hi & 0xff0000) >> 16; + mac_addr[3] = (mac_hi & 0xff000000) >> 24; + mac_addr[4] = mac_lo & 0xff; + mac_addr[5] = (mac_lo & 0xff00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + if (!getenv("eth1addr")) { + printf("<eth1addr> not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xff; + mac_addr[1] = (mac_hi & 0xff00) >> 8; + mac_addr[2] = (mac_hi & 0xff0000) >> 16; + mac_addr[3] = (mac_hi & 0xff000000) >> 24; + mac_addr[4] = mac_lo & 0xff; + mac_addr[5] = (mac_lo & 0xff00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + writel(PORT1_MII_MODE_ENABLE | PORT2_MII_MODE_ENABLE, &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + + return n; +} diff --git a/board/newflow/nanobone/mux.c b/board/newflow/nanobone/mux.c new file mode 100644 index 0000000..110a4a2 --- /dev/null +++ b/board/newflow/nanobone/mux.c @@ -0,0 +1,195 @@ +/* + * mux.c + * + * Copyright (C) 2013, Newflow Ltd - http://www.newflow.co.uk/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include "board.h" + +static struct module_pin_mux gpmc_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD7 */ + {OFFSET(gpmc_ad8), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD15 */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* GPMC_CSN0 */ + {OFFSET(gpmc_csn1), (MODE(0) | PULLUDEN)}, /* GPMC_CSN1 */ + {OFFSET(gpmc_csn2), (MODE(0) | PULLUDEN)}, /* GPMC_CSN2 */ + {OFFSET(gpmc_csn3), (MODE(0) | PULLUDEN)}, /* GPMC_CSN3 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* GPMC_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* GPMC_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* GPMC_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* GPMC_BE_CLE */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE)}, /* NAND WAIT */ + {OFFSET(lcd_data1), (MODE(1) | PULLUDDIS)}, /* GPMC A17 */ + {OFFSET(lcd_data2), (MODE(1) | PULLUDDIS)}, /* GPMC A18 */ + {OFFSET(lcd_data3), (MODE(1) | PULLUDDIS)}, /* GPMC A19 */ + {OFFSET(lcd_data4), (MODE(1) | PULLUDDIS)}, /* GPMC A20 */ + {OFFSET(lcd_data5), (MODE(1) | PULLUDDIS)}, /* GPMC A21 */ + {OFFSET(lcd_data6), (MODE(1) | PULLUDDIS)}, /* GPMC A22 */ + {OFFSET(lcd_data7), (MODE(1) | PULLUDDIS)}, /* GPMC A23 */ + {OFFSET(lcd_vsync), (MODE(1) | PULLUDDIS)}, /* GPMC A24 */ + {OFFSET(lcd_hsync), (MODE(1) | PULLUDDIS)}, /* GPMC A25 */ + {OFFSET(lcd_pclk), (MODE(1) | PULLUDDIS)}, /* GPMC A26 */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */ + {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */ + {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */ + {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */ + {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */ + {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */ + {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */ + {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */ + {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */ + {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */ + {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ + {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ + {OFFSET(gpmc_wpn), MODE(1) | RXACTIVE}, /* MII2_RXERR */ + {OFFSET(gpmc_be1n), MODE(1) | RXACTIVE}, /* MII2_COL */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mmc0_no_cd_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(emu1), (MODE(7) | RXACTIVE)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_CTSN */ + {OFFSET(uart1_rtsn), (MODE(7) | PULLUDEN | RXACTIVE)}, /* UART1_RTSN */ + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(lcd_data8), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART2_CTSN */ + {OFFSET(lcd_data9), (MODE(7) | PULLUDEN | RXACTIVE)}, /* UART2_RTSN */ + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(lcd_data10), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART3_CTSN */ + {OFFSET(lcd_data11), (MODE(6) | PULLUDEN)}, /* UART3_RTSN */ + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(lcd_data12), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_CTSN */ + {OFFSET(lcd_data13), (MODE(6) | PULLUDEN)}, /* UART4_RTSN */ + {OFFSET(uart0_ctsn), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(uart0_rtsn), (MODE(1) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data14), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(rmii1_refclk), (MODE(3) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + +static struct module_pin_mux usb0_pin_mux[] = { + {OFFSET(usb0_dm), (MODE(0) | RXACTIVE)}, /* USB0_DM */ + {OFFSET(usb0_dp), (MODE(0) | RXACTIVE)}, /* USB0_DP */ + {OFFSET(usb0_ce), (MODE(0) | RXACTIVE)}, /* USB0_CE */ + {OFFSET(usb0_id), (MODE(0) | RXACTIVE)}, /* USB0_ID */ + {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE)}, /* USB0_VBUS */ + {OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)}, /* USB0_DRVVBUS */ + {-1}, +}; + +static struct module_pin_mux usb1_pin_mux[] = { + {OFFSET(usb1_dm), (MODE(0) | RXACTIVE)}, /* USB1_DM */ + {OFFSET(usb1_dp), (MODE(0) | RXACTIVE)}, /* USB1_DP */ + {OFFSET(usb1_ce), (MODE(0) | RXACTIVE)}, /* USB1_CE */ + {OFFSET(usb1_id), (MODE(0) | RXACTIVE)}, /* USB1_ID */ + {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE)}, /* USB1_VBUS */ + {OFFSET(usb1_drvvbus), (MODE(0) | PULLUDEN)}, /* USB1_DRVVBUS */ + {-1}, +}; + +void enable_board_pin_mux() +{ + configure_module_pin_mux(gpmc_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mii2_pin_mux); + configure_module_pin_mux(mmc0_no_cd_pin_mux); + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(uart1_pin_mux); + configure_module_pin_mux(uart2_pin_mux); + configure_module_pin_mux(uart3_pin_mux); + configure_module_pin_mux(uart4_pin_mux); + configure_module_pin_mux(uart5_pin_mux); + configure_module_pin_mux(usb0_pin_mux); + configure_module_pin_mux(usb1_pin_mux); +} diff --git a/board/newflow/nanobone/u-boot.lds b/board/newflow/nanobone/u-boot.lds new file mode 100644 index 0000000..b051b57 --- /dev/null +++ b/board/newflow/nanobone/u-boot.lds @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __image_copy_start = .; + CPUDIR/start.o (.text*) + board/newflow/nanobone/libnanobone.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + _end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/boards.cfg b/boards.cfg index 211ed58..1e5ca5d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -252,6 +252,8 @@ am335x_evm_uart4 arm armv7 am335x ti am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=1,NAND am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT am335x_boneblack arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT +nanobone arm armv7 nanobone newflow am33xx nanobone:NOR_BOOT +nanobone_sdboot arm armv7 nanobone newflow am33xx nanobone:SD_BOOT ti814x_evm arm armv7 ti814x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC diff --git a/include/configs/nanobone.h b/include/configs/nanobone.h new file mode 100644 index 0000000..f5da640 --- /dev/null +++ b/include/configs/nanobone.h @@ -0,0 +1,308 @@ +/* + * nanobone.h + * + * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_NANOBONE_H +#define __CONFIG_NANOBONE_H + +#define CONFIG_AM33XX +#define CONFIG_OMAP + +#include <asm/arch/omap.h> + +#define CONFIG_DMA_COHERENT +#define CONFIG_DMA_COHERENT_SIZE (1 << 20) + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_BOARD_LATE_INIT +#define MACH_TYPE_NANOBONE 4483 +#define CONFIG_MACH_TYPE MACH_TYPE_NANOBONE + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024) +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* Custom script for NOR */ +#define CONFIG_SYS_LDSCRIPT "board/newflow/nanobone/u-boot.lds" + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_VERSION_VARIABLE + +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 0 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#ifndef CONFIG_SPL_BUILD + +#ifdef CONFIG_SD_BOOT + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "mmcdev=0\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mtdparts default;" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "fi;" \ + +#endif /* CONFIG_SD_BOOT */ + +#ifdef CONFIG_NOR_BOOT + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80f80000\0" \ + "fdt_high=0xffffffff\0" \ + "kerneladdr=0x08100000\0" + +#define CONFIG_BOOTARGS \ + "console=ttyO0,115200n8 noinitrd ip=off mem=256M " \ + "rootwait=1 rootfstype=ubifs ubi.mtd=4,64 root=ubi0:rootfs rw " \ + "quiet" + +#define CONFIG_BOOTCOMMAND \ + "mtdparts default;" \ + "bootm ${kerneladdr}" + +#endif /* CONFIG_NOR_BOOT */ + +#endif /* CONFIG_SPL_BUILD */ + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_CMD_ECHO + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#undef CONFIG_CMD_MEMTEST + +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ + +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 + + /* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + /* Platform/Board specific defs */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_CONS_INDEX 1 + +/* I2C Configuration */ +#define CONFIG_I2C +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_DRIVER_OMAP24XX_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +#define CONFIG_OMAP_GPIO + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* CPU */ +#define CONFIG_ARCH_CPU_INIT + +#ifdef CONFIG_SD_BOOT +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +/* + * Place the image at the start of the ROM defined image space. + * We limit our size to the ROM-defined downloaded image area, and use the + * rest of the space for stack. + */ +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" +#define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT +#endif /* CONFIG_SD_BOOT */ + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#ifdef CONFIG_NOR_BOOT +#define CONFIG_SYS_TEXT_BASE 0x08000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#endif +#define CONFIG_SYS_SPL_MALLOC_START 0x80a08000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif /* CONFIG_SPL_BUILD */ + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY_SMSC + +/* UBIFS support */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* NOR support + * + * NOR Size = 128 MiB + * Number of Sectors/Blocks = 1024 + * Sector Size = 128 KiB + * Word length = 16 bits + * Default layout: + * 0x00000000 - 0x000BFFFF : U-Boot (768 KiB) + * 0x000C0000 - 0x000DFFFF : First copy of U-Boot Environment (128 KiB) + * 0x000E0000 - 0x000FFFFF : Second copy of U-Boot Environment (128 KiB) + * 0x00100000 - 0x004FFFFF : Linux Kernel (4 MiB) + * 0x00500000 - 0x03FFFFFF : Root FS (59 MiB) + * 0x04000000 - 0x07FFFFFF : Data (64 MiB) + */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_FLASH +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor0=nor" +#define MTDPARTS_DEFAULT "mtdparts=nor:" \ + "768k(u-boot)," \ + "128k(u-boot-env1)," \ + "128k(u-boot-env2)," \ + "4m(kernel)," \ + "16m(rootfs)," \ + "43m(user)," \ + "64m(data)" +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB */ +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB */ + +#endif /* ! __CONFIG_NANOBONE_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 0/8] am335x: NOR support 2013-08-13 14:57 ` Mark Jackson @ 2013-08-13 15:00 ` Tom Rini 2013-08-13 15:06 ` Mark Jackson 0 siblings, 1 reply; 18+ messages in thread From: Tom Rini @ 2013-08-13 15:00 UTC (permalink / raw) To: u-boot -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 08/13/2013 10:57 AM, Mark Jackson wrote: > On 30/07/13 14:28, Tom Rini wrote: >> On Thu, Jul 18, 2013 at 03:12:57PM -0400, Tom Rini wrote: >> >>> Hey all, >>> >>> This series adds NOR support to am335x_evm, along with a few >>> generic changes to make gpmc clearer (for per-board things like >>> different NOR chips, etc). This series depends on the last >>> go-round of the am335x falcon mode docs as that adds the README >>> that I add more content to. And while I say this in 3/8, to be >>> clear, I expect to drop 3/8 in favor of Justin Waters' way of >>> doing this instead, I just include this here for completeness >>> and will get it all happy together when I assemble things in >>> u-boot-ti. >>> >>> The big changes in v4 are: - Apply again to master which >>> includes a few non-trivial updates, so the linker script got >>> re-synced. - After checking what's going on, and testing with >>> NAND again, we can be common with gpmc_cfg->irqstatus/enable, >>> and only set documented bits in gpmc_cfg->config >> >> Applied to u-boot-ti/master, thanks! > > I'm now rebasing our NanoBone code onto the TI uboot code, but I'm > coming up with the original issue [1] of having to not check for > the R_ARM_RELATIVE relocations again. Your linker script is out of sync with arch/arm/cpu/u-boot.lds - -- Tom -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJSCkoKAAoJENk4IS6UOR1WS5IP/0is6vnCBc3NtLRkOxCbIwjK oFsx7qzJ/xg+D+56ygI14JVH7zikGk2b70bh05wLog96D/oIk8lFgLj3h3YJSG99 cGlAB3ZxI7VupgILfN0lnJ0Ht6NNqou6p3qfC2lJl6/kl40mVXsPBV93X8b/N2vx eDvP6bE8cjhvtQLlOb6HnDcp5OAkbXqiexM3vfwsVALisCksK67DpFgnrm37w9T6 LVAIMRBAOmf6UHDAEbK0I2FjUb/zG/bO3dsTVl+04H5jeOeVerscQPPYtSLY2vua KaJDOXutw2CnUX4xNh3OWj/bSFz39qt5GnGJ8roNfwClbTjEtt0/7zGuGSPh7qXd CCIGHktpYtvAj2HmQ7U4aSqnF4o/gZDJlZZmNArrvDVn2/5XmdxrUO9tSdiRYMBR ljPLK+VBD7vz96mbfx3QWbL0dBnjzg0jxaOpvEX/N7SomZnb7seu9lTetaDVRJhD xj96lSaZ2BL7SGAW/1h1mt93Bh/emQDhpLI1wNIr0UCRWmdx34enQnBN51A8Al0j E132z4n1zQfj7fAG9nLdAVuuBJsDX5iyHFz3NUuxvREls+yLK5bweXUOwfhUirMd eJqlPaKiAuuoUwsPJHWCr/PS0+pU0AdxZ9dP9s9sGU1Lr+lJNUkqP0KVnb4aZqtA nmrkfKCX6p+R1C/RluK0 =LnpG -----END PGP SIGNATURE----- ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 0/8] am335x: NOR support 2013-08-13 15:00 ` Tom Rini @ 2013-08-13 15:06 ` Mark Jackson 2013-08-13 15:11 ` Tom Rini 0 siblings, 1 reply; 18+ messages in thread From: Mark Jackson @ 2013-08-13 15:06 UTC (permalink / raw) To: u-boot On 13/08/13 16:00, Tom Rini wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > On 08/13/2013 10:57 AM, Mark Jackson wrote: >> On 30/07/13 14:28, Tom Rini wrote: >>> On Thu, Jul 18, 2013 at 03:12:57PM -0400, Tom Rini wrote: >>> >>>> Hey all, >>>> >>>> This series adds NOR support to am335x_evm, along with a few >>>> generic changes to make gpmc clearer (for per-board things like >>>> different NOR chips, etc). This series depends on the last >>>> go-round of the am335x falcon mode docs as that adds the README >>>> that I add more content to. And while I say this in 3/8, to be >>>> clear, I expect to drop 3/8 in favor of Justin Waters' way of >>>> doing this instead, I just include this here for completeness >>>> and will get it all happy together when I assemble things in >>>> u-boot-ti. >>>> >>>> The big changes in v4 are: - Apply again to master which >>>> includes a few non-trivial updates, so the linker script got >>>> re-synced. - After checking what's going on, and testing with >>>> NAND again, we can be common with gpmc_cfg->irqstatus/enable, >>>> and only set documented bits in gpmc_cfg->config >>> >>> Applied to u-boot-ti/master, thanks! >> >> I'm now rebasing our NanoBone code onto the TI uboot code, but I'm >> coming up with the original issue [1] of having to not check for >> the R_ARM_RELATIVE relocations again. > > Your linker script is out of sync with arch/arm/cpu/u-boot.lds Strange ... since the am335x nor_boot compile appeared to work fine, I just copied the script from board/ti/am335x, and assumed it would work fine for me (with a library path change). So does this TI file also need updating ? Either way, my code now compiles. Cheers. ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 0/8] am335x: NOR support 2013-08-13 15:06 ` Mark Jackson @ 2013-08-13 15:11 ` Tom Rini 2013-08-13 15:20 ` Mark Jackson 0 siblings, 1 reply; 18+ messages in thread From: Tom Rini @ 2013-08-13 15:11 UTC (permalink / raw) To: u-boot -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 08/13/2013 11:06 AM, Mark Jackson wrote: > On 13/08/13 16:00, Tom Rini wrote: >> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 >> >> On 08/13/2013 10:57 AM, Mark Jackson wrote: >>> On 30/07/13 14:28, Tom Rini wrote: >>>> On Thu, Jul 18, 2013 at 03:12:57PM -0400, Tom Rini wrote: >>>> >>>>> Hey all, >>>>> >>>>> This series adds NOR support to am335x_evm, along with a >>>>> few generic changes to make gpmc clearer (for per-board >>>>> things like different NOR chips, etc). This series >>>>> depends on the last go-round of the am335x falcon mode docs >>>>> as that adds the README that I add more content to. And >>>>> while I say this in 3/8, to be clear, I expect to drop 3/8 >>>>> in favor of Justin Waters' way of doing this instead, I >>>>> just include this here for completeness and will get it all >>>>> happy together when I assemble things in u-boot-ti. >>>>> >>>>> The big changes in v4 are: - Apply again to master which >>>>> includes a few non-trivial updates, so the linker script >>>>> got re-synced. - After checking what's going on, and >>>>> testing with NAND again, we can be common with >>>>> gpmc_cfg->irqstatus/enable, and only set documented bits >>>>> in gpmc_cfg->config >>>> >>>> Applied to u-boot-ti/master, thanks! >>> >>> I'm now rebasing our NanoBone code onto the TI uboot code, but >>> I'm coming up with the original issue [1] of having to not >>> check for the R_ARM_RELATIVE relocations again. >> >> Your linker script is out of sync with arch/arm/cpu/u-boot.lds > > Strange ... since the am335x nor_boot compile appeared to work > fine, I just copied the script from board/ti/am335x, and assumed > it would work fine for me (with a library path change). > > So does this TI file also need updating ? > > Either way, my code now compiles. I had to re-sync the TI one in this series as well. Double check between what you have working now vs before, there's a few small changes there... - -- Tom -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJSCkyQAAoJENk4IS6UOR1WmrUP+wXcDGmf/sWOqB99kvxrMrYz 25rbCBYj1I65ataC9gIqXmPnKOeXLwjWOOIK5Z8fYol6Xzf7gz9E4EiuRQPxs3SO NfgEPueEBZVl52/BjzgicO7X6HPlbizuL7sp+yQbMmfsEAklnVmyGR2vOoG2A8CN 07rHmhej9QwYpVyYpAOfU/u3ZGn55PI9GxJiqVXMTRqb/WSEyv7ie0dRivSSHW4y g3WSemNBNYpvHYbYPDjJ68cDSBXiNlXX6uftQdlXD2wxhP5jP3MXUOcvhlFxXbvZ YFBjN7xAI0XeoK3OQk65z+oq/0JGq8FNk5wIKSWKjP06y4ncp1Xb5adGfoiVJ2HI FGqXRLRjHrQoON8f+90EV+a2YXiQ14/G387tJXSLWVSOzdRuaWbPMyzrOw6CT8qS BhOAsxhLCYyu+So+z9+tO1ZB+Wt8XWI1PS3DsRhw7mx9pGUjtLCjN6Ys10r71DyW 5M6rBaDu5eG3Th6X7ifoUwVJUEygh9YUHnWzAEcMtd1aYcFHsngwM7K3vtaAYv/Y PUlbay0Ars8B2JC2rJPKh5PS+BHpEsItHehdkmptKJCwC2NqR987Mv+IT19PFxJz 6Uf8Jc3tQCmfA5DG0HDVBsWon69EbRTTykpgUqCeKPohp2Ms65nKFnYSV/iDCU7U fuVnxnKZSkkuAtX1CkEl =hthS -----END PGP SIGNATURE----- ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 0/8] am335x: NOR support 2013-08-13 15:11 ` Tom Rini @ 2013-08-13 15:20 ` Mark Jackson 2013-08-13 15:45 ` Mark Jackson 0 siblings, 1 reply; 18+ messages in thread From: Mark Jackson @ 2013-08-13 15:20 UTC (permalink / raw) To: u-boot On 13/08/13 16:11, Tom Rini wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > On 08/13/2013 11:06 AM, Mark Jackson wrote: >> On 13/08/13 16:00, Tom Rini wrote: >>> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 >>> >>> On 08/13/2013 10:57 AM, Mark Jackson wrote: >>>> On 30/07/13 14:28, Tom Rini wrote: >>>>> On Thu, Jul 18, 2013 at 03:12:57PM -0400, Tom Rini wrote: >>>>> >>>>>> Hey all, >>>>>> >>>>>> This series adds NOR support to am335x_evm, along with a >>>>>> few generic changes to make gpmc clearer (for per-board >>>>>> things like different NOR chips, etc). This series >>>>>> depends on the last go-round of the am335x falcon mode docs >>>>>> as that adds the README that I add more content to. And >>>>>> while I say this in 3/8, to be clear, I expect to drop 3/8 >>>>>> in favor of Justin Waters' way of doing this instead, I >>>>>> just include this here for completeness and will get it all >>>>>> happy together when I assemble things in u-boot-ti. >>>>>> >>>>>> The big changes in v4 are: - Apply again to master which >>>>>> includes a few non-trivial updates, so the linker script >>>>>> got re-synced. - After checking what's going on, and >>>>>> testing with NAND again, we can be common with >>>>>> gpmc_cfg->irqstatus/enable, and only set documented bits >>>>>> in gpmc_cfg->config >>>>> >>>>> Applied to u-boot-ti/master, thanks! >>>> >>>> I'm now rebasing our NanoBone code onto the TI uboot code, but >>>> I'm coming up with the original issue [1] of having to not >>>> check for the R_ARM_RELATIVE relocations again. >>> >>> Your linker script is out of sync with arch/arm/cpu/u-boot.lds >> >> Strange ... since the am335x nor_boot compile appeared to work >> fine, I just copied the script from board/ti/am335x, and assumed >> it would work fine for me (with a library path change). >> >> So does this TI file also need updating ? >> >> Either way, my code now compiles. > > I had to re-sync the TI one in this series as well. Double check > between what you have working now vs before, there's a few small > changes there... Doh ... I was copying the script from the non-TI branch of uboot !! :-( ^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v4 0/8] am335x: NOR support 2013-08-13 15:20 ` Mark Jackson @ 2013-08-13 15:45 ` Mark Jackson 0 siblings, 0 replies; 18+ messages in thread From: Mark Jackson @ 2013-08-13 15:45 UTC (permalink / raw) To: u-boot On 13/08/13 16:20, Mark Jackson wrote: > On 13/08/13 16:11, Tom Rini wrote: >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> On 08/13/2013 11:06 AM, Mark Jackson wrote: >>> On 13/08/13 16:00, Tom Rini wrote: >>>> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 >>>> >>>> On 08/13/2013 10:57 AM, Mark Jackson wrote: >>>>> On 30/07/13 14:28, Tom Rini wrote: >>>>>> On Thu, Jul 18, 2013 at 03:12:57PM -0400, Tom Rini wrote: >>>>>> >>>>>>> Hey all, >>>>>>> >>>>>>> This series adds NOR support to am335x_evm, along with a >>>>>>> few generic changes to make gpmc clearer (for per-board >>>>>>> things like different NOR chips, etc). This series >>>>>>> depends on the last go-round of the am335x falcon mode docs >>>>>>> as that adds the README that I add more content to. And >>>>>>> while I say this in 3/8, to be clear, I expect to drop 3/8 >>>>>>> in favor of Justin Waters' way of doing this instead, I >>>>>>> just include this here for completeness and will get it all >>>>>>> happy together when I assemble things in u-boot-ti. >>>>>>> >>>>>>> The big changes in v4 are: - Apply again to master which >>>>>>> includes a few non-trivial updates, so the linker script >>>>>>> got re-synced. - After checking what's going on, and >>>>>>> testing with NAND again, we can be common with >>>>>>> gpmc_cfg->irqstatus/enable, and only set documented bits >>>>>>> in gpmc_cfg->config >>>>>> >>>>>> Applied to u-boot-ti/master, thanks! >>>>> >>>>> I'm now rebasing our NanoBone code onto the TI uboot code, but >>>>> I'm coming up with the original issue [1] of having to not >>>>> check for the R_ARM_RELATIVE relocations again. >>>> >>>> Your linker script is out of sync with arch/arm/cpu/u-boot.lds >>> >>> Strange ... since the am335x nor_boot compile appeared to work >>> fine, I just copied the script from board/ti/am335x, and assumed >>> it would work fine for me (with a library path change). >>> >>> So does this TI file also need updating ? >>> >>> Either way, my code now compiles. >> >> I had to re-sync the TI one in this series as well. Double check >> between what you have working now vs before, there's a few small >> changes there... > > Doh ... I was copying the script from the non-TI branch of uboot !! > > :-( > Well the code seems to work apart from I get no networking. We have dual ethernet, so I'll have to do some digging. ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2013-08-13 15:45 UTC | newest] Thread overview: 18+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-07-18 19:12 [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini 2013-07-18 19:12 ` [U-Boot] [PATCH v4 1/8] am335x_evm: Drop useless CONFIG_ENV_IS_NOWHERE Tom Rini 2013-07-18 19:12 ` [U-Boot] [PATCH v4 2/8] am335x_evm: Update SPI_BOOT support, add MTDPARTS info Tom Rini 2013-07-18 19:13 ` [U-Boot] [PATCH v4 3/8] am335x_evm: Only set CONFIG_NAND when !CONFIG_SPI_BOOT Tom Rini 2013-07-18 19:13 ` [U-Boot] [PATCH v4 4/8] am335x_evm: Rework board_is_foo() checks Tom Rini 2013-07-18 19:13 ` [U-Boot] [PATCH v4 5/8] am33xx: Correct gpmc_cfg->irqstatus/enable Tom Rini 2013-07-18 19:13 ` [U-Boot] [PATCH v4 6/8] am335x_evm: Add support for the NOR module on the memory cape Tom Rini 2013-07-18 19:13 ` [U-Boot] [PATCH v4 7/8] am335x_evm: Add support to boot from NOR Tom Rini 2013-07-18 19:21 ` Albert ARIBAUD 2013-07-18 19:47 ` Tom Rini 2013-07-18 19:13 ` [U-Boot] [PATCH v4 8/8] board/ti/am335x/README: Document NOR programming Tom Rini 2013-07-30 13:28 ` [U-Boot] [PATCH v4 0/8] am335x: NOR support Tom Rini 2013-08-13 14:57 ` Mark Jackson 2013-08-13 15:00 ` Tom Rini 2013-08-13 15:06 ` Mark Jackson 2013-08-13 15:11 ` Tom Rini 2013-08-13 15:20 ` Mark Jackson 2013-08-13 15:45 ` Mark Jackson
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