From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 13 Aug 2013 13:24:22 -0700 Subject: [U-Boot] [U-Boot, v1, 4/8] mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it In-Reply-To: <1374832955-4544-5-git-send-email-valentin.longchamp@keymile.com> References: <1374832955-4544-5-git-send-email-valentin.longchamp@keymile.com> Message-ID: <520A95F6.4030502@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 07/26/2013 03:02 AM, Valentin Longchamp wrote: > If the DDR3 module supports industrial temperature range and requires > the x2 refresh rate for that temp range, the refresh period must be > 3.9us instead of 7.8 us. > > Signed-off-by: Valentin Longchamp > > --- > arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c > index 3e7c269..603b68b 100644 > --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c > +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c > @@ -320,6 +320,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, > * = 3.9 us at ext temperature range > */ > pdimm->refresh_rate_ps = 7800000; > + if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) > + pdimm->refresh_rate_ps = 3900000; > > /* > * min four active window delay time > Has this been verified on a board? This looks half-way done. If the module supports extended temperature range, the MR2 should be adjusted to fit the module. York