From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Jackson Date: Wed, 14 Aug 2013 10:24:49 +0100 Subject: [U-Boot] [PATCH v4] Add Nanobone board support Message-ID: <520B4CE1.6050805@newflow.co.uk> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de NanoBone Specification: ----------------------- CPU: TI AM335x Memory: 256MB DDR3 64MB NOR flash 256MB NAND flash 128KB FRAM Ethernet: 2 x 10/100 connected to SMSC LAN8710 PHY USB: 1 x USB2.0 Type A I2C: 2Kbit EEPROM (Microchip 24AA02) RTC (Maxim DS1338) GPIO Expander (Microchip MCP23017) Expansion connector: 6 x UART 1 x MMC/SD 1 x USB2.0 Signed-off-by: Mark Jackson --- Changes in v4: - Tweaked after comments from Tom Rini - LEDs now initialised Changes in v3: - Rebased on TI U-Boot Changes in v2: - Tweaked after comments from Tom Rini MAINTAINERS | 4 + board/newflow/nanobone/Makefile | 38 +++++ board/newflow/nanobone/board.c | 298 +++++++++++++++++++++++++++++++++++++ board/newflow/nanobone/mux.c | 195 ++++++++++++++++++++++++ board/newflow/nanobone/u-boot.lds | 98 ++++++++++++ boards.cfg | 2 + include/configs/nanobone.h | 295 ++++++++++++++++++++++++++++++++++++ 7 files changed, 930 insertions(+) create mode 100644 board/newflow/nanobone/Makefile create mode 100644 board/newflow/nanobone/board.c create mode 100644 board/newflow/nanobone/mux.c create mode 100644 board/newflow/nanobone/u-boot.lds create mode 100644 include/configs/nanobone.h diff --git a/MAINTAINERS b/MAINTAINERS index 081cf96..4f44e8f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -717,6 +717,10 @@ Ilko Iliev PM9263 AT91SAM9263 PM9G45 ARM926EJS (AT91SAM9G45 SoC) +Mark Jackson + + NANOBONE ARM ARMV7 (AM33xx Soc) + Michael Jones omap3_mvblx ARM ARMV7 (OMAP3xx SoC) diff --git a/board/newflow/nanobone/Makefile b/board/newflow/nanobone/Makefile new file mode 100644 index 0000000..3dbeeda --- /dev/null +++ b/board/newflow/nanobone/Makefile @@ -0,0 +1,38 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y) +COBJS := mux.o +endif + +COBJS += board.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/newflow/nanobone/board.c b/board/newflow/nanobone/board.c new file mode 100644 index 0000000..743454b --- /dev/null +++ b/board/newflow/nanobone/board.c @@ -0,0 +1,298 @@ +/* + * board.c + * + * Board functions for Newflow NanoBone board + * + * Copyright (C) 2013, Newflow Ltd - http://www.newflow.co.uk/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* NOR Flash config */ +#define NOR_CS 0 +#define NOR_BASE 0x08000000 +#define NOR_SIZE GPMC_SIZE_128M +static u32 gpmc_nor_config[GPMC_MAX_REG] = { + 0x00001200, + 0x00101000, + 0x00030301, + 0x10041004, + 0x010f1010, + 0x08070280, + 0 +}; + +/* FRAM config */ +#define FRAM_CS 1 +#define FRAM_BASE 0x1c000000 +#define FRAM_SIZE GPMC_SIZE_16M +static u32 gpmc_fram_config[GPMC_MAX_REG] = { + 0x00001200, + 0x00101000, + 0x00020201, + 0x0f030f03, + 0x010d1010, + 0x000301c0, + 0 +}; + +static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + +/* MII mode defines */ +#define PORT1_MII_MODE_ENABLE 0x0 +#define PORT2_MII_MODE_ENABLE 0x0 + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41J128MJT125_RD_DQS, + .datawdsratio0 = MT41J128MJT125_WR_DQS, + .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, + .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41J128MJT125_RATIO, + .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, + + .cmd1csratio = MT41J128MJT125_RATIO, + .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, + + .cmd2csratio = MT41J128MJT125_RATIO, + .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41J128MJT125_EMIF_SDCFG, + .ref_ctrl = MT41J128MJT125_EMIF_SDREF, + .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, + .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, + .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, + .zq_config = MT41J128MJT125_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +#endif /* CONFIG_SPL_BUILD */ + +/* + * early system init of muxing and clocks. + */ +void s_init(void) +{ + /* + * The ROM will only have set up sufficient pinmux to allow for the + * first 4KiB NOR to be read, we must finish doing what we know of + * the NOR mux in this space in order to continue. + */ +#ifdef CONFIG_NOR_BOOT + asm("stmfd sp!, {r2 - r4}"); + asm("movw r4, #0x8A4"); + asm("movw r3, #0x44E1"); + asm("orr r4, r4, r3, lsl #16"); + asm("mov r2, #9"); + asm("mov r3, #8"); + asm("gpmc_mux: str r2, [r4], #4"); + asm("subs r3, r3, #1"); + asm("bne gpmc_mux"); + asm("ldmfd sp!, {r2 - r4}"); +#endif + + /* + * Save the boot parameters passed from romcode. + * We cannot delay the saving further than this, + * to prevent overwrites. + */ +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + save_omap_boot_params(); +#endif + + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + /* Setup the PLLs and the clocks for the peripherals */ + pll_init(); + + /* Enable RTC32K clock */ + rtc32k_enable(); + + enable_board_pin_mux(); + + uart_soft_reset(); + +#if defined(CONFIG_NOR_BOOT) + /* We want our console now. */ + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; +#else + gd = &gdata; + + preloader_console_init(); +#endif + + config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif /* CONFIG_SPL_BUILD */ +} + +/* + * Basic board specific setup. Pinmux has been handled already. + */ + +#define I2C_GPIO_ADDR 0x20 + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + + gpmc_init(); + + /* enable NOR flash chip select */ + enable_gpmc_cs_config(gpmc_nor_config, &gpmc_cfg->cs[NOR_CS], + NOR_BASE, NOR_SIZE); + /* enable FRAM chip select */ + enable_gpmc_cs_config(gpmc_fram_config, &gpmc_cfg->cs[FRAM_CS], + FRAM_BASE, FRAM_SIZE); + + /* init leds */ + i2c_reg_write(I2C_GPIO_ADDR, 0x00, 0xcf); + i2c_reg_write(I2C_GPIO_ADDR, 0x12, 0x30); + + return 0; +} + +int board_late_init(void) +{ + setenv("board_name", "nanobone"); + setenv("board_rev", "0002"); + + return 0; +} + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!getenv("ethaddr")) { + printf(" not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xff; + mac_addr[1] = (mac_hi & 0xff00) >> 8; + mac_addr[2] = (mac_hi & 0xff0000) >> 16; + mac_addr[3] = (mac_hi & 0xff000000) >> 24; + mac_addr[4] = mac_lo & 0xff; + mac_addr[5] = (mac_lo & 0xff00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + if (!getenv("eth1addr")) { + printf(" not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xff; + mac_addr[1] = (mac_hi & 0xff00) >> 8; + mac_addr[2] = (mac_hi & 0xff0000) >> 16; + mac_addr[3] = (mac_hi & 0xff000000) >> 24; + mac_addr[4] = mac_lo & 0xff; + mac_addr[5] = (mac_lo & 0xff00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + writel(PORT1_MII_MODE_ENABLE | PORT2_MII_MODE_ENABLE, &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + + return n; +} diff --git a/board/newflow/nanobone/mux.c b/board/newflow/nanobone/mux.c new file mode 100644 index 0000000..110a4a2 --- /dev/null +++ b/board/newflow/nanobone/mux.c @@ -0,0 +1,195 @@ +/* + * mux.c + * + * Copyright (C) 2013, Newflow Ltd - http://www.newflow.co.uk/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux gpmc_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD7 */ + {OFFSET(gpmc_ad8), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* GPMC AD15 */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* GPMC_CSN0 */ + {OFFSET(gpmc_csn1), (MODE(0) | PULLUDEN)}, /* GPMC_CSN1 */ + {OFFSET(gpmc_csn2), (MODE(0) | PULLUDEN)}, /* GPMC_CSN2 */ + {OFFSET(gpmc_csn3), (MODE(0) | PULLUDEN)}, /* GPMC_CSN3 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* GPMC_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* GPMC_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* GPMC_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* GPMC_BE_CLE */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE)}, /* NAND WAIT */ + {OFFSET(lcd_data1), (MODE(1) | PULLUDDIS)}, /* GPMC A17 */ + {OFFSET(lcd_data2), (MODE(1) | PULLUDDIS)}, /* GPMC A18 */ + {OFFSET(lcd_data3), (MODE(1) | PULLUDDIS)}, /* GPMC A19 */ + {OFFSET(lcd_data4), (MODE(1) | PULLUDDIS)}, /* GPMC A20 */ + {OFFSET(lcd_data5), (MODE(1) | PULLUDDIS)}, /* GPMC A21 */ + {OFFSET(lcd_data6), (MODE(1) | PULLUDDIS)}, /* GPMC A22 */ + {OFFSET(lcd_data7), (MODE(1) | PULLUDDIS)}, /* GPMC A23 */ + {OFFSET(lcd_vsync), (MODE(1) | PULLUDDIS)}, /* GPMC A24 */ + {OFFSET(lcd_hsync), (MODE(1) | PULLUDDIS)}, /* GPMC A25 */ + {OFFSET(lcd_pclk), (MODE(1) | PULLUDDIS)}, /* GPMC A26 */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */ + {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */ + {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */ + {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */ + {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */ + {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */ + {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */ + {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */ + {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */ + {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */ + {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ + {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ + {OFFSET(gpmc_wpn), MODE(1) | RXACTIVE}, /* MII2_RXERR */ + {OFFSET(gpmc_be1n), MODE(1) | RXACTIVE}, /* MII2_COL */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mmc0_no_cd_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(emu1), (MODE(7) | RXACTIVE)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_CTSN */ + {OFFSET(uart1_rtsn), (MODE(7) | PULLUDEN | RXACTIVE)}, /* UART1_RTSN */ + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(lcd_data8), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART2_CTSN */ + {OFFSET(lcd_data9), (MODE(7) | PULLUDEN | RXACTIVE)}, /* UART2_RTSN */ + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(lcd_data10), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART3_CTSN */ + {OFFSET(lcd_data11), (MODE(6) | PULLUDEN)}, /* UART3_RTSN */ + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(lcd_data12), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_CTSN */ + {OFFSET(lcd_data13), (MODE(6) | PULLUDEN)}, /* UART4_RTSN */ + {OFFSET(uart0_ctsn), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(uart0_rtsn), (MODE(1) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data14), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(rmii1_refclk), (MODE(3) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + +static struct module_pin_mux usb0_pin_mux[] = { + {OFFSET(usb0_dm), (MODE(0) | RXACTIVE)}, /* USB0_DM */ + {OFFSET(usb0_dp), (MODE(0) | RXACTIVE)}, /* USB0_DP */ + {OFFSET(usb0_ce), (MODE(0) | RXACTIVE)}, /* USB0_CE */ + {OFFSET(usb0_id), (MODE(0) | RXACTIVE)}, /* USB0_ID */ + {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE)}, /* USB0_VBUS */ + {OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)}, /* USB0_DRVVBUS */ + {-1}, +}; + +static struct module_pin_mux usb1_pin_mux[] = { + {OFFSET(usb1_dm), (MODE(0) | RXACTIVE)}, /* USB1_DM */ + {OFFSET(usb1_dp), (MODE(0) | RXACTIVE)}, /* USB1_DP */ + {OFFSET(usb1_ce), (MODE(0) | RXACTIVE)}, /* USB1_CE */ + {OFFSET(usb1_id), (MODE(0) | RXACTIVE)}, /* USB1_ID */ + {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE)}, /* USB1_VBUS */ + {OFFSET(usb1_drvvbus), (MODE(0) | PULLUDEN)}, /* USB1_DRVVBUS */ + {-1}, +}; + +void enable_board_pin_mux() +{ + configure_module_pin_mux(gpmc_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mii2_pin_mux); + configure_module_pin_mux(mmc0_no_cd_pin_mux); + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(uart1_pin_mux); + configure_module_pin_mux(uart2_pin_mux); + configure_module_pin_mux(uart3_pin_mux); + configure_module_pin_mux(uart4_pin_mux); + configure_module_pin_mux(uart5_pin_mux); + configure_module_pin_mux(usb0_pin_mux); + configure_module_pin_mux(usb1_pin_mux); +} diff --git a/board/newflow/nanobone/u-boot.lds b/board/newflow/nanobone/u-boot.lds new file mode 100644 index 0000000..809aea8 --- /dev/null +++ b/board/newflow/nanobone/u-boot.lds @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2013 Newflow Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + board/newflow/nanobone/libnanobone.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/boards.cfg b/boards.cfg index 211ed58..1e5ca5d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -252,6 +252,8 @@ am335x_evm_uart4 arm armv7 am335x ti am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=1,NAND am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT am335x_boneblack arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT +nanobone arm armv7 nanobone newflow am33xx nanobone:NOR_BOOT +nanobone_sdboot arm armv7 nanobone newflow am33xx nanobone:SD_BOOT ti814x_evm arm armv7 ti814x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC diff --git a/include/configs/nanobone.h b/include/configs/nanobone.h new file mode 100644 index 0000000..2cdc986 --- /dev/null +++ b/include/configs/nanobone.h @@ -0,0 +1,295 @@ +/* + * nanobone.h + * + * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_NANOBONE_H +#define __CONFIG_NANOBONE_H + +#define CONFIG_AM33XX +#define CONFIG_OMAP + +#include + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_BOARD_LATE_INIT +#define MACH_TYPE_NANOBONE 4483 +#define CONFIG_MACH_TYPE MACH_TYPE_NANOBONE + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* Custom script for NOR */ +#define CONFIG_SYS_LDSCRIPT "board/newflow/nanobone/u-boot.lds" + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* commands to include */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_VERSION_VARIABLE + +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 0 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#ifndef CONFIG_SPL_BUILD + +#ifdef CONFIG_SD_BOOT + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "mmcdev=0\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mtdparts default;" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "fi;" \ + +#endif /* CONFIG_SD_BOOT */ + +#ifdef CONFIG_NOR_BOOT + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80f80000\0" \ + "fdt_high=0xffffffff\0" \ + "kerneladdr=0x08100000\0" + +#define CONFIG_BOOTARGS \ + "console=ttyO0,115200n8 noinitrd ip=off mem=256M " \ + "rootwait=1 rootfstype=ubifs ubi.mtd=4,64 root=ubi0:rootfs rw " \ + "quiet" + +#define CONFIG_BOOTCOMMAND \ + "mtdparts default;" \ + "bootm ${kerneladdr}" + +#endif /* CONFIG_NOR_BOOT */ + +#endif /* CONFIG_SPL_BUILD */ + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_CMD_ECHO + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#undef CONFIG_CMD_MEMTEST + +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ + +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC + + /* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + /* Platform/Board specific defs */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_CONS_INDEX 1 + +/* I2C Configuration */ +#define CONFIG_I2C +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_DRIVER_OMAP24XX_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +#define CONFIG_OMAP_GPIO + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* CPU */ +#define CONFIG_ARCH_CPU_INIT + +#ifdef CONFIG_SD_BOOT +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +/* + * Place the image at the start of the ROM defined image space. + * We limit our size to the ROM-defined downloaded image area, and use the + * rest of the space for stack. + */ +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x NanoBone U-Boot SPL" +#define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT +#endif /* CONFIG_SD_BOOT */ + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#ifdef CONFIG_NOR_BOOT +#define CONFIG_SYS_TEXT_BASE 0x08000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#endif +#define CONFIG_SYS_SPL_MALLOC_START 0x80a08000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY_SMSC + +/* UBIFS support */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* NOR support + * + * NOR Size = 128 MiB + * Number of Sectors/Blocks = 1024 + * Sector Size = 128 KiB + * Word length = 16 bits + * Default layout: + * 0x00000000 - 0x000BFFFF : U-Boot (768 KiB) + * 0x000C0000 - 0x000DFFFF : First copy of U-Boot Environment (128 KiB) + * 0x000E0000 - 0x000FFFFF : Second copy of U-Boot Environment (128 KiB) + * 0x00100000 - 0x004FFFFF : Linux Kernel (4 MiB) + * 0x00500000 - 0x03FFFFFF : Root FS (59 MiB) + * 0x04000000 - 0x07FFFFFF : Data (64 MiB) + */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_FLASH +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor0=nor" +#define MTDPARTS_DEFAULT "mtdparts=nor:" \ + "768k(u-boot)," \ + "128k(u-boot-env1)," \ + "128k(u-boot-env2)," \ + "4m(kernel)," \ + "16m(rootfs)," \ + "43m(user)," \ + "64m(data)" +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB */ +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB */ + +#endif /* ! __CONFIG_NANOBONE_H */ -- 1.7.9.5