From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Date: Wed, 14 Aug 2013 10:05:04 -0600 Subject: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific In-Reply-To: <1374174821-19981-1-git-send-email-thierry.reding@gmail.com> References: <1374174821-19981-1-git-send-email-thierry.reding@gmail.com> Message-ID: <520BAAB0.6040609@wwwdotorg.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 07/18/2013 01:13 PM, Thierry Reding wrote: > From: Thierry Reding > > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This > isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and > therefore uses a cache line size of 64 bytes. Move the cache line size > setting to the per-SoC common configuration file. Tom, can these two patches be applied please?