[U-Boot] Enabling L2 cache on mx53

[Stefano Babic <sbabic@denx.de>]

Hi Marek,

On 19/08/2013 22:31, Marek Vasut wrote:
> Dear Fabio Estevam,
> 
>> Hi Marek,
>>
>> On Mon, Aug 19, 2013 at 4:51 PM, Marek Vasut <marex@denx.de> wrote:
>>> L2CC on MX53 is enabled by setting just the L2ON and C bits in CP15,
>>> there's no configuration. Not even Linux enables the L2CC on MX53, so if
>>> it's not on in U- Boot, then it's not on at all (and that sucks).
>>
>> This is what I have done:
>>
>> --- a/arch/arm/cpu/armv7/mx5/
>> lowlevel_init.S
>> +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
>> @@ -45,6 +45,11 @@
>>  #endif
>>
>>         mcr 15, 1, r0, c9, c0, 2
>> +
>> +       /* enable L2 cache */
>> +       mrc 15, 0, r0, c1, c0, 1
>> +       orr r0, r0, #(1 << 1)    /* enable l2 cache */
>> +       mcr 15, 0, r0, c1, c0, 1
>>  .endm /* init_l2cc */
>>
>>  /* AIPS setup - Only setup MPROTx registers.
>>
>> Anything else I am missing?
> 
> Try profiling the RX routine, maybe it's looping somewhere there for too long.
> 

But the RX routine belongs to the FEC driver that it is used by all
i.MXes. Is there maybe a problem with the phy and the negotiated speed
is less than expected ?

Best regards,
Stefano Babic


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