[U-Boot] [PATCH] am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF

[U-Boot] [PATCH] am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF

[Tom Rini]

Test on Beaglebone white over cpsw, usb ether and SD card (read and
write), performance increased, crc32 of data matches.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/board.c |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 2ea3d69..c261af5 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -225,3 +225,11 @@ void s_init(void)
 	sdram_init();
 #endif
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif /* !CONFIG_SYS_DCACHE_OFF */
-- 
1.7.9.5

[U-Boot] [PATCH] am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF

[Sricharan R]

Hi Tom,

On Friday 23 August 2013 09:56 PM, Tom Rini wrote:
> Test on Beaglebone white over cpsw, usb ether and SD card (read and
> write), performance increased, crc32 of data matches.
>
> Signed-off-by: Tom Rini <trini@ti.com>
> ---
>  arch/arm/cpu/armv7/am33xx/board.c |    8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
> index 2ea3d69..c261af5 100644
> --- a/arch/arm/cpu/armv7/am33xx/board.c
> +++ b/arch/arm/cpu/armv7/am33xx/board.c
> @@ -225,3 +225,11 @@ void s_init(void)
>  	sdram_init();
>  #endif
>  }
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +void enable_caches(void)
> +{
> +	/* Enable D-cache. I-cache is already enabled in start.S */
> +	dcache_enable();
> +}
> +#endif /* !CONFIG_SYS_DCACHE_OFF */
 This is fine. Do we have secure devices here ?

 If so, we should take care of setting the domains permissions for
 avoiding prefetch aborts. As it was done for OMAP using
 arm_init_domains. So that function and the above should be executed on
 am33xx as well.

 Thanks to Lokesh for reminding this.

Regards,
 Sricharan

[U-Boot] [PATCH] am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF

[Tom Rini]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 08/30/2013 12:50 AM, Sricharan R wrote:
> Hi Tom,
> 
> On Friday 23 August 2013 09:56 PM, Tom Rini wrote:
>> Test on Beaglebone white over cpsw, usb ether and SD card (read and
>> write), performance increased, crc32 of data matches.
>>
>> Signed-off-by: Tom Rini <trini@ti.com>
>> ---
>>  arch/arm/cpu/armv7/am33xx/board.c |    8 ++++++++
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
>> index 2ea3d69..c261af5 100644
>> --- a/arch/arm/cpu/armv7/am33xx/board.c
>> +++ b/arch/arm/cpu/armv7/am33xx/board.c
>> @@ -225,3 +225,11 @@ void s_init(void)
>>  	sdram_init();
>>  #endif
>>  }
>> +
>> +#ifndef CONFIG_SYS_DCACHE_OFF
>> +void enable_caches(void)
>> +{
>> +	/* Enable D-cache. I-cache is already enabled in start.S */
>> +	dcache_enable();
>> +}
>> +#endif /* !CONFIG_SYS_DCACHE_OFF */
>  This is fine. Do we have secure devices here ?
> 
>  If so, we should take care of setting the domains permissions for
>  avoiding prefetch aborts. As it was done for OMAP using
>  arm_init_domains. So that function and the above should be executed on
>  am33xx as well.
> 
>  Thanks to Lokesh for reminding this.

Yes, but I can't easily test them.  I'll see if arm_init_domains just
works on non-HS devices (I know I had a failure pulling all the OMAP4
code over, but didn't try hard, just looked again at the "easy" path).

- -- 
Tom
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[U-Boot] [PATCH] am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF

[Tom Rini]

On Fri, Aug 30, 2013 at 05:07:17PM -0400, Tom Rini wrote:

> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> On 08/30/2013 12:50 AM, Sricharan R wrote:
> > Hi Tom,
> > 
> > On Friday 23 August 2013 09:56 PM, Tom Rini wrote:
> >> Test on Beaglebone white over cpsw, usb ether and SD card (read and
> >> write), performance increased, crc32 of data matches.
> >>
> >> Signed-off-by: Tom Rini <trini@ti.com>
> >> ---
> >>  arch/arm/cpu/armv7/am33xx/board.c |    8 ++++++++
> >>  1 file changed, 8 insertions(+)
> >>
> >> diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
> >> index 2ea3d69..c261af5 100644
> >> --- a/arch/arm/cpu/armv7/am33xx/board.c
> >> +++ b/arch/arm/cpu/armv7/am33xx/board.c
> >> @@ -225,3 +225,11 @@ void s_init(void)
> >>  	sdram_init();
> >>  #endif
> >>  }
> >> +
> >> +#ifndef CONFIG_SYS_DCACHE_OFF
> >> +void enable_caches(void)
> >> +{
> >> +	/* Enable D-cache. I-cache is already enabled in start.S */
> >> +	dcache_enable();
> >> +}
> >> +#endif /* !CONFIG_SYS_DCACHE_OFF */
> >  This is fine. Do we have secure devices here ?
> > 
> >  If so, we should take care of setting the domains permissions for
> >  avoiding prefetch aborts. As it was done for OMAP using
> >  arm_init_domains. So that function and the above should be executed on
> >  am33xx as well.
> > 
> >  Thanks to Lokesh for reminding this.
> 
> Yes, but I can't easily test them.  I'll see if arm_init_domains just
> works on non-HS devices (I know I had a failure pulling all the OMAP4
> code over, but didn't try hard, just looked again at the "easy" path).

Yeah, that code as-is hangs the boards.  So if the HS devices need
something, it'll go with the rest of their patches until we're moving it
upstream.  But good to note a potential problem area!

-- 
Tom
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[U-Boot] [PATCH] am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF

[Lokesh Vutla]

Hi Tom,
On Saturday 31 August 2013 02:43 AM, Tom Rini wrote:
> On Fri, Aug 30, 2013 at 05:07:17PM -0400, Tom Rini wrote:
> 
>> -----BEGIN PGP SIGNED MESSAGE-----
>> Hash: SHA1
>>
>> On 08/30/2013 12:50 AM, Sricharan R wrote:
>>> Hi Tom,
>>>
>>> On Friday 23 August 2013 09:56 PM, Tom Rini wrote:
>>>> Test on Beaglebone white over cpsw, usb ether and SD card (read and
>>>> write), performance increased, crc32 of data matches.
>>>>
>>>> Signed-off-by: Tom Rini <trini@ti.com>
>>>> ---
>>>>  arch/arm/cpu/armv7/am33xx/board.c |    8 ++++++++
>>>>  1 file changed, 8 insertions(+)
>>>>
>>>> diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
>>>> index 2ea3d69..c261af5 100644
>>>> --- a/arch/arm/cpu/armv7/am33xx/board.c
>>>> +++ b/arch/arm/cpu/armv7/am33xx/board.c
>>>> @@ -225,3 +225,11 @@ void s_init(void)
>>>>  	sdram_init();
>>>>  #endif
>>>>  }
>>>> +
>>>> +#ifndef CONFIG_SYS_DCACHE_OFF
>>>> +void enable_caches(void)
>>>> +{
>>>> +	/* Enable D-cache. I-cache is already enabled in start.S */
>>>> +	dcache_enable();
>>>> +}
>>>> +#endif /* !CONFIG_SYS_DCACHE_OFF */
>>>  This is fine. Do we have secure devices here ?
>>>
>>>  If so, we should take care of setting the domains permissions for
>>>  avoiding prefetch aborts. As it was done for OMAP using
>>>  arm_init_domains. So that function and the above should be executed on
>>>  am33xx as well.
>>>
>>>  Thanks to Lokesh for reminding this.
>>
>> Yes, but I can't easily test them.  I'll see if arm_init_domains just
>> works on non-HS devices (I know I had a failure pulling all the OMAP4
>> code over, but didn't try hard, just looked again at the "easy" path).
> 
> Yeah, that code as-is hangs the boards.  So if the HS devices need
> something, it'll go with the rest of their patches until we're moving it
> upstream.  But good to note a potential problem area!
I added the following diff and I am able to boot my BBB over cpsw.

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 2ea3d69..8a1a29a 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -31,6 +31,11 @@
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
 #include <asm/omap_musb.h>
+#include <asm/cache.h>
+
+#define ARMV7_DCACHE_WRITEBACK  0xe
+#define ARMV7_DOMAIN_CLIENT	1
+#define ARMV7_DOMAIN_MASK	(0x3 << 0)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -225,3 +230,40 @@ void s_init(void)
 	sdram_init();
 #endif
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+	bd_t *bd = gd->bd;
+	int	i;
+
+	u32 start = bd->bi_dram[bank].start >> 20;
+	u32 size = bd->bi_dram[bank].size >> 20;
+	u32 end = start + size;
+
+	debug("%s: bank: %d\n", __func__, bank);
+	for (i = start; i < end; i++)
+		set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
+
+}
+
+void arm_init_domains(void)
+{
+	u32 reg;
+
+	reg = get_dacr();
+	/*
+	* Set DOMAIN to client access so that all permissions
+	* set in pagetables are validated by the mmu.
+	*/
+	reg &= ~ARMV7_DOMAIN_MASK;
+	reg |= ARMV7_DOMAIN_CLIENT;
+	set_dacr(reg);
+}
+#endif

AM I missing something here ?

Thanks and regards,
Lokesh
> 
> 
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
> 

[U-Boot] [PATCH] am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF

[Tom Rini]

On Mon, Sep 02, 2013 at 09:22:34AM +0530, Lokesh Vutla wrote:
> Hi Tom,
> On Saturday 31 August 2013 02:43 AM, Tom Rini wrote:
> > On Fri, Aug 30, 2013 at 05:07:17PM -0400, Tom Rini wrote:
> > 
> >> -----BEGIN PGP SIGNED MESSAGE-----
> >> Hash: SHA1
> >>
> >> On 08/30/2013 12:50 AM, Sricharan R wrote:
> >>> Hi Tom,
> >>>
> >>> On Friday 23 August 2013 09:56 PM, Tom Rini wrote:
> >>>> Test on Beaglebone white over cpsw, usb ether and SD card (read and
> >>>> write), performance increased, crc32 of data matches.
> >>>>
> >>>> Signed-off-by: Tom Rini <trini@ti.com>
> >>>> ---
> >>>>  arch/arm/cpu/armv7/am33xx/board.c |    8 ++++++++
> >>>>  1 file changed, 8 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
> >>>> index 2ea3d69..c261af5 100644
> >>>> --- a/arch/arm/cpu/armv7/am33xx/board.c
> >>>> +++ b/arch/arm/cpu/armv7/am33xx/board.c
> >>>> @@ -225,3 +225,11 @@ void s_init(void)
> >>>>  	sdram_init();
> >>>>  #endif
> >>>>  }
> >>>> +
> >>>> +#ifndef CONFIG_SYS_DCACHE_OFF
> >>>> +void enable_caches(void)
> >>>> +{
> >>>> +	/* Enable D-cache. I-cache is already enabled in start.S */
> >>>> +	dcache_enable();
> >>>> +}
> >>>> +#endif /* !CONFIG_SYS_DCACHE_OFF */
> >>>  This is fine. Do we have secure devices here ?
> >>>
> >>>  If so, we should take care of setting the domains permissions for
> >>>  avoiding prefetch aborts. As it was done for OMAP using
> >>>  arm_init_domains. So that function and the above should be executed on
> >>>  am33xx as well.
> >>>
> >>>  Thanks to Lokesh for reminding this.
> >>
> >> Yes, but I can't easily test them.  I'll see if arm_init_domains just
> >> works on non-HS devices (I know I had a failure pulling all the OMAP4
> >> code over, but didn't try hard, just looked again at the "easy" path).
> > 
> > Yeah, that code as-is hangs the boards.  So if the HS devices need
> > something, it'll go with the rest of their patches until we're moving it
> > upstream.  But good to note a potential problem area!
> I added the following diff and I am able to boot my BBB over cpsw.
> 
> diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
> index 2ea3d69..8a1a29a 100644
> --- a/arch/arm/cpu/armv7/am33xx/board.c
> +++ b/arch/arm/cpu/armv7/am33xx/board.c
> @@ -31,6 +31,11 @@
>  #include <linux/usb/gadget.h>
>  #include <linux/usb/musb.h>
>  #include <asm/omap_musb.h>
> +#include <asm/cache.h>
> +
> +#define ARMV7_DCACHE_WRITEBACK  0xe
> +#define ARMV7_DOMAIN_CLIENT	1
> +#define ARMV7_DOMAIN_MASK	(0x3 << 0)
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -225,3 +230,40 @@ void s_init(void)
>  	sdram_init();
>  #endif
>  }
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +void enable_caches(void)
> +{
> +	/* Enable D-cache. I-cache is already enabled in start.S */
> +	dcache_enable();
> +}
> +
> +void dram_bank_mmu_setup(int bank)
> +{
> +	bd_t *bd = gd->bd;
> +	int	i;
> +
> +	u32 start = bd->bi_dram[bank].start >> 20;
> +	u32 size = bd->bi_dram[bank].size >> 20;
> +	u32 end = start + size;
> +
> +	debug("%s: bank: %d\n", __func__, bank);
> +	for (i = start; i < end; i++)
> +		set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
> +
> +}
> +
> +void arm_init_domains(void)
> +{
> +	u32 reg;
> +
> +	reg = get_dacr();
> +	/*
> +	* Set DOMAIN to client access so that all permissions
> +	* set in pagetables are validated by the mmu.
> +	*/
> +	reg &= ~ARMV7_DOMAIN_MASK;
> +	reg |= ARMV7_DOMAIN_CLIENT;
> +	set_dacr(reg);
> +}
> +#endif
> 
> AM I missing something here ?

Or I am.  That gives me a straight up hang, like I saw before.  What
toolchain are you using?  I'm trying ELDK 5.2 and Linaro 2013.04.

-- 
Tom
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[U-Boot] am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF

[Tom Rini]

On Fri, Aug 23, 2013 at 12:26:49PM -0400, Tom Rini wrote:

> Test on Beaglebone white over cpsw, usb ether and SD card (read and
> write), performance increased, crc32 of data matches.
> 
> Signed-off-by: Tom Rini <trini@ti.com>

Applied to u-boot-ti/master, thanks!

-- 
Tom
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