[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Alban Bedel]

Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de>
---
 arch/arm/cpu/tegra-common/ap.c          | 1 +
 arch/arm/include/asm/arch-tegra/tegra.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 6fb11cb..9e4085c 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -71,6 +71,7 @@ int tegra_get_chip_sku(void)
 		switch (sku_id) {
 		case SKU_ID_T33:
 		case SKU_ID_T30:
+		case SKU_ID_T30MQS:
 			return TEGRA_SOC_T30;
 		}
 		break;
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 25d1fc4..6b6ce85 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -65,6 +65,7 @@ enum {
 	SKU_ID_T25E		= 0x1c,
 	SKU_ID_T33		= 0x80,
 	SKU_ID_T30		= 0x81, /* Cardhu value */
+	SKU_ID_T30MQS		= 0xb1,
 	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
 	SKU_ID_T114_1		= 0x01,
 };
-- 
1.8.4

[U-Boot] [PATCH 2/2] ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board

[Alban Bedel]

Add support for the new Tamonten? NG platform from Avionic Design.
Currently only I2C, MMC, USB and ethernet have been tested.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
---
 .../common/pinmux-config-tamonten-ng.h             | 385 +++++++++++++++++++++
 board/avionic-design/common/tamonten-ng.c          | 129 +++++++
 board/avionic-design/dts/tegra30-tamonten.dtsi     |  74 ++++
 board/avionic-design/dts/tegra30-tec-ng.dts        |   8 +
 board/avionic-design/tec-ng/Makefile               |  32 ++
 boards.cfg                                         |   1 +
 include/configs/tec-ng.h                           |  84 +++++
 7 files changed, 713 insertions(+)
 create mode 100644 board/avionic-design/common/pinmux-config-tamonten-ng.h
 create mode 100644 board/avionic-design/common/tamonten-ng.c
 create mode 100644 board/avionic-design/dts/tegra30-tamonten.dtsi
 create mode 100644 board/avionic-design/dts/tegra30-tec-ng.dts
 create mode 100644 board/avionic-design/tec-ng/Makefile
 create mode 100644 include/configs/tec-ng.h

diff --git a/board/avionic-design/common/pinmux-config-tamonten-ng.h b/board/avionic-design/common/pinmux-config-tamonten-ng.h
new file mode 100644
index 0000000..39df731
--- /dev/null
+++ b/board/avionic-design/common/pinmux-config-tamonten-ng.h
@@ -0,0 +1,385 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
+#define _PINMUX_CONFIG_TAMONTEN_NG_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)	\
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{							\
+		.padgrp		= PDRIVE_PINGROUP_##_padgrp,	\
+		.slwf		= _slwf,			\
+		.slwr		= _slwr,			\
+		.drvup		= _drvup,			\
+		.drvdn		= _drvdn,			\
+		.lpmd		= PGRP_LPMD_##_lpmd,		\
+		.schmt		= PGRP_SCHMT_##_schmt,		\
+		.hsm		= PGRP_HSM_##_hsm,		\
+	}
+
+static struct pingroup_config tamonten_ng_pinmux_common[] = {
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK,  SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD,  SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP,     NORMAL, INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK,  SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD,  SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_IORDY,   RSVD1,  UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_CS6_N,   RSVD1,  UP,     NORMAL, INPUT),
+
+	/* SDMMC4 pinmux */
+	LV_PINMUX(SDMMC4_CLK,   SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD,   SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N, RSVD1,  DOWN,   NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* UART1 */
+	DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+
+	/* UART2 */
+	DEFAULT_PINMUX(UART2_RXD,   UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD,   UARTB, NORMAL, NORMAL, OUTPUT),
+
+	/* UART3 */
+	DEFAULT_PINMUX(UART3_TXD,   UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD,   UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+
+	/* UART4 */
+	DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR, UARTD, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+
+	/* DAP */
+	DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+
+	/* I2S1 */
+	DEFAULT_PINMUX(DAP2_FS,   I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DIN,  I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+
+	/* SPDIF */
+	DEFAULT_PINMUX(SPDIF_IN,  SPDIF, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+
+	/* I2S2 */
+	DEFAULT_PINMUX(DAP3_FS,   I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN,  I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+
+	/* DAP4 */
+	DEFAULT_PINMUX(DAP4_FS,   I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DIN,  I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+
+	/* Tamonten GPIO */
+	DEFAULT_PINMUX(GPIO_PV2,   RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PV3,   RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI2_CS1_N, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* LCD */
+	DEFAULT_PINMUX(LCD_PWR1,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR2,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDIN,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_WR_N,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC0,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SCK,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR0,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PCLK,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DE,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D0,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D1,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D2,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D3,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D4,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D5,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D6,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D7,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D8,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D9,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D10,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D11,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D12,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D13,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D14,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D15,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D16,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D17,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D18,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D19,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D20,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D21,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D22,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D23,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_M1,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC1,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CRT_HSYNC, CRT,   NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CRT_VSYNC, CRT,   NORMAL, NORMAL, OUTPUT),
+
+	/* BT656 */
+	LV_PINMUX(VI_MCLK,  VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_PCLK,  VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_HSYNC, VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_VSYNC, VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D2,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D3,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D4,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D5,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D6,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D7,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D8,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D9,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D11,   RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* GPIOs */
+	DEFAULT_PINMUX(GPIO_PU5, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* LCD BL */
+	DEFAULT_PINMUX(GMI_AD8,  PWM0,  NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD10, RSVD4, NORMAL, NORMAL, OUTPUT),
+
+	/* SPI4 */
+	DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+
+	/* Video input GPIO */
+	DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Sensor GPIO */
+	DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* JTAG */
+	DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+	/* Power controls */
+	DEFAULT_PINMUX(GMI_CS2_N, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* SPI1 */
+	DEFAULT_PINMUX(SPI1_MOSI,  SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK,   SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO,  SPI1, NORMAL, NORMAL, INPUT),
+
+	/* PMU */
+	DEFAULT_PINMUX(GPIO_PV0,    RSVD1,  UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK_32K_IN,  SYSCLK, NORMAL, NORMAL, INPUT),
+
+	/* PCI */
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N,  PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_RST_N,    PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_WAKE_N,      PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N,  PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_RST_N,    PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N,  PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N,    PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+
+	/* HDMI */
+	DEFAULT_PINMUX(HDMI_CEC, CEC,   NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+	/* UART1 - NC */
+	DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT),
+
+	/* UART2 - NC */
+	DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+
+	/* DAP - NC */
+	DEFAULT_PINMUX(CLK1_REQ,  RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK3_OUT,  RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK3_REQ,  RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* DAP4 - NC */
+	DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+
+	/* Tamonten GPIO - NC */
+	DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_REQ, DAP,        NORMAL, NORMAL, INPUT),
+
+	/* BT656 - NC */
+	LV_PINMUX(VI_D0,  RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D1,  RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* GPIO - NC */
+	DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Video input - NC */
+	DEFAULT_PINMUX(CAM_MCLK,  RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB5, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW11,  RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* KBC keys - NC */
+	DEFAULT_PINMUX(KB_ROW0,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW1,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW2,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW3,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW4,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW5,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW6,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW7,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW9,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL0,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL1,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL2,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL3,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL4,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL5,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL6,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL7,  KBC, UP, NORMAL, INPUT),
+
+	/* PMU - NC */
+	DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Power rails GPIO - NC */
+	DEFAULT_PINMUX(SPI2_SCK,  RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB4, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Others - NC */
+	DEFAULT_PINMUX(GMI_WP_N,   RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PV1,   RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WAIT,   NAND, UP,     TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_ADV_N,  NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CLK,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N,  NAND, NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N,  NAND, UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_AD0,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD1,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD2,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD3,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD4,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD5,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD6,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD7,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD9,    PWM1, NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11,   NAND, NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13,   NAND, UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_WR_N,   NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_OE_N,   NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_DQS,    NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+static struct padctrl_config tamonten_ng_padctrl[] = {
+	/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+	DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
+		SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif	/* _PINMUX_CONFIG_TAMONTEN_NG_H_ */
diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c
new file mode 100644
index 0000000..7a17839
--- /dev/null
+++ b/board/avionic-design/common/tamonten-ng.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include "pinmux-config-tamonten-ng.h"
+#include <i2c.h>
+
+#define PMU_I2C_ADDRESS		0x2D
+#define MAX_I2C_RETRY		3
+
+#define PMU_REG_LDO1		0x30
+#define PMU_REG_LDO2		0x31
+#define PMU_REG_LDO5		0x32
+#define PMU_REG_LDO8		0x33
+#define PMU_REG_LDO7		0x34
+#define PMU_REG_LDO6		0x35
+#define PMU_REG_LDO4		0x36
+#define PMU_REG_LDO3		0x37
+
+#define PMU_REG_LDO_OFF		0
+#define PMU_REG_LDO_HIGH_POWER	1
+#define PMU_REG_LDO_LOW_POWER	3
+
+/* Voltage selection for the LDOs with 50mV resolution */
+#define PMU_REG_LDO_SEL_50(mV)	((((mV - 1000) / 50) + 4) << 2)
+/* Voltage selection for the LDOs with 100mV resolution */
+#define PMU_REG_LDO_SEL_100(mV)	((((mV - 1000) / 100) + 2) << 2)
+
+#define PMU_REG_LDO_50(st, mV)	(PMU_REG_LDO_##st | PMU_REG_LDO_SEL_50(mV))
+#define PMU_REG_LDO_100(st, mV)	(PMU_REG_LDO_##st | PMU_REG_LDO_SEL_50(mV))
+
+#define PMU_LDO1(st, mV)	PMU_REG_LDO_50(st, mV)
+#define PMU_LDO2(st, mV)	PMU_REG_LDO_50(st, mV)
+#define PMU_LDO5(st, mV)	PMU_REG_LDO_100(st, mV)
+#define PMU_LDO8(st, mV)	PMU_REG_LDO_100(st, mV)
+#define PMU_LDO7(st, mV)	PMU_REG_LDO_100(st, mV)
+#define PMU_LDO6(st, mV)	PMU_REG_LDO_100(st, mV)
+#define PMU_LDO4(st, mV)	PMU_REG_LDO_50(st, mV)
+#define PMU_LDO3(st, mV)	PMU_REG_LDO_100(st, mV)
+
+void pinmux_init(void)
+{
+	pinmux_config_table(tamonten_ng_pinmux_common,
+			    ARRAY_SIZE(tamonten_ng_pinmux_common));
+	pinmux_config_table(unused_pins_lowpower,
+			    ARRAY_SIZE(unused_pins_lowpower));
+
+	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
+	padgrp_config_table(tamonten_ng_padctrl,
+			    ARRAY_SIZE(tamonten_ng_padctrl));
+}
+
+
+void pmu_write(uchar reg, uchar data)
+{
+	int i;
+	i2c_set_bus_num(0);	/* PMU is on bus 0 */
+	for (i = 0; i < MAX_I2C_RETRY; ++i) {
+		if (i2c_write(PMU_I2C_ADDRESS, reg, 1, &data, 1))
+			udelay(100);
+		else
+			break;
+	}
+}
+
+void power_init_board(void)
+{
+	/* Set the periphs in reset */
+	gpio_request(GPIO_PI4, "nRST_PERIPH");
+	gpio_direction_output(GPIO_PI4, 0);
+
+	/* Disable the PCIe power */
+	gpio_request(GPIO_PT3, "EN_3V3_PEX_HVDD");
+	gpio_direction_output(GPIO_PT3, 0);
+
+	/* Disable the SATA power */
+	gpio_request(GPIO_PK3, "EN_3V3_SATA_HVDD");
+	gpio_direction_output(GPIO_PK3, 0);
+
+	/* Disable LDO1 for PCIe and SATA */
+	pmu_write(PMU_REG_LDO1, PMU_LDO1(OFF, 1050));
+
+	/* Turn on the alive signal */
+	gpio_request(GPIO_PV2, "ALIVE");
+	gpio_direction_output(GPIO_PV2, 1);
+
+	/* Wait for the periph to finish their reset */
+	udelay(1000);
+	gpio_direction_output(GPIO_PI4, 1);
+}
+
+#if defined(CONFIG_TEGRA_MMC)
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+	/* Enable LDO5 with 3.3v for SDMMC3 */
+	pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
+
+	/* Switch the power on */
+	gpio_request(GPIO_PJ2, "EN_3V3_EMMC");
+	gpio_direction_output(GPIO_PJ2, 1);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+	/*
+	 * NOTE: We don't do mmc-specific pin muxes here.
+	 * They were done globally in pinmux_init().
+	 */
+
+	/* Bring up the SDIO1 power rail */
+	board_sdmmc_voltage_init();
+}
+#endif	/* MMC */
diff --git a/board/avionic-design/dts/tegra30-tamonten.dtsi b/board/avionic-design/dts/tegra30-tamonten.dtsi
new file mode 100644
index 0000000..d80b177
--- /dev/null
+++ b/board/avionic-design/dts/tegra30-tamonten.dtsi
@@ -0,0 +1,74 @@
+#include "tegra30.dtsi"
+
+/ {
+	model = "Avionic Design Tamonten NG";
+	compatible = "ad,tamonten-ng", "nvidia,tegra30";
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	aliases {
+		i2c0 = "/i2c at 7000d000";
+		i2c1 = "/i2c at 7000c000";
+		i2c2 = "/i2c at 7000c400";
+		i2c3 = "/i2c at 7000c500";
+		i2c4 = "/i2c at 7000c700";
+		sdhci0 = "/sdhci at 78000600";
+		sdhci1 = "/sdhci at 78000400";
+		sdhci2 = "/sdhci at 78000000";
+		usb0 = "/usb at 7d008000";
+	};
+
+	i2c at 7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c at 7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c at 7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c at 7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c at 7000d000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	spi at 7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	sdhci at 78000000 {
+		status = "okay";
+		bus-width = <4>;
+	};
+
+	sdhci at 78000400 {
+		status = "okay";
+		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+		wp-gpios = <&gpio 67 0>; /* gpio PI3 */
+		bus-width = <4>;
+	};
+
+	sdhci at 78000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	usb at 7d008000 {
+		status = "okay";
+	};
+
+};
diff --git a/board/avionic-design/dts/tegra30-tec-ng.dts b/board/avionic-design/dts/tegra30-tec-ng.dts
new file mode 100644
index 0000000..244b99d
--- /dev/null
+++ b/board/avionic-design/dts/tegra30-tec-ng.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+
+#include "tegra30-tamonten.dtsi"
+
+/ {
+	model = "Avionic Design Tamonten? NG Evaluation Carrier";
+	compatible = "ad,tec-ng", "nvidia,tegra30";
+};
diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile
new file mode 100644
index 0000000..22e19e0
--- /dev/null
+++ b/board/avionic-design/tec-ng/Makefile
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2013
+# Avionic Design GmbH <www.avionic-design.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= ../common/tamonten-ng.o
+
+include ../../nvidia/common/common.mk
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/boards.cfg b/boards.cfg
index be810c7..ff8fa0c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -374,6 +374,7 @@ jornada                      arm         sa1100
 plutux                       arm         armv7:arm720t plutux            avionic-design tegra20
 medcom-wide                  arm         armv7:arm720t medcom-wide       avionic-design tegra20
 tec                          arm         armv7:arm720t tec               avionic-design tegra20
+tec-ng                       arm         armv7:arm720t tec-ng            avionic-design tegra30
 paz00                        arm         armv7:arm720t paz00             compal         tegra20
 trimslice                    arm         armv7:arm720t trimslice         compulab       tegra20
 atngw100                     avr32       at32ap      -                   atmel          at32ap700x
diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
new file mode 100644
index 0000000..13baa76
--- /dev/null
+++ b/include/configs/tec-ng.h
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra30-common.h"
+
+/* Enable fdt support for tec-ng. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-tec-ng
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT			"Tegra30 (TEC-NG) # "
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamonten? NG Evaluation Carrier"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* SPI */
+#define CONFIG_TEGRA20_SLINK
+#define CONFIG_TEGRA_SLINK_CTRLS       6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+/* Tag support */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+/* support the new (FDT-based) image format */
+#define CONFIG_FIT
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
-- 
1.8.4

[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Stephen Warren]

On 09/04/2013 07:00 AM, Alban Bedel wrote:
> Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.

CC'ing the Tegra maintainer would be helpful (Tom Warren; I CC'd him here)

> diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c

> @@ -71,6 +71,7 @@ int tegra_get_chip_sku(void)
>  		switch (sku_id) {
>  		case SKU_ID_T33:
>  		case SKU_ID_T30:
> +		case SKU_ID_T30MQS:

Where does the name "T30MQS" come from? Tom, can you verify what we call
the SKUs internally?

[U-Boot] [PATCH 2/2] ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board

[Stephen Warren]

On 09/04/2013 07:00 AM, Alban Bedel wrote:
> Add support for the new Tamonten? NG platform from Avionic Design. 
> Currently only I2C, MMC, USB and ethernet have been tested.

(Also CC'ing the Tegra maintainer here)

> diff --git a/board/avionic-design/common/tamonten-ng.c
> b/board/avionic-design/common/tamonten-ng.c

> +void pmu_write(uchar reg, uchar data) +{ +	int i; +
> i2c_set_bus_num(0);	/* PMU is on bus 0 */ +	for (i = 0; i <
> MAX_I2C_RETRY; ++i) { +		if (i2c_write(PMU_I2C_ADDRESS, reg, 1,
> &data, 1)) +			udelay(100); +		else +			break; +	} +}

Is there really a need to retry the I2C transactions? If so, why do
they fail? I assume this was just copy/pasted from some other board
file, and there's no need for any retries?

It'd be nice if there was a proper PMU subsystem, so we could have a
specific driver for each PMU chip, rather than having
open-coded/custom writes to the PMU registers in each board file, but
I guess that's not an issue with this patch specfically.

> diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h

> +/* support the new (FDT-based) image format */ +#define
> CONFIG_FIT

Hmmm. Do the standard Tegra boot scripts in tegra-common-post.h deal
well with FIT? I've tried to avoid FIT usage as much as possible.

[U-Boot] [PATCH 2/2] ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board

[Alban Bedel]

On Wed, 04 Sep 2013 12:05:00 -0600
Stephen Warren <swarren@wwwdotorg.org> wrote:

> On 09/04/2013 07:00 AM, Alban Bedel wrote:
> > Add support for the new Tamonten? NG platform from Avionic Design. 
> > Currently only I2C, MMC, USB and ethernet have been tested.
> 
> (Also CC'ing the Tegra maintainer here)

Ok, I'll add him in the next patch round.

> > diff --git a/board/avionic-design/common/tamonten-ng.c
> > b/board/avionic-design/common/tamonten-ng.c
> >
> > +void pmu_write(uchar reg, uchar data)
> > +{
> > +	int i;
> > +   i2c_set_bus_num(0);	/* PMU is on bus 0 */
> > +	for (i = 0; i < MAX_I2C_RETRY; ++i) {
> > +		if (i2c_write(PMU_I2C_ADDRESS, reg, 1, &data, 1))
> > +			udelay(100);
> > +		else
> > +			break;
> > +	}
> > +}
> 
> Is there really a need to retry the I2C transactions? If so, why do
> they fail? I assume this was just copy/pasted from some other board
> file, and there's no need for any retries?

Yes, that was adapted from the cardhu code and the retry are most
probably useless. I just made a bit more generic function because
we have to set several outputs, on cardhu only one is set.

> It'd be nice if there was a proper PMU subsystem, so we could have a
> specific driver for each PMU chip, rather than having
> open-coded/custom writes to the PMU registers in each board file, but
> I guess that's not an issue with this patch specfically.

A PMU subsystem would be nice, although something that would be
compatible with the Linux regulator and their representation in DT
would be even better.

Otherwise a first step could be to at least create a driver for this
PMU, similar to one for tps6586x. That would at least prevent too much
code duplication between the T30 boards.

> > diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
> >
> > +/* support the new (FDT-based) image format */
> > +#define CONFIG_FIT
> 
> Hmmm. Do the standard Tegra boot scripts in tegra-common-post.h deal
> well with FIT? I've tried to avoid FIT usage as much as possible.

AFAIU it doesn't change anything if you use old images, it just allow
you to also use FIT image. As the build system we use for our platform
produce FIT image we do need support for it. Or should such things,
which are not related to the HW config, be configured in another place?

Alban

[U-Boot] [PATCH 2/2] ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board

[Stephen Warren]

On 09/05/2013 06:46 AM, Alban Bedel wrote:
> On Wed, 04 Sep 2013 12:05:00 -0600
> Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 09/04/2013 07:00 AM, Alban Bedel wrote:
>>> Add support for the new Tamonten? NG platform from Avionic Design. 
>>> Currently only I2C, MMC, USB and ethernet have been tested.
...
>>> diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
>>>
>>> +/* support the new (FDT-based) image format */
>>> +#define CONFIG_FIT
>>
>> Hmmm. Do the standard Tegra boot scripts in tegra-common-post.h deal
>> well with FIT? I've tried to avoid FIT usage as much as possible.
> 
> AFAIU it doesn't change anything if you use old images, it just allow
> you to also use FIT image. As the build system we use for our platform
> produce FIT image we do need support for it. Or should such things,
> which are not related to the HW config, be configured in another place?

No, this file is the right/only place for such things.

[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Thierry Reding]

On Wed, Sep 04, 2013 at 11:59:44AM -0600, Stephen Warren wrote:
> On 09/04/2013 07:00 AM, Alban Bedel wrote:
> > Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.
> 
> CC'ing the Tegra maintainer would be helpful (Tom Warren; I CC'd him here)
> 
> > diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
> 
> > @@ -71,6 +71,7 @@ int tegra_get_chip_sku(void)
> >  		switch (sku_id) {
> >  		case SKU_ID_T33:
> >  		case SKU_ID_T30:
> > +		case SKU_ID_T30MQS:
> 
> Where does the name "T30MQS" come from? Tom, can you verify what we call
> the SKUs internally?

It seems like this is indeed called T30MQS internally. Actually it's
called TM30MQS-A3. I can provide an internal reference if required.

Thierry
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[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Stephen Warren]

On 09/20/2013 06:45 AM, Thierry Reding wrote:
> On Wed, Sep 04, 2013 at 11:59:44AM -0600, Stephen Warren wrote:
>> On 09/04/2013 07:00 AM, Alban Bedel wrote:
>>> Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.
>> 
>> CC'ing the Tegra maintainer would be helpful (Tom Warren; I CC'd
>> him here)
>> 
>>> diff --git a/arch/arm/cpu/tegra-common/ap.c
>>> b/arch/arm/cpu/tegra-common/ap.c
>> 
>>> @@ -71,6 +71,7 @@ int tegra_get_chip_sku(void) switch (sku_id)
>>> { case SKU_ID_T33: case SKU_ID_T30: +		case SKU_ID_T30MQS:
>> 
>> Where does the name "T30MQS" come from? Tom, can you verify what
>> we call the SKUs internally?
> 
> It seems like this is indeed called T30MQS internally. Actually
> it's called TM30MQS-A3. I can provide an internal reference if
> required.

As long as it's been checked, I don't think we need to document it. In
which case, IIRC, the patch was fine.

[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Tom Warren]

Alban,

Were you going to do a V2 of this patchset? 

Tom

> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Friday, September 20, 2013 9:04 AM
> To: Thierry Reding
> Cc: Tom Warren; Alban Bedel; u-boot at lists.denx.de; julian.scheel at avionic-
> design.de
> Subject: Re: [U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30
> 
> On 09/20/2013 06:45 AM, Thierry Reding wrote:
> > On Wed, Sep 04, 2013 at 11:59:44AM -0600, Stephen Warren wrote:
> >> On 09/04/2013 07:00 AM, Alban Bedel wrote:
> >>> Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.
> >>
> >> CC'ing the Tegra maintainer would be helpful (Tom Warren; I CC'd him
> >> here)
> >>
> >>> diff --git a/arch/arm/cpu/tegra-common/ap.c
> >>> b/arch/arm/cpu/tegra-common/ap.c
> >>
> >>> @@ -71,6 +71,7 @@ int tegra_get_chip_sku(void) switch (sku_id)
> >>> { case SKU_ID_T33: case SKU_ID_T30: +		case
> SKU_ID_T30MQS:
> >>
> >> Where does the name "T30MQS" come from? Tom, can you verify what
> we
> >> call the SKUs internally?
> >
> > It seems like this is indeed called T30MQS internally. Actually it's
> > called TM30MQS-A3. I can provide an internal reference if required.
> 
> As long as it's been checked, I don't think we need to document it. In which
> case, IIRC, the patch was fine.
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[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Alban Bedel]

On Fri, 20 Sep 2013 10:57:42 -0700
Tom Warren <TWarren@nvidia.com> wrote:

> Alban,
> 
> Were you going to do a V2 of this patchset? 

I expected to, but up to now there was no concrete change request.
Should I split the PMU stuff to its own mini driver, or is it
acceptable as is for now?

Alban

[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Tom Warren]

It's fine as-is for now. Send a V2 with any changes Stephen, et al requested (if any), and I'll get it into tegra-next when I return from vacation next Monday (assuming it's been Acked).

Thanks,

Tom

> -----Original Message-----
> From: Alban Bedel [mailto:alban.bedel at avionic-design.de]
> Sent: Monday, September 23, 2013 1:52 AM
> To: Tom Warren
> Cc: u-boot at lists.denx.de; julian.scheel at avionic-design.de; Tom Warren;
> Stephen Warren; Thierry Reding (thierry.reding at gmail.com)
> Subject: Re: [U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30
> 
> On Fri, 20 Sep 2013 10:57:42 -0700
> Tom Warren <TWarren@nvidia.com> wrote:
> 
> > Alban,
> >
> > Were you going to do a V2 of this patchset?
> 
> I expected to, but up to now there was no concrete change request.
> Should I split the PMU stuff to its own mini driver, or is it acceptable as is for
> now?
> 
> Alban
--
nvpublic

[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Alban Bedel]

On Mon, 23 Sep 2013 17:23:12 -0700
Tom Warren <TWarren@nvidia.com> wrote:

> It's fine as-is for now. Send a V2 with any changes Stephen, et al requested
> (if any), and I'll get it into tegra-next when I return from vacation
> next Monday (assuming it's been Acked).

What is the status with this patch serie? I'd really like to get it
merged during this window if possible.

Alban

[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Thierry Reding]

On Thu, Oct 17, 2013 at 11:29:06AM +0200, Alban Bedel wrote:
> On Mon, 23 Sep 2013 17:23:12 -0700
> Tom Warren <TWarren@nvidia.com> wrote:
> 
> > It's fine as-is for now. Send a V2 with any changes Stephen, et al requested
> > (if any), and I'll get it into tegra-next when I return from vacation
> > next Monday (assuming it's been Acked).
> 
> What is the status with this patch serie? I'd really like to get it
> merged during this window if possible.

One of the comments was that the SKU is internally listed as TM30MQS-A3,
not TM30MQS. I assume Tom was expecting you to spin a v2 of the patch to
incorporate that change.

Thierry
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[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Stephen Warren]

On 10/17/2013 04:50 AM, Thierry Reding wrote:
> On Thu, Oct 17, 2013 at 11:29:06AM +0200, Alban Bedel wrote:
>> On Mon, 23 Sep 2013 17:23:12 -0700 Tom Warren
>> <TWarren@nvidia.com> wrote:
>> 
>>> It's fine as-is for now. Send a V2 with any changes Stephen, et
>>> al requested (if any), and I'll get it into tegra-next when I
>>> return from vacation next Monday (assuming it's been Acked).
>> 
>> What is the status with this patch serie? I'd really like to get
>> it merged during this window if possible.
> 
> One of the comments was that the SKU is internally listed as
> TM30MQS-A3, not TM30MQS. I assume Tom was expecting you to spin a
> v2 of the patch to incorporate that change.

Are you sure A3 isn't the silicon revision, and hence not part of the
SKU name?

[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Thierry Reding]

On Thu, Oct 17, 2013 at 08:59:22AM -0600, Stephen Warren wrote:
> On 10/17/2013 04:50 AM, Thierry Reding wrote:
> > On Thu, Oct 17, 2013 at 11:29:06AM +0200, Alban Bedel wrote:
> >> On Mon, 23 Sep 2013 17:23:12 -0700 Tom Warren
> >> <TWarren@nvidia.com> wrote:
> >> 
> >>> It's fine as-is for now. Send a V2 with any changes Stephen, et
> >>> al requested (if any), and I'll get it into tegra-next when I
> >>> return from vacation next Monday (assuming it's been Acked).
> >> 
> >> What is the status with this patch serie? I'd really like to get
> >> it merged during this window if possible.
> > 
> > One of the comments was that the SKU is internally listed as
> > TM30MQS-A3, not TM30MQS. I assume Tom was expecting you to spin a
> > v2 of the patch to incorporate that change.
> 
> Are you sure A3 isn't the silicon revision, and hence not part of the
> SKU name?

I'm pretty sure. There's a T30MQS-A2 in the same file I found the other
one and that has SKU 0xb3. Well, I suppose that might not mean anything
regarding the silicon, but at least if we stripped -A3 and -A2, then
we'd end up with two different values for the same SKU name.

Thierry
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[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30

[Tom Warren]

Alban,


On Thu, Oct 17, 2013 at 8:26 AM, Thierry Reding <thierry.reding@gmail.com>wrote:

> On Thu, Oct 17, 2013 at 08:59:22AM -0600, Stephen Warren wrote:
> > On 10/17/2013 04:50 AM, Thierry Reding wrote:
> > > On Thu, Oct 17, 2013 at 11:29:06AM +0200, Alban Bedel wrote:
> > >> On Mon, 23 Sep 2013 17:23:12 -0700 Tom Warren
> > >> <TWarren@nvidia.com> wrote:
> > >>
> > >>> It's fine as-is for now. Send a V2 with any changes Stephen, et
> > >>> al requested (if any), and I'll get it into tegra-next when I
> > >>> return from vacation next Monday (assuming it's been Acked).
> > >>
> > >> What is the status with this patch serie? I'd really like to get
> > >> it merged during this window if possible.
> > >
> > > One of the comments was that the SKU is internally listed as
> > > TM30MQS-A3, not TM30MQS. I assume Tom was expecting you to spin a
> > > v2 of the patch to incorporate that change.
> >
> > Are you sure A3 isn't the silicon revision, and hence not part of the
> > SKU name?
>
> I'm pretty sure. There's a T30MQS-A2 in the same file I found the other
> one and that has SKU 0xb3. Well, I suppose that might not mean anything
> regarding the silicon, but at least if we stripped -A3 and -A2, then
> we'd end up with two different values for the same SKU name.
>
> Thierry
>

Whatever you decide to do here to clear up the SKU naming, I need an
Ack'ed-by patch before I can stick it in u-boot-tegra/next.

Tom