From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 10 Sep 2013 14:14:28 -0700 Subject: [U-Boot] [PATCH] powerpc/p2041: fix I2C controller's offset In-Reply-To: References: <1378800907-28472-1-git-send-email-Shaohui.Xie@freescale.com> Message-ID: <522F8BB4.5000907@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 09/10/2013 02:13 PM, Chris Packham wrote: > Hi Xie, > > On Tue, Sep 10, 2013 at 8:15 PM, Shaohui Xie wrote: >> Without this patch, SPD access will fail which leads to DDR init fail. >> >> Signed-off-by: Shaohui Xie >> --- >> include/configs/P2041RDB.h | 4 ++-- >> 1 files changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h >> index 905bacf..862614b 100644 >> --- a/include/configs/P2041RDB.h >> +++ b/include/configs/P2041RDB.h >> @@ -354,10 +354,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); >> #define CONFIG_SYS_I2C_FSL >> #define CONFIG_SYS_FSL_I2C_SPEED 400000 >> #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F >> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 >> +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 >> #define CONFIG_SYS_FSL_I2C2_SPEED 400000 >> #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F >> -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 >> +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 >> >> /* >> * RapidIO >> -- >> 1.7.0.4 >> > > Yes that appears to fix the problem. Thanks for the quick turn around. > > Tested-by: Chris Packham > Thanks for the feedback. I will take it in u-boot-mpc85xx. York