* [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value
@ 2013-08-29 10:52 Rajeshwari S Shinde
2013-08-29 11:04 ` Rajeshwari Birje
0 siblings, 1 reply; 9+ messages in thread
From: Rajeshwari S Shinde @ 2013-08-29 10:52 UTC (permalink / raw)
To: u-boot
This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL register, we need to use the same output clock value to
calculate the CLKDIV value.
as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
Input parameter to mmc_clk is changed to dwmci_host, since
we need the same to read DWMCI_CLKSEL register.
This improves the read timing values for channel 0 on SMDK5250
from 0.288sec to 0.144sec
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
---
arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++
drivers/mmc/dw_mmc.c | 2 +-
drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++--
include/dwmmc.h | 2 +-
4 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
index b9eca76..f1c8d8a 100644
--- a/arch/arm/include/asm/arch-exynos/dwmmc.h
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -14,6 +14,10 @@
#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+/* CLKSEL Register */
+#define DWMCI_DIVRATIO_BIT 24
+#define DWMCI_DIVRATIO_MASK 0x7
+
#ifdef CONFIG_OF_CONTROL
int exynos_dwmmc_init(const void *blob);
#endif
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index a82ee17..3406bdd 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -224,7 +224,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
* host->bus_hz should be set from user.
*/
if (host->mmc_clk)
- sclk = host->mmc_clk(host->dev_index);
+ sclk = host->mmc_clk(host);
else if (host->bus_hz)
sclk = host->bus_hz;
else {
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 4ef9fec..1ed4afe 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
}
-unsigned int exynos_dwmci_get_clk(int dev_index)
+unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
{
- return get_mmc_clk(dev_index);
+ unsigned long sclk;
+ int8_t clk_div;
+
+ /*
+ * Since SDCLKIN is divided inside controller by the DIVRATIO
+ * value set in the CLKSEL register, we need to use the same output
+ * clock value to calculate the CLKDIV value.
+ * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
+ */
+ clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
+ & DWMCI_DIVRATIO_MASK) + 1;
+ sclk = get_mmc_clk(host->dev_index);
+
+ return sclk / clk_div;
}
/*
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 08ced0b..26b53af 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -138,7 +138,7 @@ struct dwmci_host {
struct mmc *mmc;
void (*clksel)(struct dwmci_host *host);
- unsigned int (*mmc_clk)(int dev_index);
+ unsigned int (*mmc_clk)(struct dwmci_host *host);
};
struct dwmci_idmac {
--
1.7.12.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value
2013-08-29 10:52 [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value Rajeshwari S Shinde
@ 2013-08-29 11:04 ` Rajeshwari Birje
2013-08-29 15:01 ` Simon Glass
2013-09-11 5:28 ` Rajeshwari Birje
0 siblings, 2 replies; 9+ messages in thread
From: Rajeshwari Birje @ 2013-08-29 11:04 UTC (permalink / raw)
To: u-boot
CCing the MMC Maintainer.
On Thu, Aug 29, 2013 at 4:22 PM, Rajeshwari S Shinde
<rajeshwari.s@samsung.com> wrote:
> This patch corrects the divider value written to CLKDIV register.
> Since SDCLKIN is divided inside controller by the DIVRATIO value set
> in the CLKSEL register, we need to use the same output clock value to
> calculate the CLKDIV value.
> as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
>
> Input parameter to mmc_clk is changed to dwmci_host, since
> we need the same to read DWMCI_CLKSEL register.
>
> This improves the read timing values for channel 0 on SMDK5250
> from 0.288sec to 0.144sec
>
> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> ---
> arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++
> drivers/mmc/dw_mmc.c | 2 +-
> drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++--
> include/dwmmc.h | 2 +-
> 4 files changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
> index b9eca76..f1c8d8a 100644
> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h
> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
> @@ -14,6 +14,10 @@
> #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
> #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>
> +/* CLKSEL Register */
> +#define DWMCI_DIVRATIO_BIT 24
> +#define DWMCI_DIVRATIO_MASK 0x7
> +
> #ifdef CONFIG_OF_CONTROL
> int exynos_dwmmc_init(const void *blob);
> #endif
> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
> index a82ee17..3406bdd 100644
> --- a/drivers/mmc/dw_mmc.c
> +++ b/drivers/mmc/dw_mmc.c
> @@ -224,7 +224,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
> * host->bus_hz should be set from user.
> */
> if (host->mmc_clk)
> - sclk = host->mmc_clk(host->dev_index);
> + sclk = host->mmc_clk(host);
> else if (host->bus_hz)
> sclk = host->bus_hz;
> else {
> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
> index 4ef9fec..1ed4afe 100644
> --- a/drivers/mmc/exynos_dw_mmc.c
> +++ b/drivers/mmc/exynos_dw_mmc.c
> @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
> dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
> }
>
> -unsigned int exynos_dwmci_get_clk(int dev_index)
> +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
> {
> - return get_mmc_clk(dev_index);
> + unsigned long sclk;
> + int8_t clk_div;
> +
> + /*
> + * Since SDCLKIN is divided inside controller by the DIVRATIO
> + * value set in the CLKSEL register, we need to use the same output
> + * clock value to calculate the CLKDIV value.
> + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
> + */
> + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
> + & DWMCI_DIVRATIO_MASK) + 1;
> + sclk = get_mmc_clk(host->dev_index);
> +
> + return sclk / clk_div;
> }
>
> /*
> diff --git a/include/dwmmc.h b/include/dwmmc.h
> index 08ced0b..26b53af 100644
> --- a/include/dwmmc.h
> +++ b/include/dwmmc.h
> @@ -138,7 +138,7 @@ struct dwmci_host {
> struct mmc *mmc;
>
> void (*clksel)(struct dwmci_host *host);
> - unsigned int (*mmc_clk)(int dev_index);
> + unsigned int (*mmc_clk)(struct dwmci_host *host);
> };
>
> struct dwmci_idmac {
> --
> 1.7.12.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value
2013-08-29 11:04 ` Rajeshwari Birje
@ 2013-08-29 15:01 ` Simon Glass
2013-09-02 5:18 ` Rajeshwari Birje
2013-09-11 5:28 ` Rajeshwari Birje
1 sibling, 1 reply; 9+ messages in thread
From: Simon Glass @ 2013-08-29 15:01 UTC (permalink / raw)
To: u-boot
On Thu, Aug 29, 2013 at 5:04 AM, Rajeshwari Birje
<rajeshwari.birje@gmail.com> wrote:
> CCing the MMC Maintainer.
>
> On Thu, Aug 29, 2013 at 4:22 PM, Rajeshwari S Shinde
> <rajeshwari.s@samsung.com> wrote:
>> This patch corrects the divider value written to CLKDIV register.
>> Since SDCLKIN is divided inside controller by the DIVRATIO value set
>> in the CLKSEL register, we need to use the same output clock value to
>> calculate the CLKDIV value.
>> as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
>>
>> Input parameter to mmc_clk is changed to dwmci_host, since
>> we need the same to read DWMCI_CLKSEL register.
>>
>> This improves the read timing values for channel 0 on SMDK5250
>> from 0.288sec to 0.144sec
>>
>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>> ---
>> arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++
>> drivers/mmc/dw_mmc.c | 2 +-
>> drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++--
>> include/dwmmc.h | 2 +-
>> 4 files changed, 21 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
>> index b9eca76..f1c8d8a 100644
>> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h
>> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
>> @@ -14,6 +14,10 @@
>> #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
>> #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>>
>> +/* CLKSEL Register */
>> +#define DWMCI_DIVRATIO_BIT 24
>> +#define DWMCI_DIVRATIO_MASK 0x7
>> +
>> #ifdef CONFIG_OF_CONTROL
>> int exynos_dwmmc_init(const void *blob);
>> #endif
>> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
>> index a82ee17..3406bdd 100644
>> --- a/drivers/mmc/dw_mmc.c
>> +++ b/drivers/mmc/dw_mmc.c
>> @@ -224,7 +224,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
>> * host->bus_hz should be set from user.
>> */
>> if (host->mmc_clk)
>> - sclk = host->mmc_clk(host->dev_index);
>> + sclk = host->mmc_clk(host);
Do you need to change dw_mmc_simple.c as well?
Regards,
Simon
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value
2013-08-29 15:01 ` Simon Glass
@ 2013-09-02 5:18 ` Rajeshwari Birje
0 siblings, 0 replies; 9+ messages in thread
From: Rajeshwari Birje @ 2013-09-02 5:18 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Thu, Aug 29, 2013 at 8:31 PM, Simon Glass <sjg@chromium.org> wrote:
> On Thu, Aug 29, 2013 at 5:04 AM, Rajeshwari Birje
> <rajeshwari.birje@gmail.com> wrote:
>> CCing the MMC Maintainer.
>>
>> On Thu, Aug 29, 2013 at 4:22 PM, Rajeshwari S Shinde
>> <rajeshwari.s@samsung.com> wrote:
>>> This patch corrects the divider value written to CLKDIV register.
>>> Since SDCLKIN is divided inside controller by the DIVRATIO value set
>>> in the CLKSEL register, we need to use the same output clock value to
>>> calculate the CLKDIV value.
>>> as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
>>>
>>> Input parameter to mmc_clk is changed to dwmci_host, since
>>> we need the same to read DWMCI_CLKSEL register.
>>>
>>> This improves the read timing values for channel 0 on SMDK5250
>>> from 0.288sec to 0.144sec
>>>
>>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>>> ---
>>> arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++
>>> drivers/mmc/dw_mmc.c | 2 +-
>>> drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++--
>>> include/dwmmc.h | 2 +-
>>> 4 files changed, 21 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>> index b9eca76..f1c8d8a 100644
>>> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h
>>> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>> @@ -14,6 +14,10 @@
>>> #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
>>> #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>>>
>>> +/* CLKSEL Register */
>>> +#define DWMCI_DIVRATIO_BIT 24
>>> +#define DWMCI_DIVRATIO_MASK 0x7
>>> +
>>> #ifdef CONFIG_OF_CONTROL
>>> int exynos_dwmmc_init(const void *blob);
>>> #endif
>>> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
>>> index a82ee17..3406bdd 100644
>>> --- a/drivers/mmc/dw_mmc.c
>>> +++ b/drivers/mmc/dw_mmc.c
>>> @@ -224,7 +224,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
>>> * host->bus_hz should be set from user.
>>> */
>>> if (host->mmc_clk)
>>> - sclk = host->mmc_clk(host->dev_index);
>>> + sclk = host->mmc_clk(host);
>
> Do you need to change dw_mmc_simple.c as well?
Not able to find any file dw_mmc_simple.c.
Please do let me know if I need to check any file getting effected.
>
> Regards,
> Simon
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value
2013-08-29 11:04 ` Rajeshwari Birje
2013-08-29 15:01 ` Simon Glass
@ 2013-09-11 5:28 ` Rajeshwari Birje
2013-09-11 6:01 ` Jaehoon Chung
1 sibling, 1 reply; 9+ messages in thread
From: Rajeshwari Birje @ 2013-09-11 5:28 UTC (permalink / raw)
To: u-boot
Hi All,
Please do let me know if any comments on the same.
Regards,
Rajeshwari Shinde.
On Thu, Aug 29, 2013 at 4:34 PM, Rajeshwari Birje
<rajeshwari.birje@gmail.com> wrote:
> CCing the MMC Maintainer.
>
> On Thu, Aug 29, 2013 at 4:22 PM, Rajeshwari S Shinde
> <rajeshwari.s@samsung.com> wrote:
>> This patch corrects the divider value written to CLKDIV register.
>> Since SDCLKIN is divided inside controller by the DIVRATIO value set
>> in the CLKSEL register, we need to use the same output clock value to
>> calculate the CLKDIV value.
>> as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
>>
>> Input parameter to mmc_clk is changed to dwmci_host, since
>> we need the same to read DWMCI_CLKSEL register.
>>
>> This improves the read timing values for channel 0 on SMDK5250
>> from 0.288sec to 0.144sec
>>
>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>> ---
>> arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++
>> drivers/mmc/dw_mmc.c | 2 +-
>> drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++--
>> include/dwmmc.h | 2 +-
>> 4 files changed, 21 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
>> index b9eca76..f1c8d8a 100644
>> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h
>> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
>> @@ -14,6 +14,10 @@
>> #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
>> #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>>
>> +/* CLKSEL Register */
>> +#define DWMCI_DIVRATIO_BIT 24
>> +#define DWMCI_DIVRATIO_MASK 0x7
>> +
>> #ifdef CONFIG_OF_CONTROL
>> int exynos_dwmmc_init(const void *blob);
>> #endif
>> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
>> index a82ee17..3406bdd 100644
>> --- a/drivers/mmc/dw_mmc.c
>> +++ b/drivers/mmc/dw_mmc.c
>> @@ -224,7 +224,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
>> * host->bus_hz should be set from user.
>> */
>> if (host->mmc_clk)
>> - sclk = host->mmc_clk(host->dev_index);
>> + sclk = host->mmc_clk(host);
>> else if (host->bus_hz)
>> sclk = host->bus_hz;
>> else {
>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
>> index 4ef9fec..1ed4afe 100644
>> --- a/drivers/mmc/exynos_dw_mmc.c
>> +++ b/drivers/mmc/exynos_dw_mmc.c
>> @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
>> dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
>> }
>>
>> -unsigned int exynos_dwmci_get_clk(int dev_index)
>> +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
>> {
>> - return get_mmc_clk(dev_index);
>> + unsigned long sclk;
>> + int8_t clk_div;
>> +
>> + /*
>> + * Since SDCLKIN is divided inside controller by the DIVRATIO
>> + * value set in the CLKSEL register, we need to use the same output
>> + * clock value to calculate the CLKDIV value.
>> + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
>> + */
>> + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
>> + & DWMCI_DIVRATIO_MASK) + 1;
>> + sclk = get_mmc_clk(host->dev_index);
>> +
>> + return sclk / clk_div;
>> }
>>
>> /*
>> diff --git a/include/dwmmc.h b/include/dwmmc.h
>> index 08ced0b..26b53af 100644
>> --- a/include/dwmmc.h
>> +++ b/include/dwmmc.h
>> @@ -138,7 +138,7 @@ struct dwmci_host {
>> struct mmc *mmc;
>>
>> void (*clksel)(struct dwmci_host *host);
>> - unsigned int (*mmc_clk)(int dev_index);
>> + unsigned int (*mmc_clk)(struct dwmci_host *host);
>> };
>>
>> struct dwmci_idmac {
>> --
>> 1.7.12.4
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>
>
>
> --
> Regards,
> Rajeshwari Shinde
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value
2013-09-11 5:28 ` Rajeshwari Birje
@ 2013-09-11 6:01 ` Jaehoon Chung
2013-09-11 13:25 ` Rajeshwari Birje
0 siblings, 1 reply; 9+ messages in thread
From: Jaehoon Chung @ 2013-09-11 6:01 UTC (permalink / raw)
To: u-boot
On 09/11/2013 02:28 PM, Rajeshwari Birje wrote:
> Hi All,
>
> Please do let me know if any comments on the same.
>
> Regards,
> Rajeshwari Shinde.
>
> On Thu, Aug 29, 2013 at 4:34 PM, Rajeshwari Birje
> <rajeshwari.birje@gmail.com> wrote:
>> CCing the MMC Maintainer.
>>
>> On Thu, Aug 29, 2013 at 4:22 PM, Rajeshwari S Shinde
>> <rajeshwari.s@samsung.com> wrote:
>>> This patch corrects the divider value written to CLKDIV register.
>>> Since SDCLKIN is divided inside controller by the DIVRATIO value set
>>> in the CLKSEL register, we need to use the same output clock value to
>>> calculate the CLKDIV value.
>>> as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
>>>
>>> Input parameter to mmc_clk is changed to dwmci_host, since
>>> we need the same to read DWMCI_CLKSEL register.
>>>
>>> This improves the read timing values for channel 0 on SMDK5250
>>> from 0.288sec to 0.144sec
>>>
>>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>>> ---
>>> arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++
>>> drivers/mmc/dw_mmc.c | 2 +-
>>> drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++--
>>> include/dwmmc.h | 2 +-
>>> 4 files changed, 21 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>> index b9eca76..f1c8d8a 100644
>>> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h
>>> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>> @@ -14,6 +14,10 @@
>>> #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
>>> #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>>>
>>> +/* CLKSEL Register */
>>> +#define DWMCI_DIVRATIO_BIT 24
>>> +#define DWMCI_DIVRATIO_MASK 0x7
>>> +
>>> #ifdef CONFIG_OF_CONTROL
>>> int exynos_dwmmc_init(const void *blob);
>>> #endif
>>> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
>>> index a82ee17..3406bdd 100644
>>> --- a/drivers/mmc/dw_mmc.c
>>> +++ b/drivers/mmc/dw_mmc.c
>>> @@ -224,7 +224,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
>>> * host->bus_hz should be set from user.
>>> */
>>> if (host->mmc_clk)
>>> - sclk = host->mmc_clk(host->dev_index);
>>> + sclk = host->mmc_clk(host);
>>> else if (host->bus_hz)
>>> sclk = host->bus_hz;
>>> else {
>>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
>>> index 4ef9fec..1ed4afe 100644
>>> --- a/drivers/mmc/exynos_dw_mmc.c
>>> +++ b/drivers/mmc/exynos_dw_mmc.c
>>> @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
>>> dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
>>> }
>>>
>>> -unsigned int exynos_dwmci_get_clk(int dev_index)
>>> +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
>>> {
>>> - return get_mmc_clk(dev_index);
>>> + unsigned long sclk;
>>> + int8_t clk_div;
>>> +
>>> + /*
>>> + * Since SDCLKIN is divided inside controller by the DIVRATIO
>>> + * value set in the CLKSEL register, we need to use the same output
>>> + * clock value to calculate the CLKDIV value.
>>> + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
>>> + */
>>> + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
>>> + & DWMCI_DIVRATIO_MASK) + 1;
I known DIVRATIO is only exynos5 feature..
And If clk_div is set to 0, then clk_phase/clk_strength is also set to 0.
And I think we can fixed this problem into exynos_dwmci_add_port.
Best Regards,
Jaehoon Chung
>>> + sclk = get_mmc_clk(host->dev_index);
>>> +
>>> + return sclk / clk_div;
>>> }
>>>
>>> /*
>>> diff --git a/include/dwmmc.h b/include/dwmmc.h
>>> index 08ced0b..26b53af 100644
>>> --- a/include/dwmmc.h
>>> +++ b/include/dwmmc.h
>>> @@ -138,7 +138,7 @@ struct dwmci_host {
>>> struct mmc *mmc;
>>>
>>> void (*clksel)(struct dwmci_host *host);
>>> - unsigned int (*mmc_clk)(int dev_index);
>>> + unsigned int (*mmc_clk)(struct dwmci_host *host);
>>> };
>>>
>>> struct dwmci_idmac {
>>> --
>>> 1.7.12.4
>>>
>>> _______________________________________________
>>> U-Boot mailing list
>>> U-Boot at lists.denx.de
>>> http://lists.denx.de/mailman/listinfo/u-boot
>>
>>
>>
>> --
>> Regards,
>> Rajeshwari Shinde
>
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value
2013-09-11 6:01 ` Jaehoon Chung
@ 2013-09-11 13:25 ` Rajeshwari Birje
2013-09-17 15:27 ` Pantelis Antoniou
0 siblings, 1 reply; 9+ messages in thread
From: Rajeshwari Birje @ 2013-09-11 13:25 UTC (permalink / raw)
To: u-boot
Hi Jaehoon Chung,
Thank you for comments,
On Wed, Sep 11, 2013 at 11:31 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> On 09/11/2013 02:28 PM, Rajeshwari Birje wrote:
>> Hi All,
>>
>> Please do let me know if any comments on the same.
>>
>> Regards,
>> Rajeshwari Shinde.
>>
>> On Thu, Aug 29, 2013 at 4:34 PM, Rajeshwari Birje
>> <rajeshwari.birje@gmail.com> wrote:
>>> CCing the MMC Maintainer.
>>>
>>> On Thu, Aug 29, 2013 at 4:22 PM, Rajeshwari S Shinde
>>> <rajeshwari.s@samsung.com> wrote:
>>>> This patch corrects the divider value written to CLKDIV register.
>>>> Since SDCLKIN is divided inside controller by the DIVRATIO value set
>>>> in the CLKSEL register, we need to use the same output clock value to
>>>> calculate the CLKDIV value.
>>>> as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
>>>>
>>>> Input parameter to mmc_clk is changed to dwmci_host, since
>>>> we need the same to read DWMCI_CLKSEL register.
>>>>
>>>> This improves the read timing values for channel 0 on SMDK5250
>>>> from 0.288sec to 0.144sec
>>>>
>>>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>>>> ---
>>>> arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++
>>>> drivers/mmc/dw_mmc.c | 2 +-
>>>> drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++--
>>>> include/dwmmc.h | 2 +-
>>>> 4 files changed, 21 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>>> index b9eca76..f1c8d8a 100644
>>>> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h
>>>> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>>> @@ -14,6 +14,10 @@
>>>> #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
>>>> #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>>>>
>>>> +/* CLKSEL Register */
>>>> +#define DWMCI_DIVRATIO_BIT 24
>>>> +#define DWMCI_DIVRATIO_MASK 0x7
>>>> +
>>>> #ifdef CONFIG_OF_CONTROL
>>>> int exynos_dwmmc_init(const void *blob);
>>>> #endif
>>>> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
>>>> index a82ee17..3406bdd 100644
>>>> --- a/drivers/mmc/dw_mmc.c
>>>> +++ b/drivers/mmc/dw_mmc.c
>>>> @@ -224,7 +224,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
>>>> * host->bus_hz should be set from user.
>>>> */
>>>> if (host->mmc_clk)
>>>> - sclk = host->mmc_clk(host->dev_index);
>>>> + sclk = host->mmc_clk(host);
>>>> else if (host->bus_hz)
>>>> sclk = host->bus_hz;
>>>> else {
>>>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
>>>> index 4ef9fec..1ed4afe 100644
>>>> --- a/drivers/mmc/exynos_dw_mmc.c
>>>> +++ b/drivers/mmc/exynos_dw_mmc.c
>>>> @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
>>>> dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
>>>> }
>>>>
>>>> -unsigned int exynos_dwmci_get_clk(int dev_index)
>>>> +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
>>>> {
>>>> - return get_mmc_clk(dev_index);
>>>> + unsigned long sclk;
>>>> + int8_t clk_div;
>>>> +
>>>> + /*
>>>> + * Since SDCLKIN is divided inside controller by the DIVRATIO
>>>> + * value set in the CLKSEL register, we need to use the same output
>>>> + * clock value to calculate the CLKDIV value.
>>>> + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
>>>> + */
>>>> + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
>>>> + & DWMCI_DIVRATIO_MASK) + 1;
> I known DIVRATIO is only exynos5 feature..
> And If clk_div is set to 0, then clk_phase/clk_strength is also set to 0.
>
> And I think we can fixed this problem into exynos_dwmci_add_port.
>
> Best Regards,
> Jaehoon Chung
during the dwmci_setup_bus we call for mmc_clk, this is where the
get_mmc_clk(host->dev_index) retruns you the parent clock but since
we need the output of mux " cclk_in",
added in the exynos_dwmci_get_clk.
--
Regards,
Rajeshwari Shinde
>
>>>> + sclk = get_mmc_clk(host->dev_index);
>>>> +
>>>> + return sclk / clk_div;
>>>> }
>>>>
>>>> /*
>>>> diff --git a/include/dwmmc.h b/include/dwmmc.h
>>>> index 08ced0b..26b53af 100644
>>>> --- a/include/dwmmc.h
>>>> +++ b/include/dwmmc.h
>>>> @@ -138,7 +138,7 @@ struct dwmci_host {
>>>> struct mmc *mmc;
>>>>
>>>> void (*clksel)(struct dwmci_host *host);
>>>> - unsigned int (*mmc_clk)(int dev_index);
>>>> + unsigned int (*mmc_clk)(struct dwmci_host *host);
>>>> };
>>>>
>>>> struct dwmci_idmac {
>>>> --
>>>> 1.7.12.4
>>>>
>>>> _______________________________________________
>>>> U-Boot mailing list
>>>> U-Boot at lists.denx.de
>>>> http://lists.denx.de/mailman/listinfo/u-boot
>>>
>>>
>>>
>>> --
>>> Regards,
>>> Rajeshwari Shinde
>>
>>
>>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value
2013-09-11 13:25 ` Rajeshwari Birje
@ 2013-09-17 15:27 ` Pantelis Antoniou
2013-09-27 4:55 ` Rajeshwari Birje
0 siblings, 1 reply; 9+ messages in thread
From: Pantelis Antoniou @ 2013-09-17 15:27 UTC (permalink / raw)
To: u-boot
Hi Rajesh,
I guess we wait for an updated patch here?
Regards
-- Pantelis
On Sep 11, 2013, at 4:25 PM, Rajeshwari Birje wrote:
> Hi Jaehoon Chung,
>
> Thank you for comments,
>
>
>
> On Wed, Sep 11, 2013 at 11:31 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
>> On 09/11/2013 02:28 PM, Rajeshwari Birje wrote:
>>> Hi All,
>>>
>>> Please do let me know if any comments on the same.
>>>
>>> Regards,
>>> Rajeshwari Shinde.
>>>
>>> On Thu, Aug 29, 2013 at 4:34 PM, Rajeshwari Birje
>>> <rajeshwari.birje@gmail.com> wrote:
>>>> CCing the MMC Maintainer.
>>>>
>>>> On Thu, Aug 29, 2013 at 4:22 PM, Rajeshwari S Shinde
>>>> <rajeshwari.s@samsung.com> wrote:
>>>>> This patch corrects the divider value written to CLKDIV register.
>>>>> Since SDCLKIN is divided inside controller by the DIVRATIO value set
>>>>> in the CLKSEL register, we need to use the same output clock value to
>>>>> calculate the CLKDIV value.
>>>>> as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
>>>>>
>>>>> Input parameter to mmc_clk is changed to dwmci_host, since
>>>>> we need the same to read DWMCI_CLKSEL register.
>>>>>
>>>>> This improves the read timing values for channel 0 on SMDK5250
>>>>> from 0.288sec to 0.144sec
>>>>>
>>>>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>>>>> ---
>>>>> arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++
>>>>> drivers/mmc/dw_mmc.c | 2 +-
>>>>> drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++--
>>>>> include/dwmmc.h | 2 +-
>>>>> 4 files changed, 21 insertions(+), 4 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>>>> index b9eca76..f1c8d8a 100644
>>>>> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h
>>>>> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>>>> @@ -14,6 +14,10 @@
>>>>> #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
>>>>> #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>>>>>
>>>>> +/* CLKSEL Register */
>>>>> +#define DWMCI_DIVRATIO_BIT 24
>>>>> +#define DWMCI_DIVRATIO_MASK 0x7
>>>>> +
>>>>> #ifdef CONFIG_OF_CONTROL
>>>>> int exynos_dwmmc_init(const void *blob);
>>>>> #endif
>>>>> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
>>>>> index a82ee17..3406bdd 100644
>>>>> --- a/drivers/mmc/dw_mmc.c
>>>>> +++ b/drivers/mmc/dw_mmc.c
>>>>> @@ -224,7 +224,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
>>>>> * host->bus_hz should be set from user.
>>>>> */
>>>>> if (host->mmc_clk)
>>>>> - sclk = host->mmc_clk(host->dev_index);
>>>>> + sclk = host->mmc_clk(host);
>>>>> else if (host->bus_hz)
>>>>> sclk = host->bus_hz;
>>>>> else {
>>>>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
>>>>> index 4ef9fec..1ed4afe 100644
>>>>> --- a/drivers/mmc/exynos_dw_mmc.c
>>>>> +++ b/drivers/mmc/exynos_dw_mmc.c
>>>>> @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
>>>>> dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
>>>>> }
>>>>>
>>>>> -unsigned int exynos_dwmci_get_clk(int dev_index)
>>>>> +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
>>>>> {
>>>>> - return get_mmc_clk(dev_index);
>>>>> + unsigned long sclk;
>>>>> + int8_t clk_div;
>>>>> +
>>>>> + /*
>>>>> + * Since SDCLKIN is divided inside controller by the DIVRATIO
>>>>> + * value set in the CLKSEL register, we need to use the same output
>>>>> + * clock value to calculate the CLKDIV value.
>>>>> + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
>>>>> + */
>>>>> + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
>>>>> + & DWMCI_DIVRATIO_MASK) + 1;
>> I known DIVRATIO is only exynos5 feature..
>> And If clk_div is set to 0, then clk_phase/clk_strength is also set to 0.
>>
>> And I think we can fixed this problem into exynos_dwmci_add_port.
>>
>> Best Regards,
>> Jaehoon Chung
>
> during the dwmci_setup_bus we call for mmc_clk, this is where the
> get_mmc_clk(host->dev_index) retruns you the parent clock but since
> we need the output of mux " cclk_in",
> added in the exynos_dwmci_get_clk.
> --
> Regards,
> Rajeshwari Shinde
>>
>>>>> + sclk = get_mmc_clk(host->dev_index);
>>>>> +
>>>>> + return sclk / clk_div;
>>>>> }
>>>>>
>>>>> /*
>>>>> diff --git a/include/dwmmc.h b/include/dwmmc.h
>>>>> index 08ced0b..26b53af 100644
>>>>> --- a/include/dwmmc.h
>>>>> +++ b/include/dwmmc.h
>>>>> @@ -138,7 +138,7 @@ struct dwmci_host {
>>>>> struct mmc *mmc;
>>>>>
>>>>> void (*clksel)(struct dwmci_host *host);
>>>>> - unsigned int (*mmc_clk)(int dev_index);
>>>>> + unsigned int (*mmc_clk)(struct dwmci_host *host);
>>>>> };
>>>>>
>>>>> struct dwmci_idmac {
>>>>> --
>>>>> 1.7.12.4
>>>>>
>>>>> _______________________________________________
>>>>> U-Boot mailing list
>>>>> U-Boot at lists.denx.de
>>>>> http://lists.denx.de/mailman/listinfo/u-boot
>>>>
>>>>
>>>>
>>>> --
>>>> Regards,
>>>> Rajeshwari Shinde
>>>
>>>
>>>
>>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value
2013-09-17 15:27 ` Pantelis Antoniou
@ 2013-09-27 4:55 ` Rajeshwari Birje
0 siblings, 0 replies; 9+ messages in thread
From: Rajeshwari Birje @ 2013-09-27 4:55 UTC (permalink / raw)
To: u-boot
Hi Pantelis,
If Jaehoon Chung has no comments we can go with the same patch.
@Jaehoon: do let me know if any better suggestions.
Regards,
Rajeshwari
On Tue, Sep 17, 2013 at 8:57 PM, Pantelis Antoniou
<panto@antoniou-consulting.com> wrote:
> Hi Rajesh,
>
> I guess we wait for an updated patch here?
>
> Regards
>
> -- Pantelis
>
> On Sep 11, 2013, at 4:25 PM, Rajeshwari Birje wrote:
>
>> Hi Jaehoon Chung,
>>
>> Thank you for comments,
>>
>>
>>
>> On Wed, Sep 11, 2013 at 11:31 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
>>> On 09/11/2013 02:28 PM, Rajeshwari Birje wrote:
>>>> Hi All,
>>>>
>>>> Please do let me know if any comments on the same.
>>>>
>>>> Regards,
>>>> Rajeshwari Shinde.
>>>>
>>>> On Thu, Aug 29, 2013 at 4:34 PM, Rajeshwari Birje
>>>> <rajeshwari.birje@gmail.com> wrote:
>>>>> CCing the MMC Maintainer.
>>>>>
>>>>> On Thu, Aug 29, 2013 at 4:22 PM, Rajeshwari S Shinde
>>>>> <rajeshwari.s@samsung.com> wrote:
>>>>>> This patch corrects the divider value written to CLKDIV register.
>>>>>> Since SDCLKIN is divided inside controller by the DIVRATIO value set
>>>>>> in the CLKSEL register, we need to use the same output clock value to
>>>>>> calculate the CLKDIV value.
>>>>>> as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
>>>>>>
>>>>>> Input parameter to mmc_clk is changed to dwmci_host, since
>>>>>> we need the same to read DWMCI_CLKSEL register.
>>>>>>
>>>>>> This improves the read timing values for channel 0 on SMDK5250
>>>>>> from 0.288sec to 0.144sec
>>>>>>
>>>>>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>>>>>> ---
>>>>>> arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++
>>>>>> drivers/mmc/dw_mmc.c | 2 +-
>>>>>> drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++--
>>>>>> include/dwmmc.h | 2 +-
>>>>>> 4 files changed, 21 insertions(+), 4 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>>>>> index b9eca76..f1c8d8a 100644
>>>>>> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h
>>>>>> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>>>>> @@ -14,6 +14,10 @@
>>>>>> #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
>>>>>> #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>>>>>>
>>>>>> +/* CLKSEL Register */
>>>>>> +#define DWMCI_DIVRATIO_BIT 24
>>>>>> +#define DWMCI_DIVRATIO_MASK 0x7
>>>>>> +
>>>>>> #ifdef CONFIG_OF_CONTROL
>>>>>> int exynos_dwmmc_init(const void *blob);
>>>>>> #endif
>>>>>> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
>>>>>> index a82ee17..3406bdd 100644
>>>>>> --- a/drivers/mmc/dw_mmc.c
>>>>>> +++ b/drivers/mmc/dw_mmc.c
>>>>>> @@ -224,7 +224,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
>>>>>> * host->bus_hz should be set from user.
>>>>>> */
>>>>>> if (host->mmc_clk)
>>>>>> - sclk = host->mmc_clk(host->dev_index);
>>>>>> + sclk = host->mmc_clk(host);
>>>>>> else if (host->bus_hz)
>>>>>> sclk = host->bus_hz;
>>>>>> else {
>>>>>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
>>>>>> index 4ef9fec..1ed4afe 100644
>>>>>> --- a/drivers/mmc/exynos_dw_mmc.c
>>>>>> +++ b/drivers/mmc/exynos_dw_mmc.c
>>>>>> @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
>>>>>> dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
>>>>>> }
>>>>>>
>>>>>> -unsigned int exynos_dwmci_get_clk(int dev_index)
>>>>>> +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
>>>>>> {
>>>>>> - return get_mmc_clk(dev_index);
>>>>>> + unsigned long sclk;
>>>>>> + int8_t clk_div;
>>>>>> +
>>>>>> + /*
>>>>>> + * Since SDCLKIN is divided inside controller by the DIVRATIO
>>>>>> + * value set in the CLKSEL register, we need to use the same output
>>>>>> + * clock value to calculate the CLKDIV value.
>>>>>> + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
>>>>>> + */
>>>>>> + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
>>>>>> + & DWMCI_DIVRATIO_MASK) + 1;
>>> I known DIVRATIO is only exynos5 feature..
>>> And If clk_div is set to 0, then clk_phase/clk_strength is also set to 0.
>>>
>>> And I think we can fixed this problem into exynos_dwmci_add_port.
>>>
>>> Best Regards,
>>> Jaehoon Chung
>>
>> during the dwmci_setup_bus we call for mmc_clk, this is where the
>> get_mmc_clk(host->dev_index) retruns you the parent clock but since
>> we need the output of mux " cclk_in",
>> added in the exynos_dwmci_get_clk.
>> --
>> Regards,
>> Rajeshwari Shinde
>>>
>>>>>> + sclk = get_mmc_clk(host->dev_index);
>>>>>> +
>>>>>> + return sclk / clk_div;
>>>>>> }
>>>>>>
>>>>>> /*
>>>>>> diff --git a/include/dwmmc.h b/include/dwmmc.h
>>>>>> index 08ced0b..26b53af 100644
>>>>>> --- a/include/dwmmc.h
>>>>>> +++ b/include/dwmmc.h
>>>>>> @@ -138,7 +138,7 @@ struct dwmci_host {
>>>>>> struct mmc *mmc;
>>>>>>
>>>>>> void (*clksel)(struct dwmci_host *host);
>>>>>> - unsigned int (*mmc_clk)(int dev_index);
>>>>>> + unsigned int (*mmc_clk)(struct dwmci_host *host);
>>>>>> };
>>>>>>
>>>>>> struct dwmci_idmac {
>>>>>> --
>>>>>> 1.7.12.4
>>>>>>
>>>>>> _______________________________________________
>>>>>> U-Boot mailing list
>>>>>> U-Boot at lists.denx.de
>>>>>> http://lists.denx.de/mailman/listinfo/u-boot
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> Regards,
>>>>> Rajeshwari Shinde
>>>>
>>>>
>>>>
>>>
>
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2013-09-27 4:55 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-08-29 10:52 [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value Rajeshwari S Shinde
2013-08-29 11:04 ` Rajeshwari Birje
2013-08-29 15:01 ` Simon Glass
2013-09-02 5:18 ` Rajeshwari Birje
2013-09-11 5:28 ` Rajeshwari Birje
2013-09-11 6:01 ` Jaehoon Chung
2013-09-11 13:25 ` Rajeshwari Birje
2013-09-17 15:27 ` Pantelis Antoniou
2013-09-27 4:55 ` Rajeshwari Birje
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