[U-Boot] [PATCH 3/3] arm: rmobile: Add support lager board

Nobuhiro Iwamatsu
2013-08-22T04:23:28Z

The lager board has R8A7790, 2GB DDR3-SDRAM, USB,
Ethernet, and more.

This patch supports the following functions:
- DDR3-SDRAM
- SCIF
- QSPI
- Ethernet

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
---
arch/arm/include/asm/mach-types.h | 13 +
board/renesas/lager/Makefile | 35 ++
board/renesas/lager/lager.c | 357 ++++++++++++
board/renesas/lager/qos.c | 1112 +++++++++++++++++++++++++++++++++++++
board/renesas/lager/qos.h | 12 +
boards.cfg | 2 +
include/configs/lager.h | 186 +++++++
7 files changed, 1717 insertions(+)
create mode 100644 board/renesas/lager/Makefile
create mode 100644 board/renesas/lager/lager.c
create mode 100644 board/renesas/lager/qos.c
create mode 100644 board/renesas/lager/qos.h
create mode 100644 include/configs/lager.h

diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 440b041..67b88ad 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1106,6 +1106,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_OMAP5_SEVM 3777
#define MACH_TYPE_ARMADILLO_800EVA 3863
#define MACH_TYPE_KZM9G 4140
+#define MACH_TYPE_LAGER 4538

#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -14235,6 +14236,18 @@ extern unsigned int __machine_arch_type;
# define machine_is_kzm9g() (0)
#endif

+#ifdef CONFIG_MACH_LAGER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LAGER
+# endif
+# define machine_is_lager() (machine_arch_type == MACH_TYPE_LAGER)
+#else
+# define machine_is_lager() (0)
+#endif
+
/*
* These have not yet been registered
*/
diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile
new file mode 100644
index 0000000..acf2ebe
--- /dev/null
+++ b/board/renesas/lager/Makefile
@@ -0,0 +1,35 @@
+#
+# board/renesas/lager/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := lager.o qos.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
new file mode 100644
index 0000000..ba923d5
--- /dev/null
+++ b/board/renesas/lager/lager.c
@@ -0,0 +1,357 @@
+/*
+ * board/renesas/lager/lager.c
+ * This file is lager board support.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <miiphy.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define s_init_wait(cnt) \
+ ({ \
+ u32 i = 0x10000 * cnt; \
+ while (i > 0) \
+ i--; \
+ })
+
+#define dbpdrgd_check(bsc) \
+ ({ \
+ while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
+ ; \
+ })
+
+#if defined(CONFIG_NORFLASH)
+static void bsc_init(void)
+{
+ struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE;
+ struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE;
+
+ /* LBSC */
+ writel(0x00000020, &lbsc->cs0ctrl);
+ writel(0x00000020, &lbsc->cs1ctrl);
+ writel(0x00002020, &lbsc->ecs0ctrl);
+ writel(0x00002020, &lbsc->ecs1ctrl);
+
+ writel(0x077F077F, &lbsc->cswcr0);
+ writel(0x077F077F, &lbsc->cswcr1);
+ writel(0x077F077F, &lbsc->ecswcr0);
+ writel(0x077F077F, &lbsc->ecswcr1);
+
+ /* DBSC3 */
+ s_init_wait(10);
+
+ writel(0x0000A55A, &dbsc3_0->dbpdlck);
+ writel(0x00000001, &dbsc3_0->dbpdrga);
+ writel(0x80000000, &dbsc3_0->dbpdrgd);
+ writel(0x00000004, &dbsc3_0->dbpdrga);
+ dbpdrgd_check(dbsc3_0);
+
+ writel(0x00000006, &dbsc3_0->dbpdrga);
+ writel(0x0001C000, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000023, &dbsc3_0->dbpdrga);
+ writel(0x00FD2480, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000010, &dbsc3_0->dbpdrga);
+ writel(0xF004649B, &dbsc3_0->dbpdrgd);
+
+ writel(0x0000000F, &dbsc3_0->dbpdrga);
+ writel(0x00181EE4, &dbsc3_0->dbpdrgd);
+
+ writel(0x0000000E, &dbsc3_0->dbpdrga);
+ writel(0x33C03812, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000003, &dbsc3_0->dbpdrga);
+ writel(0x0300C481, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000007, &dbsc3_0->dbkind);
+ writel(0x10030A02, &dbsc3_0->dbconf0);
+ writel(0x00000001, &dbsc3_0->dbphytype);
+ writel(0x00000000, &dbsc3_0->dbbl);
+ writel(0x0000000B, &dbsc3_0->dbtr0);
+ writel(0x00000008, &dbsc3_0->dbtr1);
+ writel(0x00000000, &dbsc3_0->dbtr2);
+ writel(0x0000000B, &dbsc3_0->dbtr3);
+ writel(0x000C000B, &dbsc3_0->dbtr4);
+ writel(0x00000027, &dbsc3_0->dbtr5);
+ writel(0x0000001C, &dbsc3_0->dbtr6);
+ writel(0x00000005, &dbsc3_0->dbtr7);
+ writel(0x00000018, &dbsc3_0->dbtr8);
+ writel(0x00000008, &dbsc3_0->dbtr9);
+ writel(0x0000000C, &dbsc3_0->dbtr10);
+ writel(0x00000009, &dbsc3_0->dbtr11);
+ writel(0x00000012, &dbsc3_0->dbtr12);
+ writel(0x000000D0, &dbsc3_0->dbtr13);
+ writel(0x00140005, &dbsc3_0->dbtr14);
+ writel(0x00050004, &dbsc3_0->dbtr15);
+ writel(0x70233005, &dbsc3_0->dbtr16);
+ writel(0x000C0000, &dbsc3_0->dbtr17);
+ writel(0x00000300, &dbsc3_0->dbtr18);
+ writel(0x00000040, &dbsc3_0->dbtr19);
+ writel(0x00000001, &dbsc3_0->dbrnk0);
+ writel(0x00020001, &dbsc3_0->dbadj0);
+ writel(0x20082008, &dbsc3_0->dbadj2);
+ writel(0x00020002, &dbsc3_0->dbwt0cnf0);
+ writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
+
+ writel(0x00000015, &dbsc3_0->dbpdrga);
+ writel(0x00000D70, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000016, &dbsc3_0->dbpdrga);
+ writel(0x00000006, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000017, &dbsc3_0->dbpdrga);
+ writel(0x00000018, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000012, &dbsc3_0->dbpdrga);
+ writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000013, &dbsc3_0->dbpdrga);
+ writel(0x1A868300, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000023, &dbsc3_0->dbpdrga);
+ writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000014, &dbsc3_0->dbpdrga);
+ writel(0x300214D8, &dbsc3_0->dbpdrgd);
+
+ writel(0x0000001A, &dbsc3_0->dbpdrga);
+ writel(0x930035C7, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000060, &dbsc3_0->dbpdrga);
+ writel(0x330657B2, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000011, &dbsc3_0->dbpdrga);
+ writel(0x1000040B, &dbsc3_0->dbpdrgd);
+
+ writel(0x0000FA00, &dbsc3_0->dbcmd);
+ writel(0x00000001, &dbsc3_0->dbpdrga);
+ writel(0x00000071, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000004, &dbsc3_0->dbpdrga);
+ dbpdrgd_check(dbsc3_0);
+
+ writel(0x0000FA00, &dbsc3_0->dbcmd);
+ writel(0x2100FA00, &dbsc3_0->dbcmd);
+ writel(0x0000FA00, &dbsc3_0->dbcmd);
+ writel(0x0000FA00, &dbsc3_0->dbcmd);
+ writel(0x0000FA00, &dbsc3_0->dbcmd);
+ writel(0x0000FA00, &dbsc3_0->dbcmd);
+ writel(0x0000FA00, &dbsc3_0->dbcmd);
+ writel(0x0000FA00, &dbsc3_0->dbcmd);
+ writel(0x0000FA00, &dbsc3_0->dbcmd);
+
+ writel(0x110000DB, &dbsc3_0->dbcmd);
+
+ writel(0x00000001, &dbsc3_0->dbpdrga);
+ writel(0x00000181, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000004, &dbsc3_0->dbpdrga);
+ dbpdrgd_check(dbsc3_0);
+
+ writel(0x00000001, &dbsc3_0->dbpdrga);
+ writel(0x0000FE01, &dbsc3_0->dbpdrgd);
+
+ writel(0x00000004, &dbsc3_0->dbpdrga);
+ dbpdrgd_check(dbsc3_0);
+
+ writel(0x00000000, &dbsc3_0->dbbs0cnt1);
+ writel(0x01004C20, &dbsc3_0->dbcalcnf);
+ writel(0x014000AA, &dbsc3_0->dbcaltr);
+ writel(0x00000140, &dbsc3_0->dbrfcnf0);
+ writel(0x00081860, &dbsc3_0->dbrfcnf1);
+ writel(0x00010000, &dbsc3_0->dbrfcnf2);
+ writel(0x00000001, &dbsc3_0->dbrfen);
+ writel(0x00000001, &dbsc3_0->dbacen);
+}
+#else
+#define bsc_init() do {} while (0)
+#endif /* CONFIG_NORFLASH */
+
+void s_init(void)
+{
+ struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE;
+ struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* QoS(Quality-of-Service) Init */
+ qos_init();
+
+ /* BSC init */
+ bsc_init();
+}
+
+#define MSTPSR1 0xE6150038
+#define SMSTPCR1 0xE6150134
+#define TMU0_MSTP125 (1 << 25)
+
+#define MSTPSR7 0xE61501C4
+#define SMSTPCR7 0xE615014C
+#define SCIF0_MSTP721 (1 << 21)
+
+#define MSTPSR8 0xE61509A0
+#define SMSTPCR8 0xE6150990
+#define ETHER_MSTP813 (1 << 13)
+
+#define PMMR 0xE6060000
+#define GPSR4 0xE6060014
+#define IPSR14 0xE6060058
+
+#define set_guard_reg(addr, mask, value) \
+{ \
+ u32 val; \
+ val = (readl(addr) & ~(mask)) | (value); \
+ writel(~val, PMMR); \
+ writel(val, addr); \
+}
+
+#define mstp_setbits(type, addr, saddr, set) \
+ out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+ out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+ mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear) \
+ mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+ /* TMU0 */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+#if defined(CONFIG_NORFLASH)
+ /* SCIF0 */
+ set_guard_reg(GPSR4, 0x34000000, 0x00000000);
+ set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
+ set_guard_reg(GPSR4, 0x00000000, 0x34000000);
+#endif
+
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+ return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+ /* board id for linux */
+ gd->bd->bi_arch_number = MACH_TYPE_LAGER;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100;
+
+ /* Init PFC controller */
+ r8a7790_pinmux_init();
+
+ /* ETHER Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ0, NULL);
+
+ gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */
+ gpio_direction_output(GPIO_GP_5_31, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_5_31, 1);
+ udelay(1);
+
+ return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+ int ret = -ENODEV;
+
+#ifdef CONFIG_SH_ETHER
+ u32 val;
+ unsigned char enetaddr[6];
+
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+
+#endif
+
+ return ret;
+}
+
+/* lager has KSZ8041NL/RNL */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c
new file mode 100644
index 0000000..756be18
--- /dev/null
+++ b/board/renesas/lager/qos.c
@@ -0,0 +1,1112 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+enum {
+ DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04,
+ DBSC3_R05, DBSC3_R06, DBSC3_R07, DBSC3_R08, DBSC3_R09,
+ DBSC3_R10, DBSC3_R11, DBSC3_R12, DBSC3_R13, DBSC3_R14,
+ DBSC3_R15,
+ DBSC3_W00, DBSC3_W01, DBSC3_W02, DBSC3_W03, DBSC3_W04,
+ DBSC3_W05, DBSC3_W06, DBSC3_W07, DBSC3_W08, DBSC3_W09,
+ DBSC3_W10, DBSC3_W11, DBSC3_W12, DBSC3_W13, DBSC3_W14,
+ DBSC3_W15,
+ DBSC3_NR,
+};
+
+static const u32 dbsc3_qos_addr[DBSC3_NR] = {
+ [DBSC3_R00] = DBSC3_0_QOS_R0_BASE,
+ [DBSC3_R01] = DBSC3_0_QOS_R1_BASE,
+ [DBSC3_R02] = DBSC3_0_QOS_R2_BASE,
+ [DBSC3_R03] = DBSC3_0_QOS_R3_BASE,
+ [DBSC3_R04] = DBSC3_0_QOS_R4_BASE,
+ [DBSC3_R05] = DBSC3_0_QOS_R5_BASE,
+ [DBSC3_R06] = DBSC3_0_QOS_R6_BASE,
+ [DBSC3_R07] = DBSC3_0_QOS_R7_BASE,
+ [DBSC3_R08] = DBSC3_0_QOS_R8_BASE,
+ [DBSC3_R09] = DBSC3_0_QOS_R9_BASE,
+ [DBSC3_R10] = DBSC3_0_QOS_R10_BASE,
+ [DBSC3_R11] = DBSC3_0_QOS_R11_BASE,
+ [DBSC3_R12] = DBSC3_0_QOS_R12_BASE,
+ [DBSC3_R13] = DBSC3_0_QOS_R13_BASE,
+ [DBSC3_R14] = DBSC3_0_QOS_R14_BASE,
+ [DBSC3_R15] = DBSC3_0_QOS_R15_BASE,
+ [DBSC3_W00] = DBSC3_0_QOS_W0_BASE,
+ [DBSC3_W01] = DBSC3_0_QOS_W1_BASE,
+ [DBSC3_W02] = DBSC3_0_QOS_R2_BASE,
+ [DBSC3_W03] = DBSC3_0_QOS_R3_BASE,
+ [DBSC3_W04] = DBSC3_0_QOS_R4_BASE,
+ [DBSC3_W05] = DBSC3_0_QOS_R5_BASE,
+ [DBSC3_W06] = DBSC3_0_QOS_R6_BASE,
+ [DBSC3_W07] = DBSC3_0_QOS_R7_BASE,
+ [DBSC3_W08] = DBSC3_0_QOS_R8_BASE,
+ [DBSC3_W09] = DBSC3_0_QOS_R9_BASE,
+ [DBSC3_W10] = DBSC3_0_QOS_W10_BASE,
+ [DBSC3_W11] = DBSC3_0_QOS_W11_BASE,
+ [DBSC3_W12] = DBSC3_0_QOS_W12_BASE,
+ [DBSC3_W13] = DBSC3_0_QOS_W13_BASE,
+ [DBSC3_W14] = DBSC3_0_QOS_W14_BASE,
+ [DBSC3_W15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+ int i;
+ struct r8a7790_s3c *s3c;
+ struct r8a7790_s3c_qos *s3c_qos;
+ struct r8a7790_dbsc3_qos *qos_addr;
+ struct r8a7790_mxi *mxi;
+ struct r8a7790_axi_qos *axi_qos;
+
+ /* S3C -QoS */
+ s3c = (struct r8a7790_s3c *)S3C_BASE;
+ writel(0x80FF1D0D, &s3c->s3cadsplcr);
+ writel(0x0F0F0505, &s3c->s3crorr);
+ writel(0x0F0F0505, &s3c->s3cworr);
+
+ /* QoS Control Registers */
+ s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI0_BASE;
+ writel(0x00800080, &s3c_qos->s3cqos0);
+ writel(0x20410001, &s3c_qos->s3cqos1);
+ writel(0x200A2023, &s3c_qos->s3cqos2);
+ writel(0x20502001, &s3c_qos->s3cqos3);
+ writel(0x20142032, &s3c_qos->s3cqos4);
+ writel(0x20410001, &s3c_qos->s3cqos5);
+
+ writel(0x200A2023, &s3c_qos->s3cqos6);
+ writel(0x20502001, &s3c_qos->s3cqos7);
+ writel(0x20142032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI1_BASE;
+ writel(0x00800080, &s3c_qos->s3cqos0);
+ writel(0x20410001, &s3c_qos->s3cqos1);
+ writel(0x200A2023, &s3c_qos->s3cqos2);
+ writel(0x20502001, &s3c_qos->s3cqos3);
+ writel(0x20142032, &s3c_qos->s3cqos4);
+ writel(0x20410001, &s3c_qos->s3cqos5);
+ writel(0x200A2023, &s3c_qos->s3cqos6);
+ writel(0x20502001, &s3c_qos->s3cqos7);
+ writel(0x20142032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_MXI_BASE;
+ writel(0x00810081, &s3c_qos->s3cqos0);
+ writel(0x20410FFF, &s3c_qos->s3cqos1);
+ writel(0x200A2023, &s3c_qos->s3cqos2);
+ writel(0x20502001, &s3c_qos->s3cqos3);
+ writel(0x20142032, &s3c_qos->s3cqos4);
+ writel(0x20410FFF, &s3c_qos->s3cqos5);
+ writel(0x200A2023, &s3c_qos->s3cqos6);
+ writel(0x20502001, &s3c_qos->s3cqos7);
+ writel(0x20142032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_AXI_BASE;
+ writel(0x00810081, &s3c_qos->s3cqos0);
+ writel(0x20410FFF, &s3c_qos->s3cqos1);
+ writel(0x200A2023, &s3c_qos->s3cqos2);
+ writel(0x20502001, &s3c_qos->s3cqos3);
+ writel(0x20142032, &s3c_qos->s3cqos4);
+ writel(0x20410FFF, &s3c_qos->s3cqos5);
+ writel(0x200A2023, &s3c_qos->s3cqos6);
+ writel(0x20502001, &s3c_qos->s3cqos7);
+ writel(0x20142032, &s3c_qos->s3cqos8);
+
+ /* DBSC -QoS */
+ /* DBSC0 - Read/Write */
+ for (i = DBSC3_R00; i < DBSC3_NR; i++) {
+ qos_addr = (struct r8a7790_dbsc3_qos *)dbsc3_qos_addr[i];
+ writel(0x00000203, &qos_addr->dblgcnt);
+ writel(0x00002064, &qos_addr->dbtmval0);
+ writel(0x00002048, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00002019, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002019, &qos_addr->dbthres0);
+ writel(0x00002019, &qos_addr->dbthres1);
+ writel(0x00002019, &qos_addr->dbthres2);
+ writel(0x00000000, &qos_addr->dblgqon);
+ }
+ /* CCI-400 -OoS */
+ writel(0x20001000, CCI_400_MAXOT_1);
+ writel(0x20001000, CCI_400_MAXOT_2);
+ writel(0x0000000C, CCI_400_QOSCNTL_1);
+ writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+ /* MXI -OoS */
+ /* Transaction Control (MXI) */
+ mxi = (struct r8a7790_mxi *)MXI_BASE;
+ writel(0x00200000, &mxi->mxs3cracr);
+ writel(0x00000013, &mxi->mxrtcr);
+ writel(0x00000013, &mxi->mxrtcr);
+
+ /* AXI -QoS */
+ /* Transaction Control (MXI) */
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_AVB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_G2D_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX0_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX1_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_LBS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x0000212C, &axi_qos->qosthres0);
+ writel(0x000020C8, &axi_qos->qosthres1);
+ writel(0x00002064, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x0000212C, &axi_qos->qosthres0);
+ writel(0x000020C8, &axi_qos->qosthres1);
+ writel(0x00002064, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x0000212C, &axi_qos->qosthres0);
+ writel(0x000020C8, &axi_qos->qosthres1);
+ writel(0x00002064, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x0000212C, &axi_qos->qosthres0);
+ writel(0x000020C8, &axi_qos->qosthres1);
+ writel(0x00002064, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x0000212C, &axi_qos->qosthres0);
+ writel(0x000020C8, &axi_qos->qosthres1);
+ writel(0x00002064, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_PCI_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_RTX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB20_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB21_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB22_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB30_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (RT-AXI) */
+ axi_qos = (struct r8a7790_axi_qos *)RT_AXI_SHX_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RDS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002006, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)RT_AXI_STPRO_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002003, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (MP-AXI) */
+ axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ADSP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x0000212C, &axi_qos->qosthres0);
+ writel(0x000020C8, &axi_qos->qosthres1);
+ writel(0x00002034, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPU_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPUC_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200D, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (SYS-AXI256) */
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_SYX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MPX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (CCI-AXI) */
+ axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_SYX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00002005, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002001, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (Media-AXI) */
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPR_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPW_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosctset1);
+ writel(0x00000000, &axi_qos->qosctset2);
+ writel(0x00000000, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002008, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002003, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002003, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002006, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002003, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200B, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002003, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200B, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002003, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002003, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002009, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002009, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00000000, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002002, &axi_qos->qosthres2);
+ writel(0x00000000, &axi_qos->qosqon);
+
+ /* CCI-AXI Function Register */
+ writel(0x00000011, CCI_AXI_IPMMUIDVMCR);
+ writel(0x00000011, CCI_AXI_IPMMURDVMCR);
+ writel(0x00000011, CCI_AXI_IPMMUS0DVMCR);
+ writel(0x00000011, CCI_AXI_IPMMUS1DVMCR);
+ writel(0x00000011, CCI_AXI_IPMMUMPDVMCR);
+ writel(0x00000011, CCI_AXI_IPMMUDSDVMCR);
+ writel(0x0000F700, CCI_AXI_AX2ADDRMASK);
+}
diff --git a/board/renesas/lager/qos.h b/board/renesas/lager/qos.h
new file mode 100644
index 0000000..9a6c046
--- /dev/null
+++ b/board/renesas/lager/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index be810c7..8e38d3c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -341,6 +341,8 @@ u8500_href arm armv7 u8500 st-eric
snowball arm armv7 snowball st-ericsson u8500
kzm9g arm armv7 kzm9g kmc rmobile
armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile
+lager arm armv7 lager renesas rmobile
+lager_nor arm armv7 lager renesas rmobile lager:NORFLASH
zynq arm armv7 zynq xilinx zynq
zynq_dcc arm armv7 zynq xilinx zynq zynq:ZYNQ_DCC
socfpga_cyclone5 arm armv7 socfpga altera socfpga
diff --git a/include/configs/lager.h b/include/configs/lager.h
new file mode 100644
index 0000000..9ee9159
--- /dev/null
+++ b/include/configs/lager.h
@@ -0,0 +1,186 @@
+/*
+ * include/configs/lager.h
+ * This file is lager board configuration.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __LAGER_H
+#define __LAGER_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7790
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Lager"
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_BOOTZ
+
+#if defined(CONFIG_NORFLASH)
+#define CONFIG_CMD_FLASH
+#else
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#endif
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_OF_LIBFDT
+
+/* #define CONFIG_OF_LIBFDT */
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS ""
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR 0xE827fffc
+#define STACK_AREA_SIZE 0xC000
+#define LOW_LEVEL_MERAM_STACK \
+ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define LAGER_SDRAM_BASE 0x40000000
+#define LAGER_SDRAM_SIZE (2048u * 1024 * 1024)
+#define LAGER_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE 512
+#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+#define SCIF0_BASE 0xe6e60000
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START (LAGER_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+ 504 * 1024 * 1024)
+#undef CONFIG_SYS_ALT_MEMTEST
+#undef CONFIG_SYS_MEMTEST_SCRATCH
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE (LAGER_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE (LAGER_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE (256)
+#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+
+#if defined(CONFIG_CMD_FLASH)
+/* USE NOR FLASH */
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
+#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
+
+#else
+/* USE SPI */
+#define CONFIG_SYS_TEXT_BASE 0xE8080000
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SH_QSPI_BASE 0xE6B10000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
+#define CONFIG_ENV_ADDR 0xC0000
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
+#endif
+
+/* SH Ether */
+#define CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT 0
+#define CONFIG_SH_ETHER_PHY_ADDR 0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define CONFIG_BASE_CLK_FREQ 20000000u
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2)
+#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
+#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ
+
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#define CONFIG_SYS_HZ 1000
+
+#endif /* __LAGER_H */
--
1.8.3.2