From mboxrd@z Thu Jan 1 00:00:00 1970 From: Prabhakar Kushwaha Date: Fri, 20 Sep 2013 09:21:52 +0530 Subject: [U-Boot] [RFC 5/5] B4860QDS: Add support of 2 stage NAND boot loader In-Reply-To: References: <1379347543-21335-1-git-send-email-prabhakar@freescale.com> <52398B66.1070902@freescale.com> Message-ID: <523BC658.1010702@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 09/20/2013 04:51 AM, Rommel Custodio wrote: > Dear Prabhakar Kushwaha, > > Prabhakar Kushwaha freescale.com> writes: >>> > > > Thank you for the replies. > >>> You mention you use the PBL... but probably not a pblimage. The patch >>> correctly fixes RAMBOOT_PBL as a trigger to generate the pblimage (u- >>> boot.pbl) but there seems to be no RCW or PBI file defined. >> B4860 does support PBL based NAND boot. >> but I have yet to integrate u-boot-spl.bin to generated u-boot-spl.pbl. >> This is in my TODO list > This is my understanding (if need be, take it with a grain of salt) > > The Makefiles need to be modified so that SPL build will create a pblimage. > The "mkimage pblimage" needs to be executed only on the SPL binary. Then the > top-level Makefile proceeds in concatenating the u-boot-spl.bin (now a > pblimage) and u-boot.bin. > yes. This is my next plan. >>> I have one question, can this scenario be implemented on a P5040? i.e. >>> simulate that CPC is around 128Kb and load u-boot via SPL? Now all > corenet >>> processors seem to only support pblimage booting. >>> >> yes. This scenario can be implemented for P5040. Only need to create >> spl.c file + define constants. > Seems easy enough :-) though I probably don't have the resources to actually > implement it. > > Just a note. The pblimage booting is not very flexible now. Currently it > assumes that u-boot.pbl will fit into CPC (configured as SRAM). This is OK > for most processors (i.e P5040 with 1Mb CPC) but it will not work for others > (i.e T1040/1042 with only 256Kb CPC). So there is a need to have SPL in this > case. > > Me along with others are owner of T1040 platform. This whole exercise is done for T1040 & future soc which may have < 512K CPC. Once base patch of T1040QDS has been accepted(already in review state). I will send a patch set to add support of 2 Stage boot loader. Regards, Prabhakar