From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Date: Mon, 23 Sep 2013 15:45:01 -0600 Subject: [U-Boot] [PATCH v2 1/2] Tegra114: Fix PLLX M, N, P init settings In-Reply-To: <1379966870-4087-1-git-send-email-treding@nvidia.com> References: <1379966870-4087-1-git-send-email-treding@nvidia.com> Message-ID: <5240B65D.2020703@wwwdotorg.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 09/23/2013 02:07 PM, Thierry Reding wrote: > From: Jimmy Zhang > > The M, N and P width have been changed from Tegra30. The maximum value > for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should > be set accordingly. The series, Acked-by: Stephen Warren