From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pierre AUBERT Date: Wed, 25 Sep 2013 09:38:22 +0200 Subject: [U-Boot] [PATCH] ARM: arch-mx6: fix PLL2_PFD2_FREQ In-Reply-To: <52428F94.3080604@tqsc.de> References: <1378906215-14266-1-git-send-email-list-09_u-boot@tqsc.de> <523C534C.70309@denx.de> <1379687566495-163654.post@n7.nabble.com> <52428F94.3080604@tqsc.de> Message-ID: <524292EE.2030306@staubli.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hello Markus, Le 25/09/2013 09:24, Markus Niebel a ?crit : > Hello Pierre, > > --- > arch/arm/include/asm/arch-mx6/crm_regs.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h > b/arch/arm/include/asm/arch-mx6/crm_regs.h > index 74aefe6..2813593 100644 > --- a/arch/arm/include/asm/arch-mx6/crm_regs.h > +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h > @@ -892,7 +892,7 @@ struct mxc_ccm_reg { > > #define PLL2_PFD0_FREQ 352000000 > #define PLL2_PFD1_FREQ 594000000 > -#define PLL2_PFD2_FREQ 400000000 > +#define PLL2_PFD2_FREQ 396000000 > #define PLL2_PFD2_DIV_FREQ 200000000 > #define PLL3_PFD0_FREQ 720000000 > #define PLL3_PFD1_FREQ 540000000 > >> >> Hello Markus, Hello Stephano >> I think it's better to compute this frequencies rather than hard coding >> values. The default PFD frequencies are not the same for the Quad and for >> the other Socs. > As far as I read the manual for i.MX6Q/D and i.MX6DL/S have the same default values. For the i.MX6Q/D, the PLL2-PFD0 is 352MHz and the PLL2-PFD1 is 594MHz. For the i.MX6DL/S, the PLL2-PFD0 is 302.58MHz and the PLL2-PFD1 is 528MHz. The definitions in the crm_regs.h are for the i.MX6Q/D. > >> Furthermore, if you modify PLL2_PFD2_FREQ, you must also change >> PLL2_PFD2_DIV_FREQ. >> >> Please, see the patch I've submitted yesterday ([PATCH V2] mx6: compute PLL >> PFD frequencies rather than using defines) >> > Hmm. Sounds reasonable.Do you expect any side effects? > (We came accross the mismatch that was fixed with my original > patch when looking over DRAM configuration) > I've tested it on the SabreSD with i.MX6DL and on a custom board with i.MX6Q and i.MX6S and I didn't noticed any side effects. Best regards