From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 1 Oct 2013 08:42:43 -0700 Subject: [U-Boot] [PATCH] mpc85xx: Fix the offset of register address error In-Reply-To: <1379842421-13957-1-git-send-email-Yuantian.Tang@freescale.com> References: <1379842421-13957-1-git-send-email-Yuantian.Tang@freescale.com> Message-ID: <524AED73.2040205@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 09/22/2013 02:33 AM, Tang Yuantian wrote: > From: Tang Yuantian > > The offset of register address within GPIO module is just > CONFIG_SYS_MPC85xx_GPIO_ADDR, no reason to add 0xc00. > > Signed-off-by: Tang Yuantian > --- > arch/powerpc/include/asm/mpc85xx_gpio.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h > index 3d11884..87bb4a0 100644 > --- a/arch/powerpc/include/asm/mpc85xx_gpio.h > +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h > @@ -20,7 +20,7 @@ > static inline void mpc85xx_gpio_set(unsigned int mask, > unsigned int dir, unsigned int val) > { > - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); > + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); > > /* First mask off the unwanted parts of "dir" and "val" */ > dir &= mask; > @@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios) > > static inline unsigned int mpc85xx_gpio_get(unsigned int mask) > { > - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); > + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); > > /* Read the requested values */ > return in_be32(&gpio->gpdat) & mask; > Yuantian, Please go through the base address again. I think some SoCs do use 0xc00 offset from 0xF000, for eample P1020, P1023, MPC8572. I only spot checked several. York