[U-Boot] [UBOOT][PATCHv3 0/7] mtd/spi: add quad/memory mapped read support, add ti qspi controller.

[U-Boot] [UBOOT][PATCHv3 0/7] mtd/spi: add quad/memory mapped read support, add ti qspi controller.

[Sourav Poddar]

This patch series add support for TI qspi controller and in the process also
add support for quad read and memory mapped read
in mtd spi framework.

Testing details:
Did a boot from qspi mode on DRA7xx.
Testing details present in the last patch of 
the series.

Currently, TI qpsi controller supports only 16MB access.
Access for higher MB area will be added later.

v2->v3:
1. run checkpatch
2. Rearrange the code logically.
3. Remove a page read hack.

Matt Porter (3):
  omap5: add qspi support
  spi: add TI QSPI driver
  dra7xx_evm: add SPL API, QSPI, and serial flash support

Ravikumar Kattekola (1):
  drivers: mtd: :spi: Add quad read support

Sourav Poddar (3):
  armv7: hw_data: change clock divider setting.
  driver: mtd: spi: Add memory mapped read support
  README: qspi usecase and testing documentation.

 arch/arm/cpu/armv7/omap5/hw_data.c     |   10 +-
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 board/ti/dra7xx/mux_data.h             |   10 +
 doc/README.ti_qspi_dra_test            |   38 ++++
 doc/README.ti_qspi_flash               |   47 +++++
 drivers/mtd/spi/spansion.c             |    1 +
 drivers/mtd/spi/spi_flash.c            |  113 +++++++++++-
 drivers/mtd/spi/spi_flash_internal.h   |    2 +
 drivers/spi/Makefile                   |    1 +
 drivers/spi/ti_qspi.c                  |  324 ++++++++++++++++++++++++++++++++
 include/configs/dra7xx_evm.h           |   20 ++
 include/spi.h                          |    5 +
 15 files changed, 575 insertions(+), 2 deletions(-)
 create mode 100644 doc/README.ti_qspi_dra_test
 create mode 100644 doc/README.ti_qspi_flash
 create mode 100644 drivers/spi/ti_qspi.c

[U-Boot] [UBOOT][PATCHv3 1/7] omap5: add qspi support

[Sourav Poddar]

From: Matt Porter <matt.porter@linaro.org>

Add QSPI definitions and clock configuration support.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 arch/arm/cpu/armv7/omap5/hw_data.c     |    8 ++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +++
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 5 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index fbbc486..c00bfb8 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -426,6 +426,10 @@ void enable_basic_clocks(void)
 #ifdef CONFIG_DRIVER_TI_CPSW
 		(*prcm)->cm_gmac_gmac_clkctrl,
 #endif
+
+#ifdef CONFIG_TI_QSPI
+		(*prcm)->cm_l4per_qspi_clkctrl,
+#endif
 		0
 	};
 
@@ -454,6 +458,10 @@ void enable_basic_clocks(void)
 			 clk_modules_explicit_en_essential,
 			 1);
 
+#ifdef CONFIG_TI_QSPI
+	setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
 	/* Enable SCRM OPT clocks for PER and CORE dpll */
 	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 			OPTFCLKEN_SCRM_PER_MASK);
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 579818d..0b1bb46 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -933,6 +933,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_l4per_gpio8_clkctrl			= 0x4a009818,
 	.cm_l4per_mmcsd3_clkctrl		= 0x4a009820,
 	.cm_l4per_mmcsd4_clkctrl		= 0x4a009828,
+	.cm_l4per_qspi_clkctrl			= 0x4a009838,
 	.cm_l4per_uart1_clkctrl			= 0x4a009840,
 	.cm_l4per_uart2_clkctrl			= 0x4a009848,
 	.cm_l4per_uart3_clkctrl			= 0x4a009850,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index e9a51d3..414d37a 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -61,6 +61,9 @@
 /* GPMC */
 #define OMAP54XX_GPMC_BASE	0x50000000
 
+/* QSPI */
+#define QSPI_BASE		0x4B300000
+
 /*
  * Hardware Register Details
  */
diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h
index fe8b0c0..57f0de5 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -15,6 +15,7 @@
 #define BOOT_DEVICE_MMC1        5
 #define BOOT_DEVICE_MMC2        6
 #define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_SPI		10
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
 #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2_2
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 5e2f027..f865c14 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -266,6 +266,7 @@ struct prcm_regs {
 	u32 cm_l4per_mmcsd4_clkctrl;
 	u32 cm_l4per_msprohg_clkctrl;
 	u32 cm_l4per_slimbus2_clkctrl;
+	u32 cm_l4per_qspi_clkctrl;
 	u32 cm_l4per_uart1_clkctrl;
 	u32 cm_l4per_uart2_clkctrl;
 	u32 cm_l4per_uart3_clkctrl;
-- 
1.7.1

[U-Boot] [UBOOT][PATCHv3 2/7] armv7: hw_data: change clock divider setting.

[Sourav Poddar]

Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,

f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)

fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 arch/arm/cpu/armv7/omap5/hw_data.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index c00bfb8..a1b249e 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -170,7 +170,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 	{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 20 MHz   */
+	{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 20 MHz   */
 	{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 16.8 MHz */
 	{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 19.2 MHz */
 	{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 26 MHz   */
-- 
1.7.1

[U-Boot] [UBOOT][PATCHv3 3/7] drivers: mtd: :spi: Add quad read support

[Sourav Poddar]

From: Ravikumar Kattekola <rk@ti.com>

Some flash like S25fl256s supports quad read mode also.
This patch enables the quad read support based on
CONFIG_SF_QUAD_RD config.

Enabling quad read has the following components:
1. Enable the Quad mode bit in the flash device side.
2. Add a quad read mode read api. I have created a new
   api for quad mode as some flash has few more quad read
   command that can be supported. As of now, I have addded only
   QUAD OUTPUT READ command.
3. spi driver need to know that the read to be done is the
   quad read. Communicate this to the driver through a
   "SPI_QUAD" flag. This need to be done because quad read should 
only happen when quad command is sent. For reading status register
and other configuration register normal transfers should happen.

Signed-off-by: Ravikumar Kattekola <rk@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 drivers/mtd/spi/spi_flash.c          |  109 +++++++++++++++++++++++++++++++++-
 drivers/mtd/spi/spi_flash_internal.h |    2 +
 include/spi.h                        |    2 +
 3 files changed, 112 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 5d5055f..993a9d4 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -42,8 +42,13 @@ static int spi_flash_read_write(struct spi_slave *spi,
 		debug("SF: Failed to send command (%zu bytes): %d\n",
 		      cmd_len, ret);
 	} else if (data_len != 0) {
+		if (spi->quad_enable)
+			flags = SPI_QUAD;
+		else
+			flags = 0;
+
 		ret = spi_xfer(spi, data_len * 8, data_out, data_in,
-					SPI_XFER_END);
+					flags | SPI_XFER_END);
 		if (ret)
 			debug("SF: Failed to transfer %zu bytes of data: %d\n",
 			      data_len, ret);
@@ -272,6 +277,58 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 	return ret;
 }
 
+int spi_flash_cmd_read_quad(struct spi_flash *flash, u32 offset,
+		size_t len, void *data)
+{
+	struct spi_slave *spi = flash->spi;
+	u8 cmd[5], bank_sel = 0;
+	u32 remain_len, read_len;
+	int ret = -1;
+
+	/* Handle memory-mapped SPI */
+	if (flash->memory_map) {
+		memcpy(data, flash->memory_map + offset, len);
+		return 0;
+	}
+
+	spi->quad_enable = true;
+	cmd[0] = CMD_READ_ARRAY_QUAD;
+	cmd[4] = 0x00;
+
+	while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+		bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+		ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+		if (ret) {
+			debug("SF: fail to set bank%d\n", bank_sel);
+			return ret;
+		}
+#endif
+
+		remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
+		if (len < remain_len)
+			read_len = len;
+		else
+			read_len = remain_len;
+
+		spi_flash_addr(offset, cmd);
+
+		ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+						data, read_len);
+		if (ret < 0) {
+			debug("SF: read failed\n");
+			break;
+		}
+
+		offset += read_len;
+		len -= read_len;
+		data += read_len;
+	}
+
+	return ret;
+}
+
 int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
 		size_t len, void *data)
 {
@@ -395,6 +452,48 @@ int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
 }
 #endif
 
+int spi_flash_en_quad_mode(struct spi_flash *flash)
+{
+	u8 stat, con, cd;
+	u16 cr;
+	int ret;
+	cd = CMD_WRITE_STATUS;
+
+	ret = spi_flash_cmd_write_enable(flash);
+	if (ret < 0) {
+		debug("SF: enabling write failed\n");
+		goto out;
+	}
+	ret = spi_flash_cmd(flash->spi, CMD_READ_STATUS, &stat, 1);
+	ret = spi_flash_cmd(flash->spi, CMD_READ_CONFIG, &con, 1);
+	if (ret < 0) {
+		debug("%s: SF: read CR failed\n", __func__);
+		goto out;
+	}
+	/* Byte 1 - status reg, Byte 2 - config reg */
+	cr = ((con | (0x1 << 1)) << 8) | (stat << 0);
+
+	ret = spi_flash_cmd_write(flash->spi, &cd, 1, &cr, 2);
+	if (ret) {
+		debug("SF: fail to write conf register\n");
+		goto out;
+	}
+
+	ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+	if (ret < 0) {
+		debug("SF: write conf register timed out\n");
+		goto out;
+	}
+
+	ret = spi_flash_cmd_write_disable(flash);
+	if (ret < 0) {
+		debug("SF: disabling write failed\n");
+		goto out;
+	}
+out:
+	return ret;
+}
+
 #ifdef CONFIG_OF_CONTROL
 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 {
@@ -549,6 +648,10 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 		goto err_manufacturer_probe;
 #endif
 
+#ifdef CONFIG_SF_QUAD_RD
+	spi_flash_en_quad_mode(flash);
+#endif
+
 #ifdef CONFIG_OF_CONTROL
 	if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
 		debug("SF: FDT decode error\n");
@@ -601,7 +704,11 @@ void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi,
 	flash->name = name;
 	flash->poll_cmd = CMD_READ_STATUS;
 
+#ifdef CONFIG_SF_QUAD_RD
+	flash->read = spi_flash_cmd_read_quad;
+#else
 	flash->read = spi_flash_cmd_read_fast;
+#endif
 	flash->write = spi_flash_cmd_write_multi;
 	flash->erase = spi_flash_cmd_erase;
 
diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h
index af1afa9..b388837 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -17,11 +17,13 @@
 
 #define CMD_READ_ARRAY_SLOW		0x03
 #define CMD_READ_ARRAY_FAST		0x0b
+#define CMD_READ_ARRAY_QUAD		0x6b
 
 #define CMD_WRITE_STATUS		0x01
 #define CMD_PAGE_PROGRAM		0x02
 #define CMD_WRITE_DISABLE		0x04
 #define CMD_READ_STATUS			0x05
+#define CMD_READ_CONFIG			0x35
 #define CMD_FLAG_STATUS			0x70
 #define CMD_WRITE_ENABLE		0x06
 #define CMD_ERASE_4K			0x20
diff --git a/include/spi.h b/include/spi.h
index c0dab57..9d4b2dc 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -27,6 +27,7 @@
 /* SPI transfer flags */
 #define SPI_XFER_BEGIN	0x01			/* Assert CS before transfer */
 #define SPI_XFER_END	0x02			/* Deassert CS after transfer */
+#define SPI_QUAD	0x04			/* Use QUAD read command */
 
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec
@@ -45,6 +46,7 @@ struct spi_slave {
 	unsigned int	bus;
 	unsigned int	cs;
 	unsigned int max_write_size;
+	bool quad_enable;
 };
 
 /*-----------------------------------------------------------------------
-- 
1.7.1

[U-Boot] [UBOOT][PATCHv3 4/7] driver: mtd: spi: Add memory mapped read support

[Sourav Poddar]

Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped port read.

This patch enables the following:
- It enables exchange of memory map address between mtd and qspi
through the introduction of "memory_map" flag.
- Add support to communicate to the driver that memory mapped
 transfer is to be started through introduction of new flags like
"SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END".

This will enable the spi controller to do memory mapped configurations
if required.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 drivers/mtd/spi/spansion.c  |    1 +
 drivers/mtd/spi/spi_flash.c |    4 ++++
 include/spi.h               |    3 +++
 3 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index fa7ac8c..9d801a3 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -136,6 +136,7 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
 	flash->page_size = 256;
 	flash->sector_size = 256 * params->pages_per_sector;
 	flash->size = flash->sector_size * params->nr_sectors;
+	flash->memory_map = spi->memory_map;
 
 	return flash;
 }
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 993a9d4..5ad2dc1 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -287,7 +287,9 @@ int spi_flash_cmd_read_quad(struct spi_flash *flash, u32 offset,
 
 	/* Handle memory-mapped SPI */
 	if (flash->memory_map) {
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
 		memcpy(data, flash->memory_map + offset, len);
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP_END);
 		return 0;
 	}
 
@@ -338,7 +340,9 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
 
 	/* Handle memory-mapped SPI */
 	if (flash->memory_map) {
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
 		memcpy(data, flash->memory_map + offset, len);
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP_END);
 		return 0;
 	}
 
diff --git a/include/spi.h b/include/spi.h
index 9d4b2dc..559722f 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -28,6 +28,8 @@
 #define SPI_XFER_BEGIN	0x01			/* Assert CS before transfer */
 #define SPI_XFER_END	0x02			/* Deassert CS after transfer */
 #define SPI_QUAD	0x04			/* Use QUAD read command */
+#define SPI_XFER_MEM_MAP 0x08			/* Memory Mapped start */
+#define SPI_XFER_MEM_MAP_END 0x10		/* Memory Mapped End */
 
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec
@@ -47,6 +49,7 @@ struct spi_slave {
 	unsigned int	cs;
 	unsigned int max_write_size;
 	bool quad_enable;
+	void *memory_map;
 };
 
 /*-----------------------------------------------------------------------
-- 
1.7.1

[U-Boot] [UBOOT][PATCHv3 5/7] spi: add TI QSPI driver

[Sourav Poddar]

From: Matt Porter <matt.porter@linaro.org>

Adds a SPI master driver for the TI QSPI peripheral.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
[Added quad read support and memory mapped support).
---
 drivers/spi/Makefile  |    1 +
 drivers/spi/ti_qspi.c |  324 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 325 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/ti_qspi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
 COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
 
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 0000000..3e88cf4
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,324 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/omap.h>
+#include <malloc.h>
+#include <spi.h>
+
+struct qspi_slave {
+	struct spi_slave slave;
+	unsigned int mode;
+	u32 cmd;
+	u32 dc;
+};
+
+#define to_qspi_slave(s) container_of(s, struct qspi_slave, slave)
+
+struct qspi_regs {
+	u32 pid;
+	u32 pad0[3];
+	u32 sysconfig;
+	u32 pad1[3];
+	u32 intr_status_raw_set;
+	u32 intr_status_enabled_clear;
+	u32 intr_enable_set;
+	u32 intr_enable_clear;
+	u32 intc_eoi;
+	u32 pad2[3];
+	u32 spi_clock_cntrl;
+	u32 spi_dc;
+	u32 spi_cmd;
+	u32 spi_status;
+	u32 spi_data;
+	u32 spi_setup0;
+	u32 spi_setup1;
+	u32 spi_setup2;
+	u32 spi_setup3;
+	u32 spi_switch;
+	u32 spi_data1;
+	u32 spi_data2;
+	u32 spi_data3;
+};
+
+static struct qspi_regs *qspi = (struct qspi_regs *)QSPI_BASE;
+
+#define QSPI_TIMEOUT			2000000
+
+#define QSPI_FCLK			192000000
+
+/* Clock Control */
+#define QSPI_CLK_EN			(1 << 31)
+#define QSPI_CLK_DIV_MAX		0xffff
+
+/* Command */
+#define QSPI_EN_CS(n)			(n << 28)
+#define QSPI_WLEN(n)			((n-1) << 19)
+#define QSPI_3_PIN			(1 << 18)
+#define QSPI_RD_SNGL			(1 << 16)
+#define QSPI_WR_SNGL			(2 << 16)
+#define QSPI_INVAL			(4 << 16)
+#define QSPI_RD_QUAD			(7 << 16)
+
+/* Device Control */
+#define QSPI_DD(m, n)			(m << (3 + n*8))
+#define QSPI_CKPHA(n)			(1 << (2 + n*8))
+#define QSPI_CSPOL(n)			(1 << (1 + n*8))
+#define QSPI_CKPOL(n)			(1 << (n*8))
+
+/* Status */
+#define QSPI_WC				(1 << 1)
+#define QSPI_BUSY			(1 << 0)
+#define QSPI_WC_BUSY			(QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE			QSPI_WC
+
+#define MM_SWITCH			0x01
+#define MEM_CS				0x100
+#define MEM_CS_UNSELECT			0xfffff0ff
+#define MMAP_START_ADDR			0x5c000000
+#define CORE_CTRL_IO			0x4a002558
+
+#define QSPI_CMD_READ			(0x3 << 0)
+#define QSPI_CMD_READ_QUAD		(0x6b << 0)
+#define QSPI_CMD_READ_FAST		(0x0b << 0)
+#define QSPI_SETUP0_NUM_A_BYTES		(0x2 << 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS	(0x0 << 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS	(0x1 << 10)
+#define QSPI_SETUP0_READ_NORMAL		(0x0 << 12)
+#define QSPI_SETUP0_READ_QUAD		(0x3 << 12)
+#define QSPI_CMD_WRITE			(0x2 << 16)
+#define QSPI_NUM_DUMMY_BITS		(0x0 << 24)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	/* CS handled in xfer */
+	return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	/* CS handled in xfer */
+	return;
+}
+
+void spi_init(void)
+{
+	/* nothing to do */
+}
+
+void spi_set_up_spi_register(struct spi_slave *slave)
+{
+	u32 memval = 0;
+
+	slave->memory_map = (void *)MMAP_START_ADDR;
+
+#ifdef CONFIG_SF_QUAD_RD
+	memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
+		QSPI_SETUP0_NUM_D_BYTES_8_BITS | QSPI_SETUP0_READ_QUAD |
+			QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS);
+#else
+	memval |= (QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+		QSPI_SETUP0_NUM_D_BYTES_NO_BITS | QSPI_SETUP0_READ_NORMAL |
+			QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS);
+#endif
+	writel(memval, &qspi->spi_setup0);
+}
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+	uint clk_div;
+
+	if (!hz)
+		clk_div = 0;
+	else
+		clk_div = (QSPI_FCLK / hz) - 1;
+
+	debug("%s: hz: %d, clock divider %d\n", __func__, hz, clk_div);
+
+	/* disable SCLK */
+	writel(readl(&qspi->spi_clock_cntrl) & ~QSPI_CLK_EN,
+			&qspi->spi_clock_cntrl);
+
+	if (clk_div < 0) {
+		debug("%s: clock divider < 0, using /1 divider\n", __func__);
+		clk_div = 0;
+	}
+
+	if (clk_div > QSPI_CLK_DIV_MAX) {
+		debug("%s: clock divider >%d , using /%d divider\n",
+			__func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
+		clk_div = QSPI_CLK_DIV_MAX;
+	}
+
+	/* enable SCLK */
+	writel(QSPI_CLK_EN | clk_div, &qspi->spi_clock_cntrl);
+	debug("%s: spi_clock_cntrl %08x\n", __func__,
+		readl(&qspi->spi_clock_cntrl));
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode)
+{
+	struct qspi_slave *qslave;
+
+	qslave = spi_alloc_slave(struct qspi_slave, bus, cs);
+	if (!qslave)
+		return NULL;
+
+	spi_set_speed(&qslave->slave, max_hz);
+	qslave->mode = mode;
+
+#ifdef CONFIG_MMAP
+	spi_set_up_spi_register(&qslave->slave);
+#endif
+
+	debug("%s: bus:%i cs:%i mode:%i\n", __func__, bus, cs, mode);
+
+	return &qslave->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	struct qspi_slave *qslave = to_qspi_slave(slave);
+	free(qslave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+
+	writel(0, &qspi->spi_dc);
+	writel(0, &qspi->spi_cmd);
+	writel(0, &qspi->spi_data);
+
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+
+	writel(0, &qspi->spi_dc);
+	writel(0, &qspi->spi_cmd);
+	writel(0, &qspi->spi_data);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	struct qspi_slave *qslave = to_qspi_slave(slave);
+	uint words = bitlen >> 3; /* fixed 8-bit word length */
+	const uchar *txp = dout;
+	uchar *rxp = din;
+	uint status;
+	int timeout, val;
+
+	debug("%s: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", __func__,
+		slave->bus, slave->cs, bitlen, words, flags);
+
+	qslave->dc = 0;
+	if (qslave->mode & SPI_CPHA)
+		qslave->dc |= QSPI_CKPHA(slave->cs);
+	if (qslave->mode & SPI_CPOL)
+		qslave->dc |= QSPI_CKPOL(slave->cs);
+	if (qslave->mode & SPI_CS_HIGH)
+		qslave->dc |= QSPI_CSPOL(slave->cs);
+
+	writel(qslave->dc, &qspi->spi_dc);
+
+	if (flags & SPI_XFER_MEM_MAP) {
+		writel(MM_SWITCH, &qspi->spi_switch);
+		val = readl(CORE_CTRL_IO);
+		val |= MEM_CS;
+		writel(val, CORE_CTRL_IO);
+		return 0;
+	} else if (flags & SPI_XFER_MEM_MAP_END) {
+		writel(~MM_SWITCH, &qspi->spi_switch);
+		val = readl(CORE_CTRL_IO);
+		val &= MEM_CS_UNSELECT;
+		writel(val, CORE_CTRL_IO);
+		return 0;
+	}
+
+	if (bitlen == 0)
+		goto out;
+
+	if (bitlen % 8) {
+		flags |= SPI_XFER_END;
+		goto out;
+	}
+
+	/* setup command reg */
+	qslave->cmd = 0;
+	qslave->cmd |= QSPI_WLEN(8);
+	qslave->cmd |= QSPI_EN_CS(slave->cs);
+	if (flags & SPI_3WIRE)
+		qslave->cmd |= QSPI_3_PIN;
+	qslave->cmd |= 0xfff;
+
+	while (words--) {
+		if (txp) {
+			debug("tx cmd %08x dc %08x data %02x\n",
+			      qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
+			writel(*txp++, &qspi->spi_data);
+			writel(qslave->cmd | QSPI_WR_SNGL, &qspi->spi_cmd);
+			status = readl(&qspi->spi_status);
+			timeout = QSPI_TIMEOUT;
+			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
+				if (--timeout < 0) {
+					printf("QSPI tx timed out\n");
+					return -1;
+				}
+				status = readl(&qspi->spi_status);
+			}
+			debug("tx done, status %08x\n", status);
+		}
+		if (rxp) {
+			if (flags & SPI_QUAD)
+				qslave->cmd |= QSPI_RD_QUAD;
+			else
+				qslave->cmd |= QSPI_RD_SNGL;
+			debug("rx cmd %08x dc %08x\n",
+				qslave->cmd, qslave->dc);
+			writel(qslave->cmd, &qspi->spi_cmd);
+			status = readl(&qspi->spi_status);
+			timeout = QSPI_TIMEOUT;
+			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
+				if (--timeout < 0) {
+					printf("QSPI rx timed out\n");
+					return -1;
+				}
+				status = readl(&qspi->spi_status);
+			}
+			*rxp++ = readl(&qspi->spi_data);
+			debug("rx done, status %08x, read %02x\n",
+				status, *(rxp-1));
+		}
+	}
+
+out:
+	/* Terminate frame */
+	if (flags & SPI_XFER_END)
+		writel(qslave->cmd | QSPI_INVAL, &qspi->spi_cmd);
+
+	return 0;
+}
-- 
1.7.1

[U-Boot] [UBOOT][PATCHv3 6/7] dra7xx_evm: add SPL API, QSPI, and serial flash support

[Sourav Poddar]

From: Matt Porter <matt.porter@linaro.org>

Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 board/ti/dra7xx/mux_data.h   |   10 ++++++++++
 include/configs/dra7xx_evm.h |   20 ++++++++++++++++++++
 2 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 0a86594..6965cc5 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -51,5 +51,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{RGMII0_RXD2, (IEN | M0) },
 	{RGMII0_RXD1, (IEN | M0) },
 	{RGMII0_RXD0, (IEN | M0) },
+	{GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
+	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
+	{GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */
+	{GPMC_A16, (IEN | PDIS | M1)},  /* QSPI1_D[1] */
+	{GPMC_A17, (IEN | PDIS | M1)},  /* QSPI1_D[0] */
+	{GPMC_A18, (M1)},  /* QSPI1_SCLK */
+	{GPMC_A3, (IEN | PDIS | M1)},   /* QSPI1_CS2 */
+	{GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
+	{GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
+	{GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 4fbe768..1fee2f5 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -42,4 +42,24 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ADDR			2
 
+/* SPI */
+#undef	CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_MMAP
+#define CONFIG_SF_QUAD_RD
+#define CONFIG_SF_DEFAULT_SPEED                48000000
+#define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS             0
+#define CONFIG_SPL_SPI_CS              0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
-- 
1.7.1

[U-Boot] [UBOOT][PATCHv3 7/7] README: qspi usecase and testing documentation.

[Sourav Poddar]

Contains documentation and testing details for qspi flash
interface.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 doc/README.ti_qspi_dra_test |   38 ++++++++++++++++++++++++++++++++++
 doc/README.ti_qspi_flash    |   47 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 85 insertions(+), 0 deletions(-)
 create mode 100644 doc/README.ti_qspi_dra_test
 create mode 100644 doc/README.ti_qspi_flash

diff --git a/doc/README.ti_qspi_dra_test b/doc/README.ti_qspi_dra_test
new file mode 100644
index 0000000..c4540ea
--- /dev/null
+++ b/doc/README.ti_qspi_dra_test
@@ -0,0 +1,38 @@
+-------------------------------------------------
+   Simple steps used to test the QSPI at U-Boot
+-------------------------------------------------
+
+For #1, build the patched U-Boot and load MLO/u-boot.img
+
+----------------------------------
+Boot from another medium like MMC
+----------------------------------
+
+DRA752 EVM # mmc dev 0
+DRA752 EVM # fatload mmc 0 0x82000000 MLO
+DRA752 EVM # fatload mmc 0 0x83000000 u-boot.img
+
+--------------------------------------------------
+Commands to erase/write u-boot/mlo to flash device
+--------------------------------------------------
+
+DRA752 EVM # sf probe 0
+[should detect the S25FL256S serial flash device]
+
+DRA752 EVM # sf erase 0 10000
+DRA752 EVM # sf erase 10000 10000
+DRA752 EVM # sf erase 20000 10000
+DRA752 EVM # sf erase 30000 10000
+DRA752 EVM # sf erase 40000 10000
+DRA752 EVM # sf erase 50000 10000
+DRA752 EVM # sf erase 60000 10000
+
+DRA752 EVM # sf write 82000000 0 10000
+DRA752 EVM # sf write 83000000 20000 70000
+
+For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power
+on. ROM should find the GP header at offset 0 and load/execute SPL. SPL
+then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to
+find a U-Boot image header at offset 0x20000 (set in the config file)
+and proceeds to load that image using the U-Boot image payload offset/size
+from the header. It will then start U-Boot.
diff --git a/doc/README.ti_qspi_flash b/doc/README.ti_qspi_flash
new file mode 100644
index 0000000..1b86d01
--- /dev/null
+++ b/doc/README.ti_qspi_flash
@@ -0,0 +1,47 @@
+QSPI U-boot support
+------------------
+
+Host processor is connected to serial flash device via qpsi
+interface. QSPI is a kind of spi module that allows single,
+dual and quad read access to external spi devices. The module
+has a memory mapped interface which provide direct interface
+for accessing data form external spi devices.
+
+The one QSPI in the device is primarily intended for fast booting
+from Quad SPI flash devices.
+
+Usecase
+-------
+
+MLO/u-boot.img will be flashed from SD/MMC to the flash device
+using serial flash erase and write commands. Then, switch settings
+will be changed to qspi boot. Then, the ROM code will read MLO
+from the predefined location in the flash, where it was flashed and
+execute it after storing it in SDRAM. Then, the MLO will read
+u-boot.img from flash and execute it from SDRAM.
+
+SPI mode
+-------
+SPI mode uses mtd spi framework for transfer and reception of data.
+Can be used in:
+1. Normal mode: use single pin for transfers
+2. Dual Mode: use two pins for transfers.
+3. Quad mode: use four pin for transfer
+
+Memory mapped read mode
+-----------------------
+In this, SPI controller is configured using configuration port and then
+controler is switched to memory mapped port for data read.
+
+Driver
+------
+drivers/qspi/ti_qspi.c
+    - Newly created file which is responsible for configuring the
+	qspi controller and also for providing the low level api which
+	is responsible for transferring the datas from host controller
+	to flash device and vice versa.
+
+Testing
+-------
+A seperated file named README.dra_qspi_test has been created which gives all the
+details about the commands required to test qspi at u-boot level.
-- 
1.7.1

[U-Boot] [UBOOT][PATCHv3 5/7] spi: add TI QSPI driver

[Nobuhiro Iwamatsu]

Hi,

2013/9/18 Sourav Poddar <sourav.poddar@ti.com>:
> From: Matt Porter <matt.porter@linaro.org>
>
> Adds a SPI master driver for the TI QSPI peripheral.
>
> Signed-off-by: Matt Porter <matt.porter@linaro.org>
> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
> [Added quad read support and memory mapped support).
> ---
>  drivers/spi/Makefile  |    1 +
>  drivers/spi/ti_qspi.c |  324 +++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 325 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/spi/ti_qspi.c
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 91d24ce..e5941b0 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
>  COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
>  COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
>  COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
> +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
>  COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>  COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> new file mode 100644
> index 0000000..3e88cf4
> --- /dev/null
> +++ b/drivers/spi/ti_qspi.c
> @@ -0,0 +1,324 @@
> +/*
> + * TI QSPI driver
> + *
> + * Copyright (C) 2013, Texas Instruments, Incorporated
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
> + * GNU General Public License for more details.
> + */

Could you change to  'SPDX-License-Identifier:    GPL-2.0+', please?

Best regards,
  Nobuhiro
-- 
Nobuhiro Iwamatsu

[U-Boot] [UBOOT][PATCHv3 0/7] mtd/spi: add quad/memory mapped read support, add ti qspi controller.

[Jagan Teki]

Hi Sourav,

Can you rebase your changes w.r.t u-boot-spi.git with master-probe branch.
Sorry for the delay, try to send the patches without quad related stuff.

I will prepare a thread for this quad after this release as we did lot
of work last few months back.
Thanks for your help.!!!

On Wed, Sep 18, 2013 at 5:51 PM, Sourav Poddar <sourav.poddar@ti.com> wrote:
> This patch series add support for TI qspi controller and in the process also
> add support for quad read and memory mapped read
> in mtd spi framework.
>
> Testing details:
> Did a boot from qspi mode on DRA7xx.
> Testing details present in the last patch of
> the series.
>
> Currently, TI qpsi controller supports only 16MB access.
> Access for higher MB area will be added later.
>
> v2->v3:
> 1. run checkpatch
> 2. Rearrange the code logically.
> 3. Remove a page read hack.
>
> Matt Porter (3):
>   omap5: add qspi support
>   spi: add TI QSPI driver
>   dra7xx_evm: add SPL API, QSPI, and serial flash support
>
> Ravikumar Kattekola (1):
>   drivers: mtd: :spi: Add quad read support
>
> Sourav Poddar (3):
>   armv7: hw_data: change clock divider setting.
>   driver: mtd: spi: Add memory mapped read support
>   README: qspi usecase and testing documentation.
>
>  arch/arm/cpu/armv7/omap5/hw_data.c     |   10 +-
>  arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
>  arch/arm/include/asm/arch-omap5/omap.h |    3 +
>  arch/arm/include/asm/arch-omap5/spl.h  |    1 +
>  arch/arm/include/asm/omap_common.h     |    1 +
>  board/ti/dra7xx/mux_data.h             |   10 +
>  doc/README.ti_qspi_dra_test            |   38 ++++
>  doc/README.ti_qspi_flash               |   47 +++++
>  drivers/mtd/spi/spansion.c             |    1 +
>  drivers/mtd/spi/spi_flash.c            |  113 +++++++++++-
>  drivers/mtd/spi/spi_flash_internal.h   |    2 +
>  drivers/spi/Makefile                   |    1 +
>  drivers/spi/ti_qspi.c                  |  324 ++++++++++++++++++++++++++++++++
>  include/configs/dra7xx_evm.h           |   20 ++
>  include/spi.h                          |    5 +
>  15 files changed, 575 insertions(+), 2 deletions(-)
>  create mode 100644 doc/README.ti_qspi_dra_test
>  create mode 100644 doc/README.ti_qspi_flash
>  create mode 100644 drivers/spi/ti_qspi.c
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot



-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

[U-Boot] [UBOOT][PATCHv3 5/7] spi: add TI QSPI driver

[Jagan Teki]

Hi Sourav,

Please try to code the driver as specified in below thread!
http://lists.denx.de/pipermail/u-boot/2013-August/160472.html

On Fri, Sep 20, 2013 at 8:21 AM, Nobuhiro Iwamatsu
<nobuhiro.iwamatsu.yj@renesas.com> wrote:
> Hi,
>
> 2013/9/18 Sourav Poddar <sourav.poddar@ti.com>:
>> From: Matt Porter <matt.porter@linaro.org>
>>
>> Adds a SPI master driver for the TI QSPI peripheral.
>>
>> Signed-off-by: Matt Porter <matt.porter@linaro.org>
>> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
>> [Added quad read support and memory mapped support).
>> ---
>>  drivers/spi/Makefile  |    1 +
>>  drivers/spi/ti_qspi.c |  324 +++++++++++++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 325 insertions(+), 0 deletions(-)
>>  create mode 100644 drivers/spi/ti_qspi.c
>>
>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>> index 91d24ce..e5941b0 100644
>> --- a/drivers/spi/Makefile
>> +++ b/drivers/spi/Makefile
>> @@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
>>  COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
>>  COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
>>  COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
>> +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
>>  COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>>  COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
>>
>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>> new file mode 100644
>> index 0000000..3e88cf4
>> --- /dev/null
>> +++ b/drivers/spi/ti_qspi.c
>> @@ -0,0 +1,324 @@
>> +/*
>> + * TI QSPI driver
>> + *
>> + * Copyright (C) 2013, Texas Instruments, Incorporated
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>
> Could you change to  'SPDX-License-Identifier:    GPL-2.0+', please?
>
> Best regards,
>   Nobuhiro
> --
> Nobuhiro Iwamatsu
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot



-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

[U-Boot] [UBOOT][PATCHv3 0/7] mtd/spi: add quad/memory mapped read support, add ti qspi controller.

[Sourav Poddar]

On Thursday 03 October 2013 11:13 PM, Jagan Teki wrote:
> Hi Sourav,
>
> Can you rebase your changes w.r.t u-boot-spi.git with master-probe branch.
> Sorry for the delay, try to send the patches without quad related stuff.
>
Ok. I will rebase and send only ti qspi and memory mapped part.
> I will prepare a thread for this quad after this release as we did lot
> of work last few months back.
> Thanks for your help.!!!
>
Ok.
> On Wed, Sep 18, 2013 at 5:51 PM, Sourav Poddar<sourav.poddar@ti.com>  wrote:
>> This patch series add support for TI qspi controller and in the process also
>> add support for quad read and memory mapped read
>> in mtd spi framework.
>>
>> Testing details:
>> Did a boot from qspi mode on DRA7xx.
>> Testing details present in the last patch of
>> the series.
>>
>> Currently, TI qpsi controller supports only 16MB access.
>> Access for higher MB area will be added later.
>>
>> v2->v3:
>> 1. run checkpatch
>> 2. Rearrange the code logically.
>> 3. Remove a page read hack.
>>
>> Matt Porter (3):
>>    omap5: add qspi support
>>    spi: add TI QSPI driver
>>    dra7xx_evm: add SPL API, QSPI, and serial flash support
>>
>> Ravikumar Kattekola (1):
>>    drivers: mtd: :spi: Add quad read support
>>
>> Sourav Poddar (3):
>>    armv7: hw_data: change clock divider setting.
>>    driver: mtd: spi: Add memory mapped read support
>>    README: qspi usecase and testing documentation.
>>
>>   arch/arm/cpu/armv7/omap5/hw_data.c     |   10 +-
>>   arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
>>   arch/arm/include/asm/arch-omap5/omap.h |    3 +
>>   arch/arm/include/asm/arch-omap5/spl.h  |    1 +
>>   arch/arm/include/asm/omap_common.h     |    1 +
>>   board/ti/dra7xx/mux_data.h             |   10 +
>>   doc/README.ti_qspi_dra_test            |   38 ++++
>>   doc/README.ti_qspi_flash               |   47 +++++
>>   drivers/mtd/spi/spansion.c             |    1 +
>>   drivers/mtd/spi/spi_flash.c            |  113 +++++++++++-
>>   drivers/mtd/spi/spi_flash_internal.h   |    2 +
>>   drivers/spi/Makefile                   |    1 +
>>   drivers/spi/ti_qspi.c                  |  324 ++++++++++++++++++++++++++++++++
>>   include/configs/dra7xx_evm.h           |   20 ++
>>   include/spi.h                          |    5 +
>>   15 files changed, 575 insertions(+), 2 deletions(-)
>>   create mode 100644 doc/README.ti_qspi_dra_test
>>   create mode 100644 doc/README.ti_qspi_flash
>>   create mode 100644 drivers/spi/ti_qspi.c
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>
>

[U-Boot] [UBOOT][PATCHv3 5/7] spi: add TI QSPI driver

[Sourav Poddar]

On Thursday 03 October 2013 11:19 PM, Jagan Teki wrote:
> Hi Sourav,
>
> Please try to code the driver as specified in below thread!
> http://lists.denx.de/pipermail/u-boot/2013-August/160472.html
Ok.
> On Fri, Sep 20, 2013 at 8:21 AM, Nobuhiro Iwamatsu
> <nobuhiro.iwamatsu.yj@renesas.com>  wrote:
>> Hi,
>>
>> 2013/9/18 Sourav Poddar<sourav.poddar@ti.com>:
>>> From: Matt Porter<matt.porter@linaro.org>
>>>
>>> Adds a SPI master driver for the TI QSPI peripheral.
>>>
>>> Signed-off-by: Matt Porter<matt.porter@linaro.org>
>>> Signed-off-by: Sourav Poddar<sourav.poddar@ti.com>
>>> [Added quad read support and memory mapped support).
>>> ---
>>>   drivers/spi/Makefile  |    1 +
>>>   drivers/spi/ti_qspi.c |  324 +++++++++++++++++++++++++++++++++++++++++++++++++
>>>   2 files changed, 325 insertions(+), 0 deletions(-)
>>>   create mode 100644 drivers/spi/ti_qspi.c
>>>
>>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>>> index 91d24ce..e5941b0 100644
>>> --- a/drivers/spi/Makefile
>>> +++ b/drivers/spi/Makefile
>>> @@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
>>>   COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
>>>   COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
>>>   COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
>>> +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
>>>   COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>>>   COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
>>>
>>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>>> new file mode 100644
>>> index 0000000..3e88cf4
>>> --- /dev/null
>>> +++ b/drivers/spi/ti_qspi.c
>>> @@ -0,0 +1,324 @@
>>> +/*
>>> + * TI QSPI driver
>>> + *
>>> + * Copyright (C) 2013, Texas Instruments, Incorporated
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of
>>> + * the License, or (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
>>> + * GNU General Public License for more details.
>>> + */
>> Could you change to  'SPDX-License-Identifier:    GPL-2.0+', please?
>>
>> Best regards,
>>    Nobuhiro
>> --
>> Nobuhiro Iwamatsu
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>
>

[U-Boot] [UBOOT][PATCHv3 0/7] mtd/spi: add quad/memory mapped read support, add ti qspi controller.

[Jagan Teki]

Thanks,

On Thu, Oct 3, 2013 at 11:55 PM, Sourav Poddar <sourav.poddar@ti.com> wrote:
> On Thursday 03 October 2013 11:13 PM, Jagan Teki wrote:
>>
>> Hi Sourav,
>>
>> Can you rebase your changes w.r.t u-boot-spi.git with master-probe branch.
>> Sorry for the delay, try to send the patches without quad related stuff.
>>
> Ok. I will rebase and send only ti qspi and memory mapped part.
>
>> I will prepare a thread for this quad after this release as we did lot
>> of work last few months back.
>> Thanks for your help.!!!
>>
> Ok.
>
>> On Wed, Sep 18, 2013 at 5:51 PM, Sourav Poddar<sourav.poddar@ti.com>
>> wrote:
>>>
>>> This patch series add support for TI qspi controller and in the process
>>> also
>>> add support for quad read and memory mapped read
>>> in mtd spi framework.
>>>
>>> Testing details:
>>> Did a boot from qspi mode on DRA7xx.
>>> Testing details present in the last patch of
>>> the series.
>>>
>>> Currently, TI qpsi controller supports only 16MB access.
>>> Access for higher MB area will be added later.
>>>
>>> v2->v3:
>>> 1. run checkpatch
>>> 2. Rearrange the code logically.
>>> 3. Remove a page read hack.
>>>
>>> Matt Porter (3):
>>>    omap5: add qspi support
>>>    spi: add TI QSPI driver
>>>    dra7xx_evm: add SPL API, QSPI, and serial flash support
>>>
>>> Ravikumar Kattekola (1):
>>>    drivers: mtd: :spi: Add quad read support
>>>
>>> Sourav Poddar (3):
>>>    armv7: hw_data: change clock divider setting.
>>>    driver: mtd: spi: Add memory mapped read support
>>>    README: qspi usecase and testing documentation.
>>>
>>>   arch/arm/cpu/armv7/omap5/hw_data.c     |   10 +-
>>>   arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
>>>   arch/arm/include/asm/arch-omap5/omap.h |    3 +
>>>   arch/arm/include/asm/arch-omap5/spl.h  |    1 +
>>>   arch/arm/include/asm/omap_common.h     |    1 +
>>>   board/ti/dra7xx/mux_data.h             |   10 +
>>>   doc/README.ti_qspi_dra_test            |   38 ++++
>>>   doc/README.ti_qspi_flash               |   47 +++++
>>>   drivers/mtd/spi/spansion.c             |    1 +
>>>   drivers/mtd/spi/spi_flash.c            |  113 +++++++++++-
>>>   drivers/mtd/spi/spi_flash_internal.h   |    2 +
>>>   drivers/spi/Makefile                   |    1 +
>>>   drivers/spi/ti_qspi.c                  |  324
>>> ++++++++++++++++++++++++++++++++
>>>   include/configs/dra7xx_evm.h           |   20 ++
>>>   include/spi.h                          |    5 +
>>>   15 files changed, 575 insertions(+), 2 deletions(-)
>>>   create mode 100644 doc/README.ti_qspi_dra_test
>>>   create mode 100644 doc/README.ti_qspi_flash
>>>   create mode 100644 drivers/spi/ti_qspi.c
>>>
>>> _______________________________________________
>>> U-Boot mailing list
>>> U-Boot at lists.denx.de
>>> http://lists.denx.de/mailman/listinfo/u-boot
>>
>>
>>
>



-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki