From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Tue, 15 Oct 2013 13:47:23 -0600
Subject: [U-Boot] [PATCH] Tegra114: spl: Set system clock to clk_m
In-Reply-To: <CA+m5__Kh+DES2Zhqf=Y4Us5+Ovnu+7DxETCbch9ZfGXRDJTDyw@mail.gmail.com>
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	<CA+m5__Kh+DES2Zhqf=Y4Us5+Ovnu+7DxETCbch9ZfGXRDJTDyw@mail.gmail.com>
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On 10/15/2013 01:37 PM, Tom Warren wrote:
> Jimmy - please answer Stephen's questions below, and/or correct my answers.
> 
> 
> On Tue, Oct 8, 2013 at 2:18 PM, Stephen Warren <swarren@wwwdotorg.org
> <mailto:swarren@wwwdotorg.org>> wrote:
> 
>     On 10/07/2013 03:17 PM, Tom Warren wrote:
>     > From: Jimmy Zhang <jimmzhang at nvidia.com <mailto:jimmzhang@nvidia.com>>
>     >
>     > Based on Tegra114 TRM, system clock can run up to 275MHz. On power on,
> 
>     Which exact clock is "system clock"?
> 
>  
> In the T1x4 TRM, SCLK is the system clock that drives the AVP/COP. It
> appears to have 8 possible sources (PLLP, CLK_M, etc.). See the settings
> in CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0 (offset 0x28 in the CAR block).

My comment was really a request to ammend the commit description to use
the actual clock name from the TRM (sclk??) rather than a description of
the clock (system clock). Then, it'd be clear which clock it was talking
about.