From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Fri, 18 Oct 2013 11:34:58 -0700
Subject: [U-Boot] [PATCH v4 07/11] mpc8xxx: set x2 DDR3 refresh rate if
 SPD config requires it
In-Reply-To: <1382089644-14595-8-git-send-email-valentin.longchamp@keymile.com>
References: <1382089644-14595-1-git-send-email-valentin.longchamp@keymile.com>
	<1382089644-14595-8-git-send-email-valentin.longchamp@keymile.com>
Message-ID: <52617F52.7010903@freescale.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On 10/18/2013 02:47 AM, Valentin Longchamp wrote:
> If the DDR3 module supports industrial temperature range and requires
> the x2 refresh rate for that temp range, the refresh period must be
> 3.9us instead of 7.8 us.
> 
> This was successfuly tested on kmp204x board with some MT41K128M16 DDR3
> RAM chips (no module used, chips directly soldered on board with an SPD
> EEPROM).
> 
> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
> 
> ---
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - when refresh rate gets halved for extended range temperature
>   operations, the srt bit in the mode register 2 is set.
> 

Applied to 85xx/next, pending merge to 85xx/master.

York