From mboxrd@z Thu Jan  1 00:00:00 1970
From: Zhang Haijun <b42677@freescale.com>
Date: Mon, 21 Oct 2013 17:23:40 +0800
Subject: [U-Boot] [PATCH] fsl_esdhc: Add Auto command 12 interrupt bit
 detecting
In-Reply-To: <5264F187.7060707@denx.de>
References: <1381571453-7814-1-git-send-email-Haijun.Zhang@freescale.com>
	<5264E492.2070606@freescale.com> <5264F187.7060707@denx.de>
Message-ID: <5264F29C.6070909@freescale.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

Hi, Babic

Thanks.

This patch is test on PPC.


Regards,
Haijun


? 2013/10/21 17:19, Stefano Babic ??:
> Hi,
>
> On 21/10/2013 10:23, Zhang Haijun wrote:
>> Hi, all
>>
>> Who can give some comments?
> I put Antonius in CC, he's the MMC custodian.
>
>
> The driver is for both PPC and i.MX. On which platform do you test these
> changes ?
>
> Best regards,
> Stefano Babic
>
>>
>> ? 2013/10/12 17:50, Haijun Zhang ??:
>>> When Auto-CMD12 is used, the corresponding interrupt and error bit
>>> should be enabled and set to reflect auto cmd 12 error.
>>> Also add other command error detecting, like command index error,
>>> CRC error etc. Without this command error bit set system will hang
>>> due to the while loop.
>>>
>>> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
>>> ---
>>>   drivers/mmc/fsl_esdhc.c | 10 +++++-----
>>>   include/fsl_esdhc.h     |  3 ++-
>>>   2 files changed, 7 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
>>> index dc1d002..5aa592b 100644
>>> --- a/drivers/mmc/fsl_esdhc.c
>>> +++ b/drivers/mmc/fsl_esdhc.c
>>> @@ -342,13 +342,13 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
>>>   #endif
>>>   
>>>   	/* Wait for the command to complete */
>>> -	while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
>>> +	while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | CMD_ERR)))
>>>   		;
>>>   
>>>   	irqstat = esdhc_read32(&regs->irqstat);
>>>   
>>>   	/* Reset CMD and DATA portions on error */
>>> -	if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
>>> +	if (irqstat & CMD_ERR) {
>>>   		esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
>>>   			      SYSCTL_RSTC);
>>>   		while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
>>> @@ -363,12 +363,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
>>>   		}
>>>   	}
>>>   
>>> -	if (irqstat & CMD_ERR)
>>> -		return COMM_ERR;
>>> -
>>>   	if (irqstat & IRQSTAT_CTOE)
>>>   		return TIMEOUT;
>>>   
>>> +	if (irqstat & CMD_ERR)
>>> +		return COMM_ERR;
>>> +
>>>   	/* Workaround for ESDHC errata ENGcm03648 */
>>>   	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
>>>   		int timeout = 2500;
>>> diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
>>> index 67d6057..37dbe27 100644
>>> --- a/include/fsl_esdhc.h
>>> +++ b/include/fsl_esdhc.h
>>> @@ -62,7 +62,8 @@
>>>   #define IRQSTAT_TC		(0x00000002)
>>>   #define IRQSTAT_CC		(0x00000001)
>>>   
>>> -#define CMD_ERR		(IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
>>> +#define CMD_ERR		(IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE | \
>>> +				IRQSTAT_CTOE | IRQSTAT_AC12E)
>>>   #define DATA_ERR	(IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
>>>   				IRQSTAT_DMAE)
>>>   #define DATA_COMPLETE	(IRQSTAT_TC | IRQSTAT_DINT)
>

-- 
Thanks & Regards
Haijun.