From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Wed, 30 Oct 2013 09:59:16 +0100 Subject: [U-Boot] [PATCH] video: ipu_disp: Fix clock polarity logic In-Reply-To: <1383068781-9299-1-git-send-email-fabio.estevam@freescale.com> References: <1383068781-9299-1-git-send-email-fabio.estevam@freescale.com> Message-ID: <5270CA64.6060406@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 29/10/2013 18:46, Fabio Estevam wrote: > Currently the HDMI splash screen image quality on mx6solo does not show a > very stable image. > > By comparing the IPU driver from U-boot with the one from FSL 4.1.0 BSP, > we can see that there is an inverted logic for setting the DI_GEN_POL_CLK bit. > > From FSL BSP [1] we have: > > if (!sig.clk_pol) > di_gen |= DI_GEN_POLARITY_DISP_CLK; > > Applying the same logic into U-boot fixes the HDMI image stability. > > [1] git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/mxc/ipu3/ipu_disp.c?h=imx_3.0.35_4.1.0 > > Signed-off-by: Fabio Estevam > --- > drivers/video/ipu_disp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c > index 2e91356..22ac142 100644 > --- a/drivers/video/ipu_disp.c > +++ b/drivers/video/ipu_disp.c > @@ -1178,7 +1178,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, > if (sig.Vsync_pol) > di_gen |= DI_GEN_POLARITY_3; > > - if (sig.clk_pol) > + if (!sig.clk_pol) > di_gen |= DI_GEN_POL_CLK; > > } > Acked-by: Stefano Babic Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================