[U-Boot] [PATCH 01/34] zynq: Enable CONFIG_FIT_VERBOSE

[U-Boot] [PATCH 01/34] zynq: Enable CONFIG_FIT_VERBOSE

[Jagannadha Sutradharudu Teki]

Enabled fit_format_{error,warning}()

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 4c6e6e8..a6dbd0e 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -127,6 +127,7 @@
 
 /* OF */
 #define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
 #define CONFIG_OF_LIBFDT
 
 /* Commands */
-- 
1.8.3

[U-Boot] [PATCH 02/34] zynq: Enable Boot FreeBSD/vxWorks

[Jagannadha Sutradharudu Teki]

This enabled Boot FreeBSD/vxWorks from an ELF image support

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index a6dbd0e..6ac1350 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -130,6 +130,13 @@
 #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
 #define CONFIG_OF_LIBFDT
 
+/* Boot FreeBSD/vxWorks from an ELF image */
+#if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
+# define CONFIG_API
+# define CONFIG_CMD_ELF
+# define CONFIG_SYS_MMC_MAX_DEVICE	1
+#endif
+
 /* Commands */
 #include <config_cmd_default.h>
 
-- 
1.8.3

[U-Boot] [PATCH 03/34] zynq: Cleanup on miscellaneous configs

[Jagannadha Sutradharudu Teki]

Cleanup on miscellaneous configurable options:
- Rename SYS_PROMPT as "zynq-uboot"
- Add comment
- Re-order configs

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq.h | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 6ac1350..f9a071d 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -111,19 +111,21 @@
 						CONFIG_SYS_INIT_RAM_SIZE - \
 						GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_SYS_PROMPT	"U-Boot> "
-#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_PROMPT		"zynq-uboot> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_MAXARGS		15 /* max number of command args */
+#define CONFIG_SYS_CBSIZE		256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 
 #define CONFIG_SYS_LOAD_ADDR	0
-#define CONFIG_SYS_MAXARGS	15 /* max number of command args */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
 
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /* OF */
 #define CONFIG_FIT
-- 
1.8.3

[U-Boot] [PATCH 03/34] zynq: Cleanup on miscellaneous configs

[Tom Rini]

On Tue, Nov 05, 2013 at 11:16:24PM +0530, Jagannadha Sutradharudu Teki wrote:

> -#define CONFIG_SYS_PROMPT	"U-Boot> "

I'm not a fan of removing generic looking prompts, we should rely on
other things to determine what we're on.

> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

Not needed now, this is the default.

-- 
Tom
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[U-Boot] [PATCH 03/34] zynq: Cleanup on miscellaneous configs

[Michal Simek]

On 11/05/2013 08:45 PM, Tom Rini wrote:
> On Tue, Nov 05, 2013 at 11:16:24PM +0530, Jagannadha Sutradharudu Teki wrote:
> 
>> -#define CONFIG_SYS_PROMPT	"U-Boot> "
> 
> I'm not a fan of removing generic looking prompts, we should rely on
> other things to determine what we're on.

Isn't it this generic looking prompt?

include/config_fallbacks.h:56:#ifndef CONFIG_SYS_PROMPT
include/config_fallbacks.h:57:#define CONFIG_SYS_PROMPT "=> "


>> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> 
> Not needed now, this is the default.

yep.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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[U-Boot] [PATCH 04/34] zynq: Cleanup on memory configs

[Jagannadha Sutradharudu Teki]

Cleanup on memory configuration options:
- Add comment
- Re-order configs

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq.h | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index f9a071d..8ccc667 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -13,14 +13,6 @@
 /* CPU clock */
 #define CONFIG_CPU_FREQ_HZ	800000000
 
-/* Ram */
-#define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_SYS_TEXT_BASE		0
-#define CONFIG_SYS_SDRAM_BASE		0
-#define CONFIG_SYS_SDRAM_SIZE		0x40000000
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
-
 /* The following table includes the supported baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
@@ -105,11 +97,6 @@
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_SYS_MALLOC_LEN		0x400000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-						CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_PROMPT		"zynq-uboot> "
@@ -126,7 +113,21 @@
 
 #define CONFIG_SYS_LOAD_ADDR	0
 
+/* Physical Memory map */
+#define CONFIG_SYS_TEXT_BASE		0
 
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
 /* OF */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
-- 
1.8.3

[U-Boot] [PATCH 05/34] zynq: Minor config cleanup

[Jagannadha Sutradharudu Teki]

Cleanups mostly on:
- Add comments
- Re-order configs
- Remove #define CONFIG_ZYNQ_SDHCI

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq.h | 76 ++++++++++++++++++++++++++------------------------
 1 file changed, 39 insertions(+), 37 deletions(-)

diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 8ccc667..abeb2da 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -7,33 +7,51 @@
 #ifndef __CONFIG_ZYNQ_H
 #define __CONFIG_ZYNQ_H
 
-#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
+/* High Level configuration Options */
+#define CONFIG_ARMV7
 #define CONFIG_ZYNQ
 
 /* CPU clock */
-#define CONFIG_CPU_FREQ_HZ	800000000
+#ifndef CONFIG_CPU_FREQ_HZ
+# define CONFIG_CPU_FREQ_HZ	800000000
+#endif
 
+/* Serial drivers */
+#define CONFIG_BAUDRATE		115200
 /* The following table includes the supported baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
-#define CONFIG_BAUDRATE		115200
-
-/* XPSS Serial driver */
+/* Zynq Serial driver */
 #define CONFIG_ZYNQ_SERIAL
 #define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0001000
 #define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
 #define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
 
+/* DCC driver */
+#if defined(CONFIG_ZYNQ_DCC)
+# define CONFIG_ARM_DCC
+# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
+#endif
+
 /* Ethernet driver */
 #define CONFIG_NET_MULTI
 #define CONFIG_ZYNQ_GEM
 #define CONFIG_ZYNQ_GEM0
 #define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
 
-#define CONFIG_ZYNQ_SDHCI
-#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_SPI
+/* SPI */
+#ifdef CONFIG_ZYNQ_SPI
+# define CONFIG_SPI_FLASH
+# define CONFIG_SPI_FLASH_SST
+# define CONFIG_CMD_SF
+#endif
+
+/* NOR */
+#define CONFIG_SYS_NO_FLASH
 
+#define CONFIG_ZYNQ_SDHCI0
 /* MMC */
 #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
 # define CONFIG_MMC
@@ -48,7 +66,6 @@
 #endif
 
 #define CONFIG_ZYNQ_I2C0
-
 /* I2C */
 #if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
 # define CONFIG_CMD_I2C
@@ -58,26 +75,6 @@
 # define CONFIG_SYS_I2C_SLAVE		1
 #endif
 
-#if defined(CONFIG_ZYNQ_DCC)
-# define CONFIG_ARM_DCC
-# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
-#endif
-
-#define CONFIG_ZYNQ_SPI
-
-/* SPI */
-#ifdef CONFIG_ZYNQ_SPI
-# define CONFIG_SPI_FLASH
-# define CONFIG_SPI_FLASH_SST
-# define CONFIG_CMD_SF
-#endif
-
-/* Enable the PL to be downloaded */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_ZYNQPL
-#define CONFIG_CMD_FPGA
-
 #define CONFIG_BOOTP_SERVERIP
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
@@ -91,12 +88,9 @@
 #define CONFIG_PHY_MARVELL
 
 /* Environment */
+#define CONFIG_ENV_SIZE		0x10000 /* Env. sector size */
 #define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x10000
-
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_SYS_MALLOC_LEN		0x400000
+#define CONFIG_SYS_LOAD_ADDR	0
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_PROMPT		"zynq-uboot> "
@@ -111,8 +105,6 @@
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 
-#define CONFIG_SYS_LOAD_ADDR	0
-
 /* Physical Memory map */
 #define CONFIG_SYS_TEXT_BASE		0
 
@@ -123,15 +115,25 @@
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
 
+#define CONFIG_SYS_MALLOC_LEN		0x400000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
 					CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
-/* OF */
+
+/* Enable the PL to be downloaded */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_ZYNQPL
+#define CONFIG_CMD_FPGA
+
+/* Open Firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
+/* FIT support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
-#define CONFIG_OF_LIBFDT
 
 /* Boot FreeBSD/vxWorks from an ELF image */
 #if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
-- 
1.8.3

[U-Boot] [PATCH 06/34] zynq: Enable cache options

[Jagannadha Sutradharudu Teki]

- Enable cache command
- Turn-off L2 cache
- Turn-on D-cache

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index abeb2da..f32008b 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -16,6 +16,16 @@
 # define CONFIG_CPU_FREQ_HZ	800000000
 #endif
 
+/* Cache options */
+#define CONFIG_CMD_CACHE
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+# define CONFIG_SYS_L2_PL310
+# define CONFIG_SYS_PL310_BASE		0xf8f02000
+#endif
+
 /* Serial drivers */
 #define CONFIG_BAUDRATE		115200
 /* The following table includes the supported baudrates */
-- 
1.8.3

[U-Boot] [PATCH 07/34] zynq: Add UART0, UART1 configs support

[Jagannadha Sutradharudu Teki]

Zynq uart controller support two serial ports like
CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
enabled both so-that the respective board will define
these macros based on their usage.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq.h | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index f32008b..1bcb28d 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -33,10 +33,22 @@
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
 /* Zynq Serial driver */
-#define CONFIG_ZYNQ_SERIAL
-#define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0001000
-#define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
-#define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
+#define CONFIG_ZYNQ_SERIAL_UART1
+#ifdef CONFIG_ZYNQ_SERIAL_UART0
+# define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0000000
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
+# define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
+#endif
+
+#ifdef CONFIG_ZYNQ_SERIAL_UART1
+# define CONFIG_ZYNQ_SERIAL_BASEADDR1	0xE0001000
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE1	CONFIG_BAUDRATE
+# define CONFIG_ZYNQ_SERIAL_CLOCK1	50000000
+#endif
+
+#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1)
+# define CONFIG_ZYNQ_SERIAL
+#endif
 
 /* DCC driver */
 #if defined(CONFIG_ZYNQ_DCC)
-- 
1.8.3

[U-Boot] [PATCH 07/34] zynq: Add UART0, UART1 configs support

[Dinh Nguyen]

On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
> Zynq uart controller support two serial ports like
> CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
> enabled both so-that the respective board will define
> these macros based on their usage.
>
> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
> ---
>  include/configs/zynq.h | 20 ++++++++++++++++----
>  1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/include/configs/zynq.h b/include/configs/zynq.h
> index f32008b..1bcb28d 100644
> --- a/include/configs/zynq.h
> +++ b/include/configs/zynq.h
> @@ -33,10 +33,22 @@
>  	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
>  
>  /* Zynq Serial driver */
> -#define CONFIG_ZYNQ_SERIAL
> -#define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0001000
> -#define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
> -#define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
> +#define CONFIG_ZYNQ_SERIAL_UART1
> +#ifdef CONFIG_ZYNQ_SERIAL_UART0
> +# define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0000000
> +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
Why couldn't you just use CONFIG_BAUDRATE? Why do you need to add
another define?

Dinh
> +# define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
> +#endif
> +
> +#ifdef CONFIG_ZYNQ_SERIAL_UART1
> +# define CONFIG_ZYNQ_SERIAL_BASEADDR1	0xE0001000
> +# define CONFIG_ZYNQ_SERIAL_BAUDRATE1	CONFIG_BAUDRATE
> +# define CONFIG_ZYNQ_SERIAL_CLOCK1	50000000
> +#endif
> +
> +#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1)
> +# define CONFIG_ZYNQ_SERIAL
> +#endif
>  
>  /* DCC driver */
>  #if defined(CONFIG_ZYNQ_DCC)

[U-Boot] [PATCH 07/34] zynq: Add UART0, UART1 configs support

[Michal Simek]

On 11/06/2013 05:17 AM, Dinh Nguyen wrote:
> 
> On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
>> Zynq uart controller support two serial ports like
>> CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
>> enabled both so-that the respective board will define
>> these macros based on their usage.
>>
>> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
>> ---
>>  include/configs/zynq.h | 20 ++++++++++++++++----
>>  1 file changed, 16 insertions(+), 4 deletions(-)
>>
>> diff --git a/include/configs/zynq.h b/include/configs/zynq.h
>> index f32008b..1bcb28d 100644
>> --- a/include/configs/zynq.h
>> +++ b/include/configs/zynq.h
>> @@ -33,10 +33,22 @@
>>  	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
>>  
>>  /* Zynq Serial driver */
>> -#define CONFIG_ZYNQ_SERIAL
>> -#define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0001000
>> -#define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
>> -#define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
>> +#define CONFIG_ZYNQ_SERIAL_UART1
>> +#ifdef CONFIG_ZYNQ_SERIAL_UART0
>> +# define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0000000
>> +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
> Why couldn't you just use CONFIG_BAUDRATE? Why do you need to add
> another define?

If we start to use the same CONFIG_BAUDRATE(or better gd->baudrate)
in the driver then we lose config options to setup different baudrate
for every single device.

I haven't seen any code for SERIAL_MULTI if you want to configure
2 serial drivers but on different baudrate.
If there is better way how to do it please let us know.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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[U-Boot] [PATCH 07/34] zynq: Add UART0, UART1 configs support

[Dinh Nguyen]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512


On 11/6/13 12:45 AM, Michal Simek wrote:
> On 11/06/2013 05:17 AM, Dinh Nguyen wrote:
>>
>> On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
>>> Zynq uart controller support two serial ports like
>>> CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
>>> enabled both so-that the respective board will define
>>> these macros based on their usage.
>>>
>>> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
>>> ---
>>>  include/configs/zynq.h | 20 ++++++++++++++++----
>>>  1 file changed, 16 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/include/configs/zynq.h b/include/configs/zynq.h
>>> index f32008b..1bcb28d 100644
>>> --- a/include/configs/zynq.h
>>> +++ b/include/configs/zynq.h
>>> @@ -33,10 +33,22 @@
>>>      {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200,
230400}
>>> 
>>>  /* Zynq Serial driver */
>>> -#define CONFIG_ZYNQ_SERIAL
>>> -#define CONFIG_ZYNQ_SERIAL_BASEADDR0    0xE0001000
>>> -#define CONFIG_ZYNQ_SERIAL_BAUDRATE0    CONFIG_BAUDRATE
>>> -#define CONFIG_ZYNQ_SERIAL_CLOCK0    50000000
>>> +#define CONFIG_ZYNQ_SERIAL_UART1
>>> +#ifdef CONFIG_ZYNQ_SERIAL_UART0
>>> +# define CONFIG_ZYNQ_SERIAL_BASEADDR0    0xE0000000
>>> +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0    CONFIG_BAUDRATE
>> Why couldn't you just use CONFIG_BAUDRATE? Why do you need to add
>> another define?
>
> If we start to use the same CONFIG_BAUDRATE(or better gd->baudrate)
> in the driver then we lose config options to setup different baudrate
> for every single device.
>
> I haven't seen any code for SERIAL_MULTI if you want to configure
> 2 serial drivers but on different baudrate.
> If there is better way how to do it please let us know.
I guess the question then is what would be the use case for supporting
different baudrates on different device?

Dinh
>
>
> Thanks,
> Michal
>

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[U-Boot] [PATCH 07/34] zynq: Add UART0, UART1 configs support

[Michal Simek]

On 11/06/2013 02:50 PM, Dinh Nguyen wrote:
> 
> 
> On 11/6/13 12:45 AM, Michal Simek wrote:
>> On 11/06/2013 05:17 AM, Dinh Nguyen wrote:
>>>
>>> On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
>>>> Zynq uart controller support two serial ports like
>>>> CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
>>>> enabled both so-that the respective board will define
>>>> these macros based on their usage.
>>>>
>>>> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
>>>> ---
>>>>  include/configs/zynq.h | 20 ++++++++++++++++----
>>>>  1 file changed, 16 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/include/configs/zynq.h b/include/configs/zynq.h
>>>> index f32008b..1bcb28d 100644
>>>> --- a/include/configs/zynq.h
>>>> +++ b/include/configs/zynq.h
>>>> @@ -33,10 +33,22 @@
>>>>      {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200,
> 230400}
>>>>
>>>>  /* Zynq Serial driver */
>>>> -#define CONFIG_ZYNQ_SERIAL
>>>> -#define CONFIG_ZYNQ_SERIAL_BASEADDR0    0xE0001000
>>>> -#define CONFIG_ZYNQ_SERIAL_BAUDRATE0    CONFIG_BAUDRATE
>>>> -#define CONFIG_ZYNQ_SERIAL_CLOCK0    50000000
>>>> +#define CONFIG_ZYNQ_SERIAL_UART1
>>>> +#ifdef CONFIG_ZYNQ_SERIAL_UART0
>>>> +# define CONFIG_ZYNQ_SERIAL_BASEADDR0    0xE0000000
>>>> +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0    CONFIG_BAUDRATE
>>> Why couldn't you just use CONFIG_BAUDRATE? Why do you need to add
>>> another define?
> 
>> If we start to use the same CONFIG_BAUDRATE(or better gd->baudrate)
>> in the driver then we lose config options to setup different baudrate
>> for every single device.
> 
>> I haven't seen any code for SERIAL_MULTI if you want to configure
>> 2 serial drivers but on different baudrate.
>> If there is better way how to do it please let us know.
> I guess the question then is what would be the use case for supporting
> different baudrates on different device?

I don't have any particular case in my mind but based on my experience
with various customer they could have intention to replace old subsystem
by fpga and one serial console can go to standard output which is logged
by default and different serial output for debug purpose and both
can run on different baudrates.

I just think that with SERIAL_MULTI support various baudrate should be supported
and doing it through macros is one way to go.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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[U-Boot] [PATCH 07/34] zynq: Add UART0, UART1 configs support

[Dinh Nguyen]

On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
> Zynq uart controller support two serial ports like
> CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
> enabled both so-that the respective board will define
> these macros based on their usage.
>
> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
> ---
>  include/configs/zynq.h | 20 ++++++++++++++++----
>  1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/include/configs/zynq.h b/include/configs/zynq.h
> index f32008b..1bcb28d 100644
> --- a/include/configs/zynq.h
> +++ b/include/configs/zynq.h
> @@ -33,10 +33,22 @@
>  	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
>  
>  /* Zynq Serial driver */
> -#define CONFIG_ZYNQ_SERIAL
> -#define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0001000
> -#define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
> -#define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
> +#define CONFIG_ZYNQ_SERIAL_UART1
> +#ifdef CONFIG_ZYNQ_SERIAL_UART0
> +# define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0000000
> +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
Why can't the driver just make use of CONFIG_BAUDRATE? Why do you need
to add another
define?

Dinh
> +# define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
> +#endif
> +
> +#ifdef CONFIG_ZYNQ_SERIAL_UART1
> +# define CONFIG_ZYNQ_SERIAL_BASEADDR1	0xE0001000
> +# define CONFIG_ZYNQ_SERIAL_BAUDRATE1	CONFIG_BAUDRATE
> +# define CONFIG_ZYNQ_SERIAL_CLOCK1	50000000
> +#endif
> +
> +#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1)
> +# define CONFIG_ZYNQ_SERIAL
> +#endif
>  
>  /* DCC driver */
>  #if defined(CONFIG_ZYNQ_DCC)

[U-Boot] [PATCH 08/34] zynq: Add GEM0, GEM1 configs support

[Jagannadha Sutradharudu Teki]

Zynq ethernet controller support two GEM's like
CONFIG_ZYNQ_GEM0 and CONFIG_ZYNQ_GEM1 enabled
both so-that the respective board will define
these macros based on their usage.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq.h | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 1bcb28d..680d503 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -57,10 +57,16 @@
 #endif
 
 /* Ethernet driver */
-#define CONFIG_NET_MULTI
-#define CONFIG_ZYNQ_GEM
 #define CONFIG_ZYNQ_GEM0
 #define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
+#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1)
+# define CONFIG_NET_MULTI
+# define CONFIG_ZYNQ_GEM
+# define CONFIG_MII
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_PHYLIB
+# define CONFIG_PHY_MARVELL
+#endif
 
 #define CONFIG_ZYNQ_SPI
 /* SPI */
@@ -103,12 +109,6 @@
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_MAY_FAIL
 
-/* MII and Phylib */
-#define CONFIG_MII
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MARVELL
-
 /* Environment */
 #define CONFIG_ENV_SIZE		0x10000 /* Env. sector size */
 #define CONFIG_ENV_IS_NOWHERE
-- 
1.8.3

[U-Boot] [PATCH 09/34] zynq-common: Rename zynq with zynq-common

[Jagannadha Sutradharudu Teki]

zynq.h -> zynq-common.h, zynq-common is Common
configuration options for all Zynq boards.

zynq.h is no longer exists hense removed from boards.cfg

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 boards.cfg                                | 2 --
 include/configs/{zynq.h => zynq-common.h} | 9 ++++++---
 2 files changed, 6 insertions(+), 5 deletions(-)
 rename include/configs/{zynq.h => zynq-common.h} (95%)

diff --git a/boards.cfg b/boards.cfg
index 5e10125..058ca3f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -344,8 +344,6 @@ Active  arm         armv7          socfpga     altera          socfpga
 Active  arm         armv7          u8500       st-ericsson     snowball            snowball                             -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
 Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
 Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
-Active  arm         armv7          zynq        xilinx          zynq                zynq                                 -                                                                                                                                 Michal Simek <monstr@monstr.eu>
-Active  arm         armv7          zynq        xilinx          zynq                zynq_dcc                             zynq:ZYNQ_DCC                                                                                                                     Michal Simek <monstr@monstr.eu>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq.h b/include/configs/zynq-common.h
similarity index 95%
rename from include/configs/zynq.h
rename to include/configs/zynq-common.h
index 680d503..438215b 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq-common.h
@@ -1,11 +1,14 @@
 /*
  * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Common configuration options for all Zynq boards.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_ZYNQ_H
-#define __CONFIG_ZYNQ_H
+#ifndef __CONFIG_ZYNQ_COMMON_H
+#define __CONFIG_ZYNQ_COMMON_H
 
 /* High Level configuration Options */
 #define CONFIG_ARMV7
@@ -171,4 +174,4 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
-#endif /* __CONFIG_ZYNQ_H */
+#endif /* __CONFIG_ZYNQ_COMMON_H */
-- 
1.8.3

[U-Boot] [PATCH 10/34] spi: Add zynq qspi controller driver

[Jagannadha Sutradharudu Teki]

Zynq qspi controller driver supports single bus
with singe chipselect.

Zynq qspi can be operated in below connection modes
- single qspi
- dual qspi, with dual stacked
- dual qspi, with dual parallel

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 arch/arm/include/asm/arch-zynq/hardware.h |   1 +
 drivers/spi/Makefile                      |   1 +
 drivers/spi/zynq_qspi.c                   | 447 ++++++++++++++++++++++++++++++
 3 files changed, 449 insertions(+)
 create mode 100644 drivers/spi/zynq_qspi.c

diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index cd69677..05870ae 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -19,6 +19,7 @@
 #define ZYNQ_I2C_BASEADDR1		0xE0005000
 #define ZYNQ_SPI_BASEADDR0		0xE0006000
 #define ZYNQ_SPI_BASEADDR1		0xE0007000
+#define ZYNQ_QSPI_BASEADDR		0xE000D000
 #define ZYNQ_DDRC_BASEADDR		0xF8006000
 
 /* Reflect slcr offsets */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 27902fe..5fafee0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
+obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
new file mode 100644
index 0000000..f38ebca
--- /dev/null
+++ b/drivers/spi/zynq_qspi.c
@@ -0,0 +1,447 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Zynq PS Quad-SPI(QSPI) controller driver (master mode only)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+/* zynq spi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
+#define ZYNQ_QSPI_CR_IFMODE_MASK	(1 << 31)	/* Flash intrface mode*/
+#define ZYNQ_QSPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
+#define ZYNQ_QSPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
+#define ZYNQ_QSPI_CR_PCS_MASK		(1 << 10)	/* Peri chip select */
+#define ZYNQ_QSPI_CR_FW_MASK		(0x3 << 6)	/* FIFO width */
+#define ZYNQ_QSPI_CR_BRD_MASK		(0x7 << 3)	/* Baud rate div */
+#define ZYNQ_QSPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
+#define ZYNQ_QSPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
+#define ZYNQ_QSPI_CR_MSTREN_MASK	(1 << 0)	/* Mode select */
+#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	(1 << 4)	/* RX_FIFO_not_empty */
+#define ZYNQ_QSPI_IXR_TXOW_MASK		(1 << 2)	/* TX_FIFO_not_full */
+#define ZYNQ_QSPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
+#define ZYNQ_QSPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
+
+/* QSPI Transmit Data Register */
+#define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C /* Transmit 4-byte inst */
+#define ZYNQ_QSPI_TXD_00_01_OFFSET	0x80 /* Transmit 1-byte inst */
+#define ZYNQ_QSPI_TXD_00_10_OFFSET	0x84 /* Transmit 2-byte inst */
+#define ZYNQ_QSPI_TXD_00_11_OFFSET	0x88 /* Transmit 3-byte inst */
+
+/* Definitions of the flash commands - Flash insts in ascending order */
+#define ZYNQ_QSPI_FLASH_INST_WRSR	0x01	/* Write status register */
+#define ZYNQ_QSPI_FLASH_INST_PP		0x02	/* Page program */
+#define ZYNQ_QSPI_FLASH_INST_WRDS	0x04	/* Write disable */
+#define ZYNQ_QSPI_FLASH_INST_RDSR1	0x05	/* Read status register 1 */
+#define ZYNQ_QSPI_FLASH_INST_WREN	0x06	/* Write enable */
+#define ZYNQ_QSPI_FLASH_INST_AFR	0x0B	/* Fast read data bytes */
+#define ZYNQ_QSPI_FLASH_INST_BE_4K	0x20	/* Erase 4KiB block */
+#define ZYNQ_QSPI_FLASH_INST_RDSR2	0x35	/* Read status register 2 */
+#define ZYNQ_QSPI_FLASH_INST_BE_32K	0x52	/* Erase 32KiB block */
+#define ZYNQ_QSPI_FLASH_INST_RDID	0x9F	/* Read JEDEC ID */
+#define ZYNQ_QSPI_FLASH_INST_SE		0xD8	/* Sector erase (usually 64KB)*/
+
+#define ZYNQ_QSPI_FIFO_DEPTH		63
+#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
+#define CONFIG_SYS_ZYNQ_QSPI_WAIT	CONFIG_SYS_HZ/100	/* 10 ms */
+#endif
+
+/* zynq qspi register set */
+struct zynq_qspi_regs {
+	u32 cr;		/* 0x00 */
+	u32 isr;	/* 0x04 */
+	u32 ier;	/* 0x08 */
+	u32 idr;	/* 0x0C */
+	u32 imr;	/* 0x10 */
+	u32 enr;	/* 0x14 */
+	u32 dr;		/* 0x18 */
+	u32 txd0r;	/* 0x1C */
+	u32 rxdr;	/* 0x20 */
+	u32 sicr;	/* 0x24 */
+	u32 txftr;	/* 0x28 */
+	u32 rxftr;	/* 0x2C */
+	u32 gpior;	/* 0x30 */
+	u32 reserved0[19];
+	u32 txd1r;	/* 0x80 */
+	u32 txd2r;	/* 0x84 */
+	u32 txd3r;	/* 0x88 */
+};
+
+/*
+ * struct zynq_qspi_inst_format - Defines qspi flash instruction format
+ * @inst:	Instruction code
+ * @inst_size:	Size of the instruction including address bytes
+ * @inst_off:	Register address where instruction has to be written
+ */
+struct zynq_qspi_inst_format {
+	u8 inst;
+	u8 inst_size;
+	u8 inst_off;
+};
+
+/* List of all the QSPI instructions and its format */
+static struct zynq_qspi_inst_format flash_inst[] = {
+	{ZYNQ_QSPI_FLASH_INST_WRSR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+	{ZYNQ_QSPI_FLASH_INST_PP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
+	{ZYNQ_QSPI_FLASH_INST_WRDS, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+	{ZYNQ_QSPI_FLASH_INST_RDSR1, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+	{ZYNQ_QSPI_FLASH_INST_WREN, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+	{ZYNQ_QSPI_FLASH_INST_AFR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+	{ZYNQ_QSPI_FLASH_INST_BE_4K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
+	{ZYNQ_QSPI_FLASH_INST_RDSR2, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+	{ZYNQ_QSPI_FLASH_INST_BE_32K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
+	{ZYNQ_QSPI_FLASH_INST_RDID, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+	{ZYNQ_QSPI_FLASH_INST_SE, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
+	/* Add all the instructions supported by the flash device */
+};
+
+/* zynq spi slave */
+struct zynq_qspi_slave {
+	struct spi_slave slave;
+	struct zynq_qspi_regs *base;
+	u8 mode;
+	u8 is_inst;
+	u8 fifo_depth;
+	const void *tx_buf;
+	void *rx_buf;
+	u32 tx_len;
+	u32 rx_len;
+	u32 speed_hz;
+	u32 input_hz;
+	u32 req_hz;
+};
+
+static inline struct zynq_qspi_slave *to_zynq_qspi_slave(
+		struct spi_slave *slave)
+{
+	return container_of(slave, struct zynq_qspi_slave, slave);
+}
+
+static void zynq_qspi_init_hw(struct zynq_qspi_slave *zslave)
+{
+	u32 confr;
+
+	/* Disable SPI */
+	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+
+	/* Disable Interrupts */
+	writel(ZYNQ_QSPI_IXR_ALL_MASK, &zslave->base->idr);
+
+	/* Clear RX FIFO */
+	while (readl(&zslave->base->isr) &
+			ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
+		readl(&zslave->base->rxdr);
+
+	/* Clear Interrupts */
+	writel(ZYNQ_QSPI_IXR_ALL_MASK, &zslave->base->isr);
+
+	/* Manual slave select and Auto start */
+	confr = ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
+		ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
+		ZYNQ_QSPI_CR_MSTREN_MASK;
+	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
+	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
+	writel(confr, &zslave->base->cr);
+
+	/* Enable SPI */
+	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+}
+
+/*
+ * zynq_qspi_read - Copy data to RX buffer
+ * @zqspi:      Pointer to zynq_qspi_slave
+ * @data:       The 32 bit variable where data is stored
+ * @size:       Number of bytes to be copied from data to RX buffer
+ */
+static void zynq_qspi_read(struct zynq_qspi_slave *zslave, u32 data, u8 size)
+{
+	if (zslave->rx_buf) {
+		data >>= (4 - size) * 8;
+		data = le32_to_cpu(data);
+		memcpy((u8 *)zslave->rx_buf, &data, size);
+		zslave->rx_buf += size;
+	}
+
+	zslave->rx_len -= size;
+}
+
+/*
+ * zynq_qspi_write - Copy data from TX buffer
+ * @zslave:	Pointer to zynq_qspi_slave
+ * @data:	Pointer to the 32 bit variable where data is to be copied
+ * @size:	Number of bytes to be copied from TX buffer to data
+ */
+static void zynq_qspi_write(struct zynq_qspi_slave *zslave, u32 *data, u8 size)
+{
+	if (zslave->tx_buf) {
+		switch (size) {
+		case 1:
+			*data = *((u8 *)zslave->tx_buf);
+			zslave->tx_buf += 1;
+			*data |= 0xFFFFFF00;
+			break;
+		case 2:
+			*data = *((u16 *)zslave->tx_buf);
+			zslave->tx_buf += 2;
+			*data |= 0xFFFF0000;
+			break;
+		case 3:
+			*data = *((u16 *)zslave->tx_buf);
+			zslave->tx_buf += 2;
+			*data |= (*((u8 *)zslave->tx_buf) << 16);
+			zslave->tx_buf += 1;
+			*data |= 0xFF000000;
+			break;
+		case 4:
+			/* Can not assume word aligned buffer */
+			memcpy(data, zslave->tx_buf, size);
+			zslave->tx_buf += 4;
+			break;
+		default:
+			/* This will never execute */
+			break;
+		}
+	} else {
+		*data = 0;
+	}
+
+	zslave->tx_len -= size;
+}
+
+static int zynq_qspi_check_txfifo(struct zynq_qspi_slave *zslave)
+{
+	u32 ts, status;
+
+	ts = get_timer(0);
+	status = readl(&zslave->base->isr);
+	while (!(status & ZYNQ_QSPI_IXR_TXOW_MASK)) {
+		if (get_timer(ts) > CONFIG_SYS_ZYNQ_QSPI_WAIT) {
+			printf("spi_xfer: Timeout! TX FIFO not full\n");
+			return -1;
+		}
+		status = readl(&zslave->base->isr);
+	}
+
+	return 0;
+}
+
+static int zynq_qspi_process_tx(struct zynq_qspi_slave *zslave)
+{
+	struct zynq_qspi_inst_format *curr_inst;
+	u8 inst, index;
+	u32 buf;
+
+	inst = *(u8 *)zslave->tx_buf;
+	/* instuction */
+	if (inst && zslave->is_inst) {
+		for (index = 0; index < ARRAY_SIZE(flash_inst); index++)
+			if (inst == flash_inst[index].inst)
+				break;
+
+		if (index == ARRAY_SIZE(flash_inst)) {
+			printf("spi_xfer: Unsupported inst %02x\n", inst);
+			return -1;
+		}
+
+		curr_inst = &flash_inst[index];
+		debug("spi_xfer: inst:%02x inst_size:%d inst_off:%02x\n",
+		      curr_inst->inst, curr_inst->inst_size,
+		      curr_inst->inst_off);
+
+		zynq_qspi_write(zslave, &buf, curr_inst->inst_size);
+		writel(buf, &zslave->base->cr + (curr_inst->inst_off / 4));
+		zslave->is_inst = 0;
+	} else if (!zslave->is_inst) { /* addr + data */
+		if (zslave->tx_len < 4) {
+			/* Check TXOW for txd1, txd2 and txd3 */
+			if (zynq_qspi_check_txfifo(zslave) < 0)
+				return -1;
+
+			zynq_qspi_write(zslave, &buf, zslave->tx_len);
+			writel(buf,
+			       &zslave->base->txd1r + (zslave->tx_len - 1));
+		} else {
+			zynq_qspi_write(zslave, &buf, 4);
+			writel(buf, &zslave->base->txd0r);
+		}
+	}
+
+	return 0;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	/* 1 bus with 1 chipselect */
+	return bus < 1 && cs < 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+
+	debug("spi_cs_activate: 0x%08x\n", (u32)slave);
+	clrbits_le32(&zslave->base->cr, ZYNQ_QSPI_CR_PCS_MASK);
+
+	zslave->is_inst = 1;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+
+	debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
+	setbits_le32(&zslave->base->cr, ZYNQ_QSPI_CR_PCS_MASK);
+
+	zslave->is_inst = 0;
+}
+
+void spi_init()
+{
+	/* nothing to do */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode)
+{
+	struct zynq_qspi_slave *zslave;
+
+	if (!spi_cs_is_valid(bus, cs))
+		return NULL;
+
+	zslave = spi_alloc_slave(struct zynq_qspi_slave, bus, cs);
+	if (!zslave) {
+		printf("SPI_error: Fail to allocate zynq_qspi_slave\n");
+		return NULL;
+	}
+
+	zslave->base = (struct zynq_qspi_regs *)ZYNQ_QSPI_BASEADDR;
+	zslave->mode = mode;
+	zslave->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
+	zslave->input_hz = 200000000;
+	zslave->speed_hz = zslave->input_hz / 2;
+	zslave->req_hz = max_hz;
+
+	/* init the zynq spi hw */
+	zynq_qspi_init_hw(zslave);
+
+	return &zslave->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+
+	debug("spi_free_slave: 0x%08x\n", (u32)slave);
+	free(zslave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+	u32 confr = 0;
+	u8 baud_rate_val = 0;
+
+	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+
+	/* Set the SPI Clock phase and polarities */
+	confr = readl(&zslave->base->cr);
+	confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
+	if (zslave->mode & SPI_CPHA)
+		confr |= ZYNQ_QSPI_CR_CPHA_MASK;
+	if (zslave->mode & SPI_CPOL)
+		confr |= ZYNQ_QSPI_CR_CPOL_MASK;
+
+	/* Set the clock frequency */
+	if (zslave->req_hz == 0) {
+		/* Set baudrate x8, if the req_hz is 0 */
+		baud_rate_val = 0x2;
+	} else if (zslave->speed_hz != zslave->req_hz) {
+		while ((baud_rate_val < 8) &&
+				((zslave->input_hz /
+				(2 << baud_rate_val)) > zslave->req_hz))
+			baud_rate_val++;
+		zslave->speed_hz = zslave->req_hz / (2 << baud_rate_val);
+	}
+	confr &= ~ZYNQ_QSPI_CR_BRD_MASK;
+	confr |= (baud_rate_val << 3);
+	writel(confr, &zslave->base->cr);
+
+	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+
+	debug("spi_release_bus: 0x%08x\n", (u32)slave);
+	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+		void *din, unsigned long flags)
+{
+	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+	u32 len = bitlen / 8, tx_tvl;
+	u32 buf, status;
+
+	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
+	      slave->bus, slave->cs, bitlen, len, flags);
+
+	if (bitlen == 0)
+		return -1;
+
+	if (bitlen % 8) {
+		debug("spi_xfer: Non byte aligned SPI transfer\n");
+		return -1;
+	}
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	zslave->tx_len = len;
+	zslave->rx_len = len;
+	zslave->tx_buf = dout;
+	zslave->rx_buf = din;
+	while (zslave->rx_len > 0) {
+		/* Write the data into TX FIFO - tx threshold is fifo_depth */
+		tx_tvl = 0;
+		while ((tx_tvl < zslave->fifo_depth) && zslave->tx_len) {
+			if (zynq_qspi_process_tx(zslave) < 0) {
+				flags |= SPI_XFER_END;
+				goto out;
+			}
+			tx_tvl++;
+		}
+
+		/* Check TX FIFO completion */
+		if (zynq_qspi_check_txfifo(zslave) < 0) {
+			flags |= SPI_XFER_END;
+			goto out;
+		}
+
+		/* Read the data from RX FIFO */
+		status = readl(&zslave->base->isr);
+		while (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK) {
+			buf = readl(&zslave->base->rxdr);
+			if (zslave->rx_len < 4)
+				zynq_qspi_read(zslave, buf, zslave->rx_len);
+			else
+				zynq_qspi_read(zslave, buf, 4);
+			status = readl(&zslave->base->isr);
+		}
+	}
+
+out:
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	return 0;
+}
-- 
1.8.3

[U-Boot] [PATCH 10/34] spi: Add zynq qspi controller driver

[thomas.langer at lantiq.com]

Hello Jagan,

I have some comments and questions:

Am 05.11.2013 18:51, schrieb Jagannadha Sutradharudu Teki:
> +
> +/* Definitions of the flash commands - Flash insts in ascending order */
> +#define ZYNQ_QSPI_FLASH_INST_WRSR	0x01	/* Write status register */
> +#define ZYNQ_QSPI_FLASH_INST_PP		0x02	/* Page program */
> +#define ZYNQ_QSPI_FLASH_INST_WRDS	0x04	/* Write disable */
> +#define ZYNQ_QSPI_FLASH_INST_RDSR1	0x05	/* Read status register 1 */
> +#define ZYNQ_QSPI_FLASH_INST_WREN	0x06	/* Write enable */
> +#define ZYNQ_QSPI_FLASH_INST_AFR	0x0B	/* Fast read data bytes */
> +#define ZYNQ_QSPI_FLASH_INST_BE_4K	0x20	/* Erase 4KiB block */
> +#define ZYNQ_QSPI_FLASH_INST_RDSR2	0x35	/* Read status register 2 */
> +#define ZYNQ_QSPI_FLASH_INST_BE_32K	0x52	/* Erase 32KiB block */
> +#define ZYNQ_QSPI_FLASH_INST_RDID	0x9F	/* Read JEDEC ID */
> +#define ZYNQ_QSPI_FLASH_INST_SE		0xD8	/* Sector erase (usually 64KB)*/
> +
Why needs the spi controller this list of flash commands?
It is the job of the flash driver to handle this, the spi controller
only forwards this to the devices!

> +
> +/* List of all the QSPI instructions and its format */
> +static struct zynq_qspi_inst_format flash_inst[] = {
> +	{ZYNQ_QSPI_FLASH_INST_WRSR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_PP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_WRDS, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_RDSR1, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_WREN, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_AFR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_BE_4K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_RDSR2, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_BE_32K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_RDID, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_SE, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	/* Add all the instructions supported by the flash device */
> +};
Is this table used to encode which parts needs DUAL or QUAD transfers?
And are you sure the table is complete? The flash drivers don't use more
instructions?
What happens if some device is connected, which is no flash?
> +
> +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> +		void *din, unsigned long flags)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +	u32 len = bitlen / 8, tx_tvl;
> +	u32 buf, status;
> +
> +	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
> +	      slave->bus, slave->cs, bitlen, len, flags);
> +
> +	if (bitlen == 0)
> +		return -1;
> +
> +	if (bitlen % 8) {
> +		debug("spi_xfer: Non byte aligned SPI transfer\n");
> +		return -1;
> +	}
> +
> +	if (flags & SPI_XFER_BEGIN)
> +		spi_cs_activate(slave);
> +
> +	zslave->tx_len = len;
> +	zslave->rx_len = len;
> +	zslave->tx_buf = dout;
> +	zslave->rx_buf = din;
> +	while (zslave->rx_len > 0) {
> +		/* Write the data into TX FIFO - tx threshold is fifo_depth */
> +		tx_tvl = 0;
> +		while ((tx_tvl < zslave->fifo_depth) && zslave->tx_len) {
> +			if (zynq_qspi_process_tx(zslave) < 0) {
> +				flags |= SPI_XFER_END;
> +				goto out;
> +			}
> +			tx_tvl++;
> +		}
> +
> +		/* Check TX FIFO completion */
> +		if (zynq_qspi_check_txfifo(zslave) < 0) {
> +			flags |= SPI_XFER_END;
> +			goto out;
> +		}
> +
> +		/* Read the data from RX FIFO */
> +		status = readl(&zslave->base->isr);
> +		while (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK) {
> +			buf = readl(&zslave->base->rxdr);
> +			if (zslave->rx_len < 4)
> +				zynq_qspi_read(zslave, buf, zslave->rx_len);
> +			else
> +				zynq_qspi_read(zslave, buf, 4);
> +			status = readl(&zslave->base->isr);
> +		}
> +	}
> +
> +out:
> +	if (flags & SPI_XFER_END)
> +		spi_cs_deactivate(slave);
> +
> +	return 0;
> +}
In this function I miss the parts, where the caller (e.g. the flash
driver) tells the controller to transfer some parts in DUAL or QUAD mode!

Best Regards,
Thomas

[U-Boot] [PATCH 10/34] spi: Add zynq qspi controller driver

[Jagan Teki]

Hi Thomas,

On Wednesday 06 November 2013 01:29 AM, thomas.langer at lantiq.com wrote:
> Hello Jagan,
>
> I have some comments and questions:
>
> Am 05.11.2013 18:51, schrieb Jagannadha Sutradharudu Teki:
>> +
>> +/* Definitions of the flash commands - Flash insts in ascending order */
>> +#define ZYNQ_QSPI_FLASH_INST_WRSR	0x01	/* Write status register */
>> +#define ZYNQ_QSPI_FLASH_INST_PP		0x02	/* Page program */
>> +#define ZYNQ_QSPI_FLASH_INST_WRDS	0x04	/* Write disable */
>> +#define ZYNQ_QSPI_FLASH_INST_RDSR1	0x05	/* Read status register 1 */
>> +#define ZYNQ_QSPI_FLASH_INST_WREN	0x06	/* Write enable */
>> +#define ZYNQ_QSPI_FLASH_INST_AFR	0x0B	/* Fast read data bytes */
>> +#define ZYNQ_QSPI_FLASH_INST_BE_4K	0x20	/* Erase 4KiB block */
>> +#define ZYNQ_QSPI_FLASH_INST_RDSR2	0x35	/* Read status register 2 */
>> +#define ZYNQ_QSPI_FLASH_INST_BE_32K	0x52	/* Erase 32KiB block */
>> +#define ZYNQ_QSPI_FLASH_INST_RDID	0x9F	/* Read JEDEC ID */
>> +#define ZYNQ_QSPI_FLASH_INST_SE		0xD8	/* Sector erase (usually 64KB)*/
>> +
> Why needs the spi controller this list of flash commands?
> It is the job of the flash driver to handle this, the spi controller
> only forwards this to the devices!
>
>> +
>> +/* List of all the QSPI instructions and its format */
>> +static struct zynq_qspi_inst_format flash_inst[] = {
>> +	{ZYNQ_QSPI_FLASH_INST_WRSR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_PP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_WRDS, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_RDSR1, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_WREN, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_AFR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_BE_4K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_RDSR2, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_BE_32K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_RDID, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_SE, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
>> +	/* Add all the instructions supported by the flash device */
>> +};
> Is this table used to encode which parts needs DUAL or QUAD transfers?
> And are you sure the table is complete? The flash drivers don't use more
> instructions?
> What happens if some device is connected, which is no flash?
>> +
>> +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
>> +		void *din, unsigned long flags)
>> +{
>> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
>> +	u32 len = bitlen / 8, tx_tvl;
>> +	u32 buf, status;
>> +
>> +	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
>> +	      slave->bus, slave->cs, bitlen, len, flags);
>> +
>> +	if (bitlen == 0)
>> +		return -1;
>> +
>> +	if (bitlen % 8) {
>> +		debug("spi_xfer: Non byte aligned SPI transfer\n");
>> +		return -1;
>> +	}
>> +
>> +	if (flags & SPI_XFER_BEGIN)
>> +		spi_cs_activate(slave);
>> +
>> +	zslave->tx_len = len;
>> +	zslave->rx_len = len;
>> +	zslave->tx_buf = dout;
>> +	zslave->rx_buf = din;
>> +	while (zslave->rx_len > 0) {
>> +		/* Write the data into TX FIFO - tx threshold is fifo_depth */
>> +		tx_tvl = 0;
>> +		while ((tx_tvl < zslave->fifo_depth) && zslave->tx_len) {
>> +			if (zynq_qspi_process_tx(zslave) < 0) {
>> +				flags |= SPI_XFER_END;
>> +				goto out;
>> +			}
>> +			tx_tvl++;
>> +		}
>> +
>> +		/* Check TX FIFO completion */
>> +		if (zynq_qspi_check_txfifo(zslave) < 0) {
>> +			flags |= SPI_XFER_END;
>> +			goto out;
>> +		}
>> +
>> +		/* Read the data from RX FIFO */
>> +		status = readl(&zslave->base->isr);
>> +		while (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK) {
>> +			buf = readl(&zslave->base->rxdr);
>> +			if (zslave->rx_len < 4)
>> +				zynq_qspi_read(zslave, buf, zslave->rx_len);
>> +			else
>> +				zynq_qspi_read(zslave, buf, 4);
>> +			status = readl(&zslave->base->isr);
>> +		}
>> +	}
>> +
>> +out:
>> +	if (flags & SPI_XFER_END)
>> +		spi_cs_deactivate(slave);
>> +
>> +	return 0;
>> +}
> In this function I miss the parts, where the caller (e.g. the flash
> driver) tells the controller to transfer some parts in DUAL or QUAD mode!

Yes- I sent this as part of zynq support series.
I will fix the details where controller won't need to aware of flash 
specific data in coming versions.

-- 
Thanks,
Jagan.

[U-Boot] [PATCH 10/34] spi: Add zynq qspi controller driver

[Dinh Nguyen]

On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
> Zynq qspi controller driver supports single bus
> with singe chipselect.
>
> Zynq qspi can be operated in below connection modes
> - single qspi
> - dual qspi, with dual stacked
> - dual qspi, with dual parallel
>
> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
> ---
>  arch/arm/include/asm/arch-zynq/hardware.h |   1 +
>  drivers/spi/Makefile                      |   1 +
>  drivers/spi/zynq_qspi.c                   | 447 ++++++++++++++++++++++++++++++
>  3 files changed, 449 insertions(+)
>  create mode 100644 drivers/spi/zynq_qspi.c
>
> diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
> index cd69677..05870ae 100644
> --- a/arch/arm/include/asm/arch-zynq/hardware.h
> +++ b/arch/arm/include/asm/arch-zynq/hardware.h
> @@ -19,6 +19,7 @@
>  #define ZYNQ_I2C_BASEADDR1		0xE0005000
>  #define ZYNQ_SPI_BASEADDR0		0xE0006000
>  #define ZYNQ_SPI_BASEADDR1		0xE0007000
> +#define ZYNQ_QSPI_BASEADDR		0xE000D000
>  #define ZYNQ_DDRC_BASEADDR		0xF8006000
>  
>  /* Reflect slcr offsets */
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 27902fe..5fafee0 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -37,3 +37,4 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
>  obj-$(CONFIG_TI_QSPI) += ti_qspi.o
>  obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>  obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
> +obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
> diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
> new file mode 100644
> index 0000000..f38ebca
> --- /dev/null
> +++ b/drivers/spi/zynq_qspi.c
> @@ -0,0 +1,447 @@
> +/*
> + * (C) Copyright 2013 Xilinx, Inc.
> + *
> + * Zynq PS Quad-SPI(QSPI) controller driver (master mode only)
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +#include <malloc.h>
> +#include <spi.h>
> +#include <asm/io.h>
> +#include <asm/arch/hardware.h>
> +
> +/* zynq spi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
> +#define ZYNQ_QSPI_CR_IFMODE_MASK	(1 << 31)	/* Flash intrface mode*/
> +#define ZYNQ_QSPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
> +#define ZYNQ_QSPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
> +#define ZYNQ_QSPI_CR_PCS_MASK		(1 << 10)	/* Peri chip select */
> +#define ZYNQ_QSPI_CR_FW_MASK		(0x3 << 6)	/* FIFO width */
> +#define ZYNQ_QSPI_CR_BRD_MASK		(0x7 << 3)	/* Baud rate div */
> +#define ZYNQ_QSPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
> +#define ZYNQ_QSPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
> +#define ZYNQ_QSPI_CR_MSTREN_MASK	(1 << 0)	/* Mode select */
> +#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	(1 << 4)	/* RX_FIFO_not_empty */
> +#define ZYNQ_QSPI_IXR_TXOW_MASK		(1 << 2)	/* TX_FIFO_not_full */
> +#define ZYNQ_QSPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
> +#define ZYNQ_QSPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
> +
> +/* QSPI Transmit Data Register */
> +#define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C /* Transmit 4-byte inst */
> +#define ZYNQ_QSPI_TXD_00_01_OFFSET	0x80 /* Transmit 1-byte inst */
> +#define ZYNQ_QSPI_TXD_00_10_OFFSET	0x84 /* Transmit 2-byte inst */
> +#define ZYNQ_QSPI_TXD_00_11_OFFSET	0x88 /* Transmit 3-byte inst */
> +
> +/* Definitions of the flash commands - Flash insts in ascending order */
> +#define ZYNQ_QSPI_FLASH_INST_WRSR	0x01	/* Write status register */
> +#define ZYNQ_QSPI_FLASH_INST_PP		0x02	/* Page program */
> +#define ZYNQ_QSPI_FLASH_INST_WRDS	0x04	/* Write disable */
> +#define ZYNQ_QSPI_FLASH_INST_RDSR1	0x05	/* Read status register 1 */
> +#define ZYNQ_QSPI_FLASH_INST_WREN	0x06	/* Write enable */
> +#define ZYNQ_QSPI_FLASH_INST_AFR	0x0B	/* Fast read data bytes */
> +#define ZYNQ_QSPI_FLASH_INST_BE_4K	0x20	/* Erase 4KiB block */
> +#define ZYNQ_QSPI_FLASH_INST_RDSR2	0x35	/* Read status register 2 */
> +#define ZYNQ_QSPI_FLASH_INST_BE_32K	0x52	/* Erase 32KiB block */
> +#define ZYNQ_QSPI_FLASH_INST_RDID	0x9F	/* Read JEDEC ID */
> +#define ZYNQ_QSPI_FLASH_INST_SE		0xD8	/* Sector erase (usually 64KB)*/
> +
> +#define ZYNQ_QSPI_FIFO_DEPTH		63
> +#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
> +#define CONFIG_SYS_ZYNQ_QSPI_WAIT	CONFIG_SYS_HZ/100	/* 10 ms */
> +#endif
> +
> +/* zynq qspi register set */
> +struct zynq_qspi_regs {
> +	u32 cr;		/* 0x00 */
> +	u32 isr;	/* 0x04 */
> +	u32 ier;	/* 0x08 */
> +	u32 idr;	/* 0x0C */
> +	u32 imr;	/* 0x10 */
> +	u32 enr;	/* 0x14 */
> +	u32 dr;		/* 0x18 */
> +	u32 txd0r;	/* 0x1C */
> +	u32 rxdr;	/* 0x20 */
> +	u32 sicr;	/* 0x24 */
> +	u32 txftr;	/* 0x28 */
> +	u32 rxftr;	/* 0x2C */
> +	u32 gpior;	/* 0x30 */
> +	u32 reserved0[19];
> +	u32 txd1r;	/* 0x80 */
> +	u32 txd2r;	/* 0x84 */
> +	u32 txd3r;	/* 0x88 */
> +};
> +
> +/*
> + * struct zynq_qspi_inst_format - Defines qspi flash instruction format
> + * @inst:	Instruction code
> + * @inst_size:	Size of the instruction including address bytes
> + * @inst_off:	Register address where instruction has to be written
> + */
> +struct zynq_qspi_inst_format {
> +	u8 inst;
> +	u8 inst_size;
> +	u8 inst_off;
> +};
> +
> +/* List of all the QSPI instructions and its format */
> +static struct zynq_qspi_inst_format flash_inst[] = {
> +	{ZYNQ_QSPI_FLASH_INST_WRSR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_PP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_WRDS, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_RDSR1, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_WREN, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_AFR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_BE_4K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_RDSR2, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_BE_32K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_RDID, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_SE, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	/* Add all the instructions supported by the flash device */
> +};
> +
> +/* zynq spi slave */
> +struct zynq_qspi_slave {
> +	struct spi_slave slave;
> +	struct zynq_qspi_regs *base;
> +	u8 mode;
> +	u8 is_inst;
> +	u8 fifo_depth;
> +	const void *tx_buf;
> +	void *rx_buf;
> +	u32 tx_len;
> +	u32 rx_len;
> +	u32 speed_hz;
> +	u32 input_hz;
> +	u32 req_hz;
> +};
> +
> +static inline struct zynq_qspi_slave *to_zynq_qspi_slave(
> +		struct spi_slave *slave)
> +{
> +	return container_of(slave, struct zynq_qspi_slave, slave);
> +}
> +
> +static void zynq_qspi_init_hw(struct zynq_qspi_slave *zslave)
> +{
> +	u32 confr;
> +
> +	/* Disable SPI */
> +	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
> +
> +	/* Disable Interrupts */
> +	writel(ZYNQ_QSPI_IXR_ALL_MASK, &zslave->base->idr);
> +
> +	/* Clear RX FIFO */
> +	while (readl(&zslave->base->isr) &
> +			ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
> +		readl(&zslave->base->rxdr);
> +
> +	/* Clear Interrupts */
> +	writel(ZYNQ_QSPI_IXR_ALL_MASK, &zslave->base->isr);
> +
> +	/* Manual slave select and Auto start */
> +	confr = ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
> +		ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
> +		ZYNQ_QSPI_CR_MSTREN_MASK;
> +	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
> +	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
Why &= ~ZYNQ_QSPI_CR_MSA_MASK twice?
> +	writel(confr, &zslave->base->cr);
> +
> +	/* Enable SPI */
> +	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
> +}
> +
> +/*
> + * zynq_qspi_read - Copy data to RX buffer
> + * @zqspi:      Pointer to zynq_qspi_slave
> + * @data:       The 32 bit variable where data is stored
> + * @size:       Number of bytes to be copied from data to RX buffer
> + */
> +static void zynq_qspi_read(struct zynq_qspi_slave *zslave, u32 data, u8 size)
> +{
> +	if (zslave->rx_buf) {
> +		data >>= (4 - size) * 8;
> +		data = le32_to_cpu(data);
> +		memcpy((u8 *)zslave->rx_buf, &data, size);
> +		zslave->rx_buf += size;
> +	}
> +
> +	zslave->rx_len -= size;
> +}
> +
> +/*
> + * zynq_qspi_write - Copy data from TX buffer
> + * @zslave:	Pointer to zynq_qspi_slave
> + * @data:	Pointer to the 32 bit variable where data is to be copied
> + * @size:	Number of bytes to be copied from TX buffer to data
> + */
> +static void zynq_qspi_write(struct zynq_qspi_slave *zslave, u32 *data, u8 size)
> +{
> +	if (zslave->tx_buf) {
> +		switch (size) {
> +		case 1:
> +			*data = *((u8 *)zslave->tx_buf);
> +			zslave->tx_buf += 1;
> +			*data |= 0xFFFFFF00;
> +			break;
> +		case 2:
> +			*data = *((u16 *)zslave->tx_buf);
> +			zslave->tx_buf += 2;
> +			*data |= 0xFFFF0000;
> +			break;
> +		case 3:
> +			*data = *((u16 *)zslave->tx_buf);
> +			zslave->tx_buf += 2;
> +			*data |= (*((u8 *)zslave->tx_buf) << 16);
> +			zslave->tx_buf += 1;
> +			*data |= 0xFF000000;
> +			break;
> +		case 4:
> +			/* Can not assume word aligned buffer */
> +			memcpy(data, zslave->tx_buf, size);
> +			zslave->tx_buf += 4;
> +			break;
> +		default:
> +			/* This will never execute */
> +			break;
> +		}
> +	} else {
> +		*data = 0;
> +	}
> +
> +	zslave->tx_len -= size;
> +}
> +
> +static int zynq_qspi_check_txfifo(struct zynq_qspi_slave *zslave)
> +{
> +	u32 ts, status;
> +
> +	ts = get_timer(0);
> +	status = readl(&zslave->base->isr);
> +	while (!(status & ZYNQ_QSPI_IXR_TXOW_MASK)) {
> +		if (get_timer(ts) > CONFIG_SYS_ZYNQ_QSPI_WAIT) {
> +			printf("spi_xfer: Timeout! TX FIFO not full\n");
> +			return -1;
> +		}
> +		status = readl(&zslave->base->isr);
> +	}
> +
> +	return 0;
> +}
> +
> +static int zynq_qspi_process_tx(struct zynq_qspi_slave *zslave)
> +{
> +	struct zynq_qspi_inst_format *curr_inst;
> +	u8 inst, index;
> +	u32 buf;
> +
> +	inst = *(u8 *)zslave->tx_buf;
> +	/* instuction */
> +	if (inst && zslave->is_inst) {
> +		for (index = 0; index < ARRAY_SIZE(flash_inst); index++)
> +			if (inst == flash_inst[index].inst)
> +				break;
> +
> +		if (index == ARRAY_SIZE(flash_inst)) {
> +			printf("spi_xfer: Unsupported inst %02x\n", inst);
> +			return -1;
> +		}
> +
> +		curr_inst = &flash_inst[index];
> +		debug("spi_xfer: inst:%02x inst_size:%d inst_off:%02x\n",
> +		      curr_inst->inst, curr_inst->inst_size,
> +		      curr_inst->inst_off);
> +
> +		zynq_qspi_write(zslave, &buf, curr_inst->inst_size);
> +		writel(buf, &zslave->base->cr + (curr_inst->inst_off / 4));
> +		zslave->is_inst = 0;
> +	} else if (!zslave->is_inst) { /* addr + data */
> +		if (zslave->tx_len < 4) {
> +			/* Check TXOW for txd1, txd2 and txd3 */
> +			if (zynq_qspi_check_txfifo(zslave) < 0)
> +				return -1;
> +
> +			zynq_qspi_write(zslave, &buf, zslave->tx_len);
> +			writel(buf,
> +			       &zslave->base->txd1r + (zslave->tx_len - 1));
> +		} else {
> +			zynq_qspi_write(zslave, &buf, 4);
> +			writel(buf, &zslave->base->txd0r);
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> +{
> +	/* 1 bus with 1 chipselect */
> +	return bus < 1 && cs < 1;
> +}
> +
> +void spi_cs_activate(struct spi_slave *slave)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +
> +	debug("spi_cs_activate: 0x%08x\n", (u32)slave);
> +	clrbits_le32(&zslave->base->cr, ZYNQ_QSPI_CR_PCS_MASK);
> +
> +	zslave->is_inst = 1;
> +}
> +
> +void spi_cs_deactivate(struct spi_slave *slave)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +
> +	debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
> +	setbits_le32(&zslave->base->cr, ZYNQ_QSPI_CR_PCS_MASK);
> +
> +	zslave->is_inst = 0;
> +}
> +
> +void spi_init()
> +{
> +	/* nothing to do */
> +}
> +
> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> +		unsigned int max_hz, unsigned int mode)
> +{
> +	struct zynq_qspi_slave *zslave;
> +
> +	if (!spi_cs_is_valid(bus, cs))
> +		return NULL;
> +
> +	zslave = spi_alloc_slave(struct zynq_qspi_slave, bus, cs);
> +	if (!zslave) {
> +		printf("SPI_error: Fail to allocate zynq_qspi_slave\n");
> +		return NULL;
> +	}
> +
> +	zslave->base = (struct zynq_qspi_regs *)ZYNQ_QSPI_BASEADDR;
> +	zslave->mode = mode;
> +	zslave->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
> +	zslave->input_hz = 200000000;
Should this be a CONFIG define?

Dinh
> +	zslave->speed_hz = zslave->input_hz / 2;
> +	zslave->req_hz = max_hz;
> +
> +	/* init the zynq spi hw */
> +	zynq_qspi_init_hw(zslave);
> +
> +	return &zslave->slave;
> +}
> +
> +void spi_free_slave(struct spi_slave *slave)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +
> +	debug("spi_free_slave: 0x%08x\n", (u32)slave);
> +	free(zslave);
> +}
> +
> +int spi_claim_bus(struct spi_slave *slave)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +	u32 confr = 0;
> +	u8 baud_rate_val = 0;
> +
> +	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
> +
> +	/* Set the SPI Clock phase and polarities */
> +	confr = readl(&zslave->base->cr);
> +	confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
> +	if (zslave->mode & SPI_CPHA)
> +		confr |= ZYNQ_QSPI_CR_CPHA_MASK;
> +	if (zslave->mode & SPI_CPOL)
> +		confr |= ZYNQ_QSPI_CR_CPOL_MASK;
> +
> +	/* Set the clock frequency */
> +	if (zslave->req_hz == 0) {
> +		/* Set baudrate x8, if the req_hz is 0 */
> +		baud_rate_val = 0x2;
> +	} else if (zslave->speed_hz != zslave->req_hz) {
> +		while ((baud_rate_val < 8) &&
> +				((zslave->input_hz /
> +				(2 << baud_rate_val)) > zslave->req_hz))
> +			baud_rate_val++;
> +		zslave->speed_hz = zslave->req_hz / (2 << baud_rate_val);
> +	}
> +	confr &= ~ZYNQ_QSPI_CR_BRD_MASK;
> +	confr |= (baud_rate_val << 3);
> +	writel(confr, &zslave->base->cr);
> +
> +	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
> +
> +	return 0;
> +}
> +
> +void spi_release_bus(struct spi_slave *slave)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +
> +	debug("spi_release_bus: 0x%08x\n", (u32)slave);
> +	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
> +}
> +
> +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> +		void *din, unsigned long flags)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +	u32 len = bitlen / 8, tx_tvl;
> +	u32 buf, status;
> +
> +	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
> +	      slave->bus, slave->cs, bitlen, len, flags);
> +
> +	if (bitlen == 0)
> +		return -1;
> +
> +	if (bitlen % 8) {
> +		debug("spi_xfer: Non byte aligned SPI transfer\n");
> +		return -1;
> +	}
> +
> +	if (flags & SPI_XFER_BEGIN)
> +		spi_cs_activate(slave);
> +
> +	zslave->tx_len = len;
> +	zslave->rx_len = len;
> +	zslave->tx_buf = dout;
> +	zslave->rx_buf = din;
> +	while (zslave->rx_len > 0) {
> +		/* Write the data into TX FIFO - tx threshold is fifo_depth */
> +		tx_tvl = 0;
> +		while ((tx_tvl < zslave->fifo_depth) && zslave->tx_len) {
> +			if (zynq_qspi_process_tx(zslave) < 0) {
> +				flags |= SPI_XFER_END;
> +				goto out;
> +			}
> +			tx_tvl++;
> +		}
> +
> +		/* Check TX FIFO completion */
> +		if (zynq_qspi_check_txfifo(zslave) < 0) {
> +			flags |= SPI_XFER_END;
> +			goto out;
> +		}
> +
> +		/* Read the data from RX FIFO */
> +		status = readl(&zslave->base->isr);
> +		while (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK) {
> +			buf = readl(&zslave->base->rxdr);
> +			if (zslave->rx_len < 4)
> +				zynq_qspi_read(zslave, buf, zslave->rx_len);
> +			else
> +				zynq_qspi_read(zslave, buf, 4);
> +			status = readl(&zslave->base->isr);
> +		}
> +	}
> +
> +out:
> +	if (flags & SPI_XFER_END)
> +		spi_cs_deactivate(slave);
> +
> +	return 0;
> +}

[U-Boot] [PATCH 10/34] spi: Add zynq qspi controller driver

[Dinh Nguyen]

On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
> Zynq qspi controller driver supports single bus
> with singe chipselect.
>
> Zynq qspi can be operated in below connection modes
> - single qspi
> - dual qspi, with dual stacked
> - dual qspi, with dual parallel
>
> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
> ---
>  arch/arm/include/asm/arch-zynq/hardware.h |   1 +
>  drivers/spi/Makefile                      |   1 +
>  drivers/spi/zynq_qspi.c                   | 447 ++++++++++++++++++++++++++++++
>  3 files changed, 449 insertions(+)
>  create mode 100644 drivers/spi/zynq_qspi.c
>
> diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
> index cd69677..05870ae 100644
> --- a/arch/arm/include/asm/arch-zynq/hardware.h
> +++ b/arch/arm/include/asm/arch-zynq/hardware.h
> @@ -19,6 +19,7 @@
>  #define ZYNQ_I2C_BASEADDR1		0xE0005000
>  #define ZYNQ_SPI_BASEADDR0		0xE0006000
>  #define ZYNQ_SPI_BASEADDR1		0xE0007000
> +#define ZYNQ_QSPI_BASEADDR		0xE000D000
>  #define ZYNQ_DDRC_BASEADDR		0xF8006000
>  
>  /* Reflect slcr offsets */
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 27902fe..5fafee0 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -37,3 +37,4 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
>  obj-$(CONFIG_TI_QSPI) += ti_qspi.o
>  obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>  obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
> +obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
> diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
> new file mode 100644
> index 0000000..f38ebca
> --- /dev/null
> +++ b/drivers/spi/zynq_qspi.c
> @@ -0,0 +1,447 @@
> +/*
> + * (C) Copyright 2013 Xilinx, Inc.
> + *
> + * Zynq PS Quad-SPI(QSPI) controller driver (master mode only)
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +#include <malloc.h>
> +#include <spi.h>
> +#include <asm/io.h>
> +#include <asm/arch/hardware.h>
> +
> +/* zynq spi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
> +#define ZYNQ_QSPI_CR_IFMODE_MASK	(1 << 31)	/* Flash intrface mode*/
> +#define ZYNQ_QSPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
> +#define ZYNQ_QSPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
> +#define ZYNQ_QSPI_CR_PCS_MASK		(1 << 10)	/* Peri chip select */
> +#define ZYNQ_QSPI_CR_FW_MASK		(0x3 << 6)	/* FIFO width */
> +#define ZYNQ_QSPI_CR_BRD_MASK		(0x7 << 3)	/* Baud rate div */
> +#define ZYNQ_QSPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
> +#define ZYNQ_QSPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
> +#define ZYNQ_QSPI_CR_MSTREN_MASK	(1 << 0)	/* Mode select */
> +#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	(1 << 4)	/* RX_FIFO_not_empty */
> +#define ZYNQ_QSPI_IXR_TXOW_MASK		(1 << 2)	/* TX_FIFO_not_full */
> +#define ZYNQ_QSPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
> +#define ZYNQ_QSPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
> +
> +/* QSPI Transmit Data Register */
> +#define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C /* Transmit 4-byte inst */
> +#define ZYNQ_QSPI_TXD_00_01_OFFSET	0x80 /* Transmit 1-byte inst */
> +#define ZYNQ_QSPI_TXD_00_10_OFFSET	0x84 /* Transmit 2-byte inst */
> +#define ZYNQ_QSPI_TXD_00_11_OFFSET	0x88 /* Transmit 3-byte inst */
> +
> +/* Definitions of the flash commands - Flash insts in ascending order */
> +#define ZYNQ_QSPI_FLASH_INST_WRSR	0x01	/* Write status register */
> +#define ZYNQ_QSPI_FLASH_INST_PP		0x02	/* Page program */
> +#define ZYNQ_QSPI_FLASH_INST_WRDS	0x04	/* Write disable */
> +#define ZYNQ_QSPI_FLASH_INST_RDSR1	0x05	/* Read status register 1 */
> +#define ZYNQ_QSPI_FLASH_INST_WREN	0x06	/* Write enable */
> +#define ZYNQ_QSPI_FLASH_INST_AFR	0x0B	/* Fast read data bytes */
> +#define ZYNQ_QSPI_FLASH_INST_BE_4K	0x20	/* Erase 4KiB block */
> +#define ZYNQ_QSPI_FLASH_INST_RDSR2	0x35	/* Read status register 2 */
> +#define ZYNQ_QSPI_FLASH_INST_BE_32K	0x52	/* Erase 32KiB block */
> +#define ZYNQ_QSPI_FLASH_INST_RDID	0x9F	/* Read JEDEC ID */
> +#define ZYNQ_QSPI_FLASH_INST_SE		0xD8	/* Sector erase (usually 64KB)*/
> +
> +#define ZYNQ_QSPI_FIFO_DEPTH		63
> +#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
> +#define CONFIG_SYS_ZYNQ_QSPI_WAIT	CONFIG_SYS_HZ/100	/* 10 ms */
> +#endif
> +
> +/* zynq qspi register set */
> +struct zynq_qspi_regs {
> +	u32 cr;		/* 0x00 */
> +	u32 isr;	/* 0x04 */
> +	u32 ier;	/* 0x08 */
> +	u32 idr;	/* 0x0C */
> +	u32 imr;	/* 0x10 */
> +	u32 enr;	/* 0x14 */
> +	u32 dr;		/* 0x18 */
> +	u32 txd0r;	/* 0x1C */
> +	u32 rxdr;	/* 0x20 */
> +	u32 sicr;	/* 0x24 */
> +	u32 txftr;	/* 0x28 */
> +	u32 rxftr;	/* 0x2C */
> +	u32 gpior;	/* 0x30 */
> +	u32 reserved0[19];
> +	u32 txd1r;	/* 0x80 */
> +	u32 txd2r;	/* 0x84 */
> +	u32 txd3r;	/* 0x88 */
> +};
> +
> +/*
> + * struct zynq_qspi_inst_format - Defines qspi flash instruction format
> + * @inst:	Instruction code
> + * @inst_size:	Size of the instruction including address bytes
> + * @inst_off:	Register address where instruction has to be written
> + */
> +struct zynq_qspi_inst_format {
> +	u8 inst;
> +	u8 inst_size;
> +	u8 inst_off;
> +};
> +
> +/* List of all the QSPI instructions and its format */
> +static struct zynq_qspi_inst_format flash_inst[] = {
> +	{ZYNQ_QSPI_FLASH_INST_WRSR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_PP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_WRDS, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_RDSR1, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_WREN, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_AFR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_BE_4K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_RDSR2, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_BE_32K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_RDID, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
> +	{ZYNQ_QSPI_FLASH_INST_SE, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
> +	/* Add all the instructions supported by the flash device */
> +};
> +
> +/* zynq spi slave */
> +struct zynq_qspi_slave {
> +	struct spi_slave slave;
> +	struct zynq_qspi_regs *base;
> +	u8 mode;
> +	u8 is_inst;
> +	u8 fifo_depth;
> +	const void *tx_buf;
> +	void *rx_buf;
> +	u32 tx_len;
> +	u32 rx_len;
> +	u32 speed_hz;
> +	u32 input_hz;
> +	u32 req_hz;
> +};
> +
> +static inline struct zynq_qspi_slave *to_zynq_qspi_slave(
> +		struct spi_slave *slave)
> +{
> +	return container_of(slave, struct zynq_qspi_slave, slave);
> +}
> +
> +static void zynq_qspi_init_hw(struct zynq_qspi_slave *zslave)
> +{
> +	u32 confr;
> +
> +	/* Disable SPI */
> +	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
> +
> +	/* Disable Interrupts */
> +	writel(ZYNQ_QSPI_IXR_ALL_MASK, &zslave->base->idr);
> +
> +	/* Clear RX FIFO */
> +	while (readl(&zslave->base->isr) &
> +			ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
> +		readl(&zslave->base->rxdr);
> +
> +	/* Clear Interrupts */
> +	writel(ZYNQ_QSPI_IXR_ALL_MASK, &zslave->base->isr);
> +
> +	/* Manual slave select and Auto start */
> +	confr = ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
> +		ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
> +		ZYNQ_QSPI_CR_MSTREN_MASK;
> +	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
> +	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
Copy/paste error? Why "confr &= ~ZYNQ_QSPI_CR_MSA_MASK;" twice?
> +	writel(confr, &zslave->base->cr);
> +
> +	/* Enable SPI */
> +	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
> +}
> +
> +/*
> + * zynq_qspi_read - Copy data to RX buffer
> + * @zqspi:      Pointer to zynq_qspi_slave
> + * @data:       The 32 bit variable where data is stored
> + * @size:       Number of bytes to be copied from data to RX buffer
> + */
> +static void zynq_qspi_read(struct zynq_qspi_slave *zslave, u32 data, u8 size)
> +{
> +	if (zslave->rx_buf) {
> +		data >>= (4 - size) * 8;
> +		data = le32_to_cpu(data);
> +		memcpy((u8 *)zslave->rx_buf, &data, size);
> +		zslave->rx_buf += size;
> +	}
> +
> +	zslave->rx_len -= size;
> +}
> +
> +/*
> + * zynq_qspi_write - Copy data from TX buffer
> + * @zslave:	Pointer to zynq_qspi_slave
> + * @data:	Pointer to the 32 bit variable where data is to be copied
> + * @size:	Number of bytes to be copied from TX buffer to data
> + */
> +static void zynq_qspi_write(struct zynq_qspi_slave *zslave, u32 *data, u8 size)
> +{
> +	if (zslave->tx_buf) {
> +		switch (size) {
> +		case 1:
> +			*data = *((u8 *)zslave->tx_buf);
> +			zslave->tx_buf += 1;
> +			*data |= 0xFFFFFF00;
> +			break;
> +		case 2:
> +			*data = *((u16 *)zslave->tx_buf);
> +			zslave->tx_buf += 2;
> +			*data |= 0xFFFF0000;
> +			break;
> +		case 3:
> +			*data = *((u16 *)zslave->tx_buf);
> +			zslave->tx_buf += 2;
> +			*data |= (*((u8 *)zslave->tx_buf) << 16);
> +			zslave->tx_buf += 1;
> +			*data |= 0xFF000000;
> +			break;
> +		case 4:
> +			/* Can not assume word aligned buffer */
> +			memcpy(data, zslave->tx_buf, size);
> +			zslave->tx_buf += 4;
> +			break;
> +		default:
> +			/* This will never execute */
> +			break;
> +		}
> +	} else {
> +		*data = 0;
> +	}
> +
> +	zslave->tx_len -= size;
> +}
> +
> +static int zynq_qspi_check_txfifo(struct zynq_qspi_slave *zslave)
> +{
> +	u32 ts, status;
> +
> +	ts = get_timer(0);
> +	status = readl(&zslave->base->isr);
> +	while (!(status & ZYNQ_QSPI_IXR_TXOW_MASK)) {
> +		if (get_timer(ts) > CONFIG_SYS_ZYNQ_QSPI_WAIT) {
> +			printf("spi_xfer: Timeout! TX FIFO not full\n");
> +			return -1;
> +		}
> +		status = readl(&zslave->base->isr);
> +	}
> +
> +	return 0;
> +}
> +
> +static int zynq_qspi_process_tx(struct zynq_qspi_slave *zslave)
> +{
> +	struct zynq_qspi_inst_format *curr_inst;
> +	u8 inst, index;
> +	u32 buf;
> +
> +	inst = *(u8 *)zslave->tx_buf;
> +	/* instuction */
> +	if (inst && zslave->is_inst) {
> +		for (index = 0; index < ARRAY_SIZE(flash_inst); index++)
> +			if (inst == flash_inst[index].inst)
> +				break;
> +
> +		if (index == ARRAY_SIZE(flash_inst)) {
> +			printf("spi_xfer: Unsupported inst %02x\n", inst);
> +			return -1;
> +		}
> +
> +		curr_inst = &flash_inst[index];
> +		debug("spi_xfer: inst:%02x inst_size:%d inst_off:%02x\n",
> +		      curr_inst->inst, curr_inst->inst_size,
> +		      curr_inst->inst_off);
> +
> +		zynq_qspi_write(zslave, &buf, curr_inst->inst_size);
> +		writel(buf, &zslave->base->cr + (curr_inst->inst_off / 4));
> +		zslave->is_inst = 0;
> +	} else if (!zslave->is_inst) { /* addr + data */
> +		if (zslave->tx_len < 4) {
> +			/* Check TXOW for txd1, txd2 and txd3 */
> +			if (zynq_qspi_check_txfifo(zslave) < 0)
> +				return -1;
> +
> +			zynq_qspi_write(zslave, &buf, zslave->tx_len);
> +			writel(buf,
> +			       &zslave->base->txd1r + (zslave->tx_len - 1));
> +		} else {
> +			zynq_qspi_write(zslave, &buf, 4);
> +			writel(buf, &zslave->base->txd0r);
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> +{
> +	/* 1 bus with 1 chipselect */
> +	return bus < 1 && cs < 1;
> +}
> +
> +void spi_cs_activate(struct spi_slave *slave)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +
> +	debug("spi_cs_activate: 0x%08x\n", (u32)slave);
> +	clrbits_le32(&zslave->base->cr, ZYNQ_QSPI_CR_PCS_MASK);
> +
> +	zslave->is_inst = 1;
> +}
> +
> +void spi_cs_deactivate(struct spi_slave *slave)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +
> +	debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
> +	setbits_le32(&zslave->base->cr, ZYNQ_QSPI_CR_PCS_MASK);
> +
> +	zslave->is_inst = 0;
> +}
> +
> +void spi_init()
> +{
> +	/* nothing to do */
> +}
> +
> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> +		unsigned int max_hz, unsigned int mode)
> +{
> +	struct zynq_qspi_slave *zslave;
> +
> +	if (!spi_cs_is_valid(bus, cs))
> +		return NULL;
> +
> +	zslave = spi_alloc_slave(struct zynq_qspi_slave, bus, cs);
> +	if (!zslave) {
> +		printf("SPI_error: Fail to allocate zynq_qspi_slave\n");
> +		return NULL;
> +	}
> +
> +	zslave->base = (struct zynq_qspi_regs *)ZYNQ_QSPI_BASEADDR;
> +	zslave->mode = mode;
> +	zslave->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
> +	zslave->input_hz = 200000000;
Should 200000000 be a CONFIG define?

Dinh
> +	zslave->speed_hz = zslave->input_hz / 2;
> +	zslave->req_hz = max_hz;
> +
> +	/* init the zynq spi hw */
> +	zynq_qspi_init_hw(zslave);
> +
> +	return &zslave->slave;
> +}
> +
> +void spi_free_slave(struct spi_slave *slave)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +
> +	debug("spi_free_slave: 0x%08x\n", (u32)slave);
> +	free(zslave);
> +}
> +
> +int spi_claim_bus(struct spi_slave *slave)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +	u32 confr = 0;
> +	u8 baud_rate_val = 0;
> +
> +	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
> +
> +	/* Set the SPI Clock phase and polarities */
> +	confr = readl(&zslave->base->cr);
> +	confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
> +	if (zslave->mode & SPI_CPHA)
> +		confr |= ZYNQ_QSPI_CR_CPHA_MASK;
> +	if (zslave->mode & SPI_CPOL)
> +		confr |= ZYNQ_QSPI_CR_CPOL_MASK;
> +
> +	/* Set the clock frequency */
> +	if (zslave->req_hz == 0) {
> +		/* Set baudrate x8, if the req_hz is 0 */
> +		baud_rate_val = 0x2;
> +	} else if (zslave->speed_hz != zslave->req_hz) {
> +		while ((baud_rate_val < 8) &&
> +				((zslave->input_hz /
> +				(2 << baud_rate_val)) > zslave->req_hz))
> +			baud_rate_val++;
> +		zslave->speed_hz = zslave->req_hz / (2 << baud_rate_val);
> +	}
> +	confr &= ~ZYNQ_QSPI_CR_BRD_MASK;
> +	confr |= (baud_rate_val << 3);
> +	writel(confr, &zslave->base->cr);
> +
> +	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
> +
> +	return 0;
> +}
> +
> +void spi_release_bus(struct spi_slave *slave)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +
> +	debug("spi_release_bus: 0x%08x\n", (u32)slave);
> +	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
> +}
> +
> +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> +		void *din, unsigned long flags)
> +{
> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
> +	u32 len = bitlen / 8, tx_tvl;
> +	u32 buf, status;
> +
> +	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
> +	      slave->bus, slave->cs, bitlen, len, flags);
> +
> +	if (bitlen == 0)
> +		return -1;
> +
> +	if (bitlen % 8) {
> +		debug("spi_xfer: Non byte aligned SPI transfer\n");
> +		return -1;
> +	}
> +
> +	if (flags & SPI_XFER_BEGIN)
> +		spi_cs_activate(slave);
> +
> +	zslave->tx_len = len;
> +	zslave->rx_len = len;
> +	zslave->tx_buf = dout;
> +	zslave->rx_buf = din;
> +	while (zslave->rx_len > 0) {
> +		/* Write the data into TX FIFO - tx threshold is fifo_depth */
> +		tx_tvl = 0;
> +		while ((tx_tvl < zslave->fifo_depth) && zslave->tx_len) {
> +			if (zynq_qspi_process_tx(zslave) < 0) {
> +				flags |= SPI_XFER_END;
> +				goto out;
> +			}
> +			tx_tvl++;
> +		}
> +
> +		/* Check TX FIFO completion */
> +		if (zynq_qspi_check_txfifo(zslave) < 0) {
> +			flags |= SPI_XFER_END;
> +			goto out;
> +		}
> +
> +		/* Read the data from RX FIFO */
> +		status = readl(&zslave->base->isr);
> +		while (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK) {
> +			buf = readl(&zslave->base->rxdr);
> +			if (zslave->rx_len < 4)
> +				zynq_qspi_read(zslave, buf, zslave->rx_len);
> +			else
> +				zynq_qspi_read(zslave, buf, 4);
> +			status = readl(&zslave->base->isr);
> +		}
> +	}
> +
> +out:
> +	if (flags & SPI_XFER_END)
> +		spi_cs_deactivate(slave);
> +
> +	return 0;
> +}

[U-Boot] [PATCH 10/34] spi: Add zynq qspi controller driver

[Jagan Teki]

On Wednesday 06 November 2013 10:32 AM, Dinh Nguyen wrote:
>
> On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
>> Zynq qspi controller driver supports single bus
>> with singe chipselect.
>>
>> Zynq qspi can be operated in below connection modes
>> - single qspi
>> - dual qspi, with dual stacked
>> - dual qspi, with dual parallel
>>
>> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
>> ---
>>   arch/arm/include/asm/arch-zynq/hardware.h |   1 +
>>   drivers/spi/Makefile                      |   1 +
>>   drivers/spi/zynq_qspi.c                   | 447 ++++++++++++++++++++++++++++++
>>   3 files changed, 449 insertions(+)
>>   create mode 100644 drivers/spi/zynq_qspi.c
>>
>> diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
>> index cd69677..05870ae 100644
>> --- a/arch/arm/include/asm/arch-zynq/hardware.h
>> +++ b/arch/arm/include/asm/arch-zynq/hardware.h
>> @@ -19,6 +19,7 @@
>>   #define ZYNQ_I2C_BASEADDR1		0xE0005000
>>   #define ZYNQ_SPI_BASEADDR0		0xE0006000
>>   #define ZYNQ_SPI_BASEADDR1		0xE0007000
>> +#define ZYNQ_QSPI_BASEADDR		0xE000D000
>>   #define ZYNQ_DDRC_BASEADDR		0xF8006000
>>
>>   /* Reflect slcr offsets */
>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>> index 27902fe..5fafee0 100644
>> --- a/drivers/spi/Makefile
>> +++ b/drivers/spi/Makefile
>> @@ -37,3 +37,4 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
>>   obj-$(CONFIG_TI_QSPI) += ti_qspi.o
>>   obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>>   obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
>> +obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
>> diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
>> new file mode 100644
>> index 0000000..f38ebca
>> --- /dev/null
>> +++ b/drivers/spi/zynq_qspi.c
>> @@ -0,0 +1,447 @@
>> +/*
>> + * (C) Copyright 2013 Xilinx, Inc.
>> + *
>> + * Zynq PS Quad-SPI(QSPI) controller driver (master mode only)
>> + *
>> + * SPDX-License-Identifier:	GPL-2.0+
>> + */
>> +
>> +#include <config.h>
>> +#include <common.h>
>> +#include <malloc.h>
>> +#include <spi.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/hardware.h>
>> +
>> +/* zynq spi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
>> +#define ZYNQ_QSPI_CR_IFMODE_MASK	(1 << 31)	/* Flash intrface mode*/
>> +#define ZYNQ_QSPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
>> +#define ZYNQ_QSPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
>> +#define ZYNQ_QSPI_CR_PCS_MASK		(1 << 10)	/* Peri chip select */
>> +#define ZYNQ_QSPI_CR_FW_MASK		(0x3 << 6)	/* FIFO width */
>> +#define ZYNQ_QSPI_CR_BRD_MASK		(0x7 << 3)	/* Baud rate div */
>> +#define ZYNQ_QSPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
>> +#define ZYNQ_QSPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
>> +#define ZYNQ_QSPI_CR_MSTREN_MASK	(1 << 0)	/* Mode select */
>> +#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	(1 << 4)	/* RX_FIFO_not_empty */
>> +#define ZYNQ_QSPI_IXR_TXOW_MASK		(1 << 2)	/* TX_FIFO_not_full */
>> +#define ZYNQ_QSPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
>> +#define ZYNQ_QSPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
>> +
>> +/* QSPI Transmit Data Register */
>> +#define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C /* Transmit 4-byte inst */
>> +#define ZYNQ_QSPI_TXD_00_01_OFFSET	0x80 /* Transmit 1-byte inst */
>> +#define ZYNQ_QSPI_TXD_00_10_OFFSET	0x84 /* Transmit 2-byte inst */
>> +#define ZYNQ_QSPI_TXD_00_11_OFFSET	0x88 /* Transmit 3-byte inst */
>> +
>> +/* Definitions of the flash commands - Flash insts in ascending order */
>> +#define ZYNQ_QSPI_FLASH_INST_WRSR	0x01	/* Write status register */
>> +#define ZYNQ_QSPI_FLASH_INST_PP		0x02	/* Page program */
>> +#define ZYNQ_QSPI_FLASH_INST_WRDS	0x04	/* Write disable */
>> +#define ZYNQ_QSPI_FLASH_INST_RDSR1	0x05	/* Read status register 1 */
>> +#define ZYNQ_QSPI_FLASH_INST_WREN	0x06	/* Write enable */
>> +#define ZYNQ_QSPI_FLASH_INST_AFR	0x0B	/* Fast read data bytes */
>> +#define ZYNQ_QSPI_FLASH_INST_BE_4K	0x20	/* Erase 4KiB block */
>> +#define ZYNQ_QSPI_FLASH_INST_RDSR2	0x35	/* Read status register 2 */
>> +#define ZYNQ_QSPI_FLASH_INST_BE_32K	0x52	/* Erase 32KiB block */
>> +#define ZYNQ_QSPI_FLASH_INST_RDID	0x9F	/* Read JEDEC ID */
>> +#define ZYNQ_QSPI_FLASH_INST_SE		0xD8	/* Sector erase (usually 64KB)*/
>> +
>> +#define ZYNQ_QSPI_FIFO_DEPTH		63
>> +#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
>> +#define CONFIG_SYS_ZYNQ_QSPI_WAIT	CONFIG_SYS_HZ/100	/* 10 ms */
>> +#endif
>> +
>> +/* zynq qspi register set */
>> +struct zynq_qspi_regs {
>> +	u32 cr;		/* 0x00 */
>> +	u32 isr;	/* 0x04 */
>> +	u32 ier;	/* 0x08 */
>> +	u32 idr;	/* 0x0C */
>> +	u32 imr;	/* 0x10 */
>> +	u32 enr;	/* 0x14 */
>> +	u32 dr;		/* 0x18 */
>> +	u32 txd0r;	/* 0x1C */
>> +	u32 rxdr;	/* 0x20 */
>> +	u32 sicr;	/* 0x24 */
>> +	u32 txftr;	/* 0x28 */
>> +	u32 rxftr;	/* 0x2C */
>> +	u32 gpior;	/* 0x30 */
>> +	u32 reserved0[19];
>> +	u32 txd1r;	/* 0x80 */
>> +	u32 txd2r;	/* 0x84 */
>> +	u32 txd3r;	/* 0x88 */
>> +};
>> +
>> +/*
>> + * struct zynq_qspi_inst_format - Defines qspi flash instruction format
>> + * @inst:	Instruction code
>> + * @inst_size:	Size of the instruction including address bytes
>> + * @inst_off:	Register address where instruction has to be written
>> + */
>> +struct zynq_qspi_inst_format {
>> +	u8 inst;
>> +	u8 inst_size;
>> +	u8 inst_off;
>> +};
>> +
>> +/* List of all the QSPI instructions and its format */
>> +static struct zynq_qspi_inst_format flash_inst[] = {
>> +	{ZYNQ_QSPI_FLASH_INST_WRSR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_PP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_WRDS, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_RDSR1, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_WREN, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_AFR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_BE_4K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_RDSR2, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_BE_32K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_RDID, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
>> +	{ZYNQ_QSPI_FLASH_INST_SE, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
>> +	/* Add all the instructions supported by the flash device */
>> +};
>> +
>> +/* zynq spi slave */
>> +struct zynq_qspi_slave {
>> +	struct spi_slave slave;
>> +	struct zynq_qspi_regs *base;
>> +	u8 mode;
>> +	u8 is_inst;
>> +	u8 fifo_depth;
>> +	const void *tx_buf;
>> +	void *rx_buf;
>> +	u32 tx_len;
>> +	u32 rx_len;
>> +	u32 speed_hz;
>> +	u32 input_hz;
>> +	u32 req_hz;
>> +};
>> +
>> +static inline struct zynq_qspi_slave *to_zynq_qspi_slave(
>> +		struct spi_slave *slave)
>> +{
>> +	return container_of(slave, struct zynq_qspi_slave, slave);
>> +}
>> +
>> +static void zynq_qspi_init_hw(struct zynq_qspi_slave *zslave)
>> +{
>> +	u32 confr;
>> +
>> +	/* Disable SPI */
>> +	writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
>> +
>> +	/* Disable Interrupts */
>> +	writel(ZYNQ_QSPI_IXR_ALL_MASK, &zslave->base->idr);
>> +
>> +	/* Clear RX FIFO */
>> +	while (readl(&zslave->base->isr) &
>> +			ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
>> +		readl(&zslave->base->rxdr);
>> +
>> +	/* Clear Interrupts */
>> +	writel(ZYNQ_QSPI_IXR_ALL_MASK, &zslave->base->isr);
>> +
>> +	/* Manual slave select and Auto start */
>> +	confr = ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
>> +		ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
>> +		ZYNQ_QSPI_CR_MSTREN_MASK;
>> +	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
>> +	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
> Copy/paste error? Why "confr &= ~ZYNQ_QSPI_CR_MSA_MASK;" twice?

Will fix in coming series.

>> +	writel(confr, &zslave->base->cr);
>> +
>> +	/* Enable SPI */
>> +	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
>> +}
>> +
>> +/*
>> + * zynq_qspi_read - Copy data to RX buffer
>> + * @zqspi:      Pointer to zynq_qspi_slave
>> + * @data:       The 32 bit variable where data is stored
>> + * @size:       Number of bytes to be copied from data to RX buffer
>> + */
>> +static void zynq_qspi_read(struct zynq_qspi_slave *zslave, u32 data, u8 size)
>> +{
>> +	if (zslave->rx_buf) {
>> +		data >>= (4 - size) * 8;
>> +		data = le32_to_cpu(data);
>> +		memcpy((u8 *)zslave->rx_buf, &data, size);
>> +		zslave->rx_buf += size;
>> +	}
>> +
>> +	zslave->rx_len -= size;
>> +}
>> +
>> +/*
>> + * zynq_qspi_write - Copy data from TX buffer
>> + * @zslave:	Pointer to zynq_qspi_slave
>> + * @data:	Pointer to the 32 bit variable where data is to be copied
>> + * @size:	Number of bytes to be copied from TX buffer to data
>> + */
>> +static void zynq_qspi_write(struct zynq_qspi_slave *zslave, u32 *data, u8 size)
>> +{
>> +	if (zslave->tx_buf) {
>> +		switch (size) {
>> +		case 1:
>> +			*data = *((u8 *)zslave->tx_buf);
>> +			zslave->tx_buf += 1;
>> +			*data |= 0xFFFFFF00;
>> +			break;
>> +		case 2:
>> +			*data = *((u16 *)zslave->tx_buf);
>> +			zslave->tx_buf += 2;
>> +			*data |= 0xFFFF0000;
>> +			break;
>> +		case 3:
>> +			*data = *((u16 *)zslave->tx_buf);
>> +			zslave->tx_buf += 2;
>> +			*data |= (*((u8 *)zslave->tx_buf) << 16);
>> +			zslave->tx_buf += 1;
>> +			*data |= 0xFF000000;
>> +			break;
>> +		case 4:
>> +			/* Can not assume word aligned buffer */
>> +			memcpy(data, zslave->tx_buf, size);
>> +			zslave->tx_buf += 4;
>> +			break;
>> +		default:
>> +			/* This will never execute */
>> +			break;
>> +		}
>> +	} else {
>> +		*data = 0;
>> +	}
>> +
>> +	zslave->tx_len -= size;
>> +}
>> +
>> +static int zynq_qspi_check_txfifo(struct zynq_qspi_slave *zslave)
>> +{
>> +	u32 ts, status;
>> +
>> +	ts = get_timer(0);
>> +	status = readl(&zslave->base->isr);
>> +	while (!(status & ZYNQ_QSPI_IXR_TXOW_MASK)) {
>> +		if (get_timer(ts) > CONFIG_SYS_ZYNQ_QSPI_WAIT) {
>> +			printf("spi_xfer: Timeout! TX FIFO not full\n");
>> +			return -1;
>> +		}
>> +		status = readl(&zslave->base->isr);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static int zynq_qspi_process_tx(struct zynq_qspi_slave *zslave)
>> +{
>> +	struct zynq_qspi_inst_format *curr_inst;
>> +	u8 inst, index;
>> +	u32 buf;
>> +
>> +	inst = *(u8 *)zslave->tx_buf;
>> +	/* instuction */
>> +	if (inst && zslave->is_inst) {
>> +		for (index = 0; index < ARRAY_SIZE(flash_inst); index++)
>> +			if (inst == flash_inst[index].inst)
>> +				break;
>> +
>> +		if (index == ARRAY_SIZE(flash_inst)) {
>> +			printf("spi_xfer: Unsupported inst %02x\n", inst);
>> +			return -1;
>> +		}
>> +
>> +		curr_inst = &flash_inst[index];
>> +		debug("spi_xfer: inst:%02x inst_size:%d inst_off:%02x\n",
>> +		      curr_inst->inst, curr_inst->inst_size,
>> +		      curr_inst->inst_off);
>> +
>> +		zynq_qspi_write(zslave, &buf, curr_inst->inst_size);
>> +		writel(buf, &zslave->base->cr + (curr_inst->inst_off / 4));
>> +		zslave->is_inst = 0;
>> +	} else if (!zslave->is_inst) { /* addr + data */
>> +		if (zslave->tx_len < 4) {
>> +			/* Check TXOW for txd1, txd2 and txd3 */
>> +			if (zynq_qspi_check_txfifo(zslave) < 0)
>> +				return -1;
>> +
>> +			zynq_qspi_write(zslave, &buf, zslave->tx_len);
>> +			writel(buf,
>> +			       &zslave->base->txd1r + (zslave->tx_len - 1));
>> +		} else {
>> +			zynq_qspi_write(zslave, &buf, 4);
>> +			writel(buf, &zslave->base->txd0r);
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
>> +{
>> +	/* 1 bus with 1 chipselect */
>> +	return bus < 1 && cs < 1;
>> +}
>> +
>> +void spi_cs_activate(struct spi_slave *slave)
>> +{
>> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
>> +
>> +	debug("spi_cs_activate: 0x%08x\n", (u32)slave);
>> +	clrbits_le32(&zslave->base->cr, ZYNQ_QSPI_CR_PCS_MASK);
>> +
>> +	zslave->is_inst = 1;
>> +}
>> +
>> +void spi_cs_deactivate(struct spi_slave *slave)
>> +{
>> +	struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
>> +
>> +	debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
>> +	setbits_le32(&zslave->base->cr, ZYNQ_QSPI_CR_PCS_MASK);
>> +
>> +	zslave->is_inst = 0;
>> +}
>> +
>> +void spi_init()
>> +{
>> +	/* nothing to do */
>> +}
>> +
>> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
>> +		unsigned int max_hz, unsigned int mode)
>> +{
>> +	struct zynq_qspi_slave *zslave;
>> +
>> +	if (!spi_cs_is_valid(bus, cs))
>> +		return NULL;
>> +
>> +	zslave = spi_alloc_slave(struct zynq_qspi_slave, bus, cs);
>> +	if (!zslave) {
>> +		printf("SPI_error: Fail to allocate zynq_qspi_slave\n");
>> +		return NULL;
>> +	}
>> +
>> +	zslave->base = (struct zynq_qspi_regs *)ZYNQ_QSPI_BASEADDR;
>> +	zslave->mode = mode;
>> +	zslave->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
>> +	zslave->input_hz = 200000000;
> Should 200000000 be a CONFIG define?
Yes - I will mark this constant with macro.

-- 
Thanks,
Jagan.

[U-Boot] [PATCH 11/34] zynq-common: Enable CONFIG_ZYNQ_QSPI

[Jagannadha Sutradharudu Teki]

Tested qspi on zynq board with stmicro, spansion and winbond
flashes by enabling CONFIG_ZYNQ_QSPI.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 438215b..200401c 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -79,6 +79,16 @@
 # define CONFIG_CMD_SF
 #endif
 
+/* QSPI */
+#ifdef CONFIG_ZYNQ_QSPI
+# define CONFIG_CMD_SF
+# define CONFIG_SF_DEFAULT_SPEED	30000000
+# define CONFIG_SPI_FLASH
+# define CONFIG_SPI_FLASH_STMICRO
+# define CONFIG_SPI_FLASH_SPANSION
+# define CONFIG_SPI_FLASH_WINBOND
+#endif
+
 /* NOR */
 #define CONFIG_SYS_NO_FLASH
 
-- 
1.8.3

[U-Boot] [PATCH 12/34] zynq: Add zynq zc70x board support

[Jagannadha Sutradharudu Teki]

The Zynq-7000 APSOC zc702 and zc706 enabled complte embedded
processing includes ASIC and FPGA design.

ZC702-:

APSOC:
- XC7Z020-CLG484-1
Memory:
- DDR3 Component Memory 1GB
- 16MB Quad SPI Flash
- IIC - 1 KB EEPROM
Connectivity:
- Gigabit Ethernet GMII, RGMII and SGMII.
- USB OTG - Host USB
- IIC Bus Headers/HUB
- 1 CAN with Wake on CAN
- USB-UART
Video/Display:
- HDMI Video OUT
- 8X LEDs
Control & I/O:
- 3 User Push Buttons
- 2 User Switches
- 8 User LEDs

For more info on zc702 board:
- http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm

ZC706-:

APSOC:
- XC7Z045 FFG900 -2 AP SoC
Memory:
- DDR3 Component Memory 1GB (PS)
- DDR3 SODIM Memory 1GB (PL)
- 2X16MB Quad SPI Flash (dual parallel)
- IIC - 1 KB EEPROM
Connectivity:
- PCIe Gen2x4
- SFP+ and SMA Pairs
- GigE RGMII Ethernet (PS)
- USB OTG 1 (PS) - Host USB
- IIC Bus Headers/HUB (PS)
- 1 CAN with Wake on CAN (PS)
- USB-UART
Video/Display:
- HDMI 8 color RGB 4.4.4 1080P-60 OUT
- HDMI IN 8 color RGB 4.4.4
Control & I/O:
- 2 User Push Buttons/Dip Switch, 2 User LEDs
- IIC access to GPIO
- SDIO (SD Card slot)
- 3 User Push Buttons, 2 User Switches, 8 User LEDs

For more info on zc706 board:
- http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 boards.cfg                    |  1 +
 include/configs/zynq-common.h |  9 ---------
 include/configs/zynq_zc70x.h  | 26 ++++++++++++++++++++++++++
 3 files changed, 27 insertions(+), 9 deletions(-)
 create mode 100644 include/configs/zynq_zc70x.h

diff --git a/boards.cfg b/boards.cfg
index 058ca3f..64c693b 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -344,6 +344,7 @@ Active  arm         armv7          socfpga     altera          socfpga
 Active  arm         armv7          u8500       st-ericsson     snowball            snowball                             -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
 Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
 Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
+Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc70x				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 200401c..d69c59b 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -36,7 +36,6 @@
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
 /* Zynq Serial driver */
-#define CONFIG_ZYNQ_SERIAL_UART1
 #ifdef CONFIG_ZYNQ_SERIAL_UART0
 # define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0000000
 # define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
@@ -60,8 +59,6 @@
 #endif
 
 /* Ethernet driver */
-#define CONFIG_ZYNQ_GEM0
-#define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
 #if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1)
 # define CONFIG_NET_MULTI
 # define CONFIG_ZYNQ_GEM
@@ -71,7 +68,6 @@
 # define CONFIG_PHY_MARVELL
 #endif
 
-#define CONFIG_ZYNQ_SPI
 /* SPI */
 #ifdef CONFIG_ZYNQ_SPI
 # define CONFIG_SPI_FLASH
@@ -89,10 +85,6 @@
 # define CONFIG_SPI_FLASH_WINBOND
 #endif
 
-/* NOR */
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_ZYNQ_SDHCI0
 /* MMC */
 #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
 # define CONFIG_MMC
@@ -106,7 +98,6 @@
 # define CONFIG_DOS_PARTITION
 #endif
 
-#define CONFIG_ZYNQ_I2C0
 /* I2C */
 #if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
 # define CONFIG_CMD_I2C
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
new file mode 100644
index 0000000..559cd19
--- /dev/null
+++ b/include/configs/zynq_zc70x.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards
+ * See zynq_common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZC70X_H
+#define __CONFIG_ZYNQ_ZC70X_H
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_QSPI
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZC70X_H */
-- 
1.8.3

[U-Boot] [PATCH 13/34] zynq: Add zynq zed board support

[Jagannadha Sutradharudu Teki]

Zed is a complete development board based on the
Xilinx Zynq-7000 All Programmable SoC.

APSOC:
- XC7Z020-CLG484-1
Memory:
- 512 MB DDR3
- 256 Mb Quad-SPI Flash(
- Full size SD/MMC card cage
Connectivity:
- 10/100/1000 Ethernet
- USB OTG (Device/Host/OTG)
- USB-UART
Expansion:
- FMC (Low Pin Count)
- Pmod. headers (2x6)
Video/Display:
- HDMI output (1080p60 + audio)
- VGA connector
- 128 x 32 OLED
- User LEDs (9)
User inputs:
- Slide switches (8)
- Push button switches (7)
Audio:
- 24-bit stereo audio CODEC
- Stereo line in/out
- Headphone
- Microphone input
Analog:
- Xilinx XADC header
- Supports 4 analog inputs
- 2 Differential / 4 Single-ended
Debug:
- On-board USB JTAG programming port
- ARM Debug Access Port (DAP)

For more info - http://zedboard.org/product/zedboard

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 boards.cfg                 |  1 +
 include/configs/zynq_zed.h | 25 +++++++++++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 include/configs/zynq_zed.h

diff --git a/boards.cfg b/boards.cfg
index 64c693b..4a2286c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -345,6 +345,7 @@ Active  arm         armv7          u8500       st-ericsson     snowball
 Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
 Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc70x				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
+Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zed				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
new file mode 100644
index 0000000..1d3dcf7
--- /dev/null
+++ b/include/configs/zynq_zed.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Zynq Evaluation and Development Board - ZedBoard
+ * See zynq_common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZED_H
+#define __CONFIG_ZYNQ_ZED_H
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_QSPI
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZED_H */
-- 
1.8.3

[U-Boot] [PATCH 14/34] zynq-common: Define CONFIG_SPI_FLASH_BAR

[Jagannadha Sutradharudu Teki]

Enabled bank/extn' addr register support for accessing
> 16Mbyte flash devices.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index d69c59b..7e02289 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -80,6 +80,7 @@
 # define CONFIG_CMD_SF
 # define CONFIG_SF_DEFAULT_SPEED	30000000
 # define CONFIG_SPI_FLASH
+# define CONFIG_SPI_FLASH_BAR
 # define CONFIG_SPI_FLASH_STMICRO
 # define CONFIG_SPI_FLASH_SPANSION
 # define CONFIG_SPI_FLASH_WINBOND
-- 
1.8.3

[U-Boot] [PATCH 15/34] zynq: Add PHYS_SDRAM_1_SIZE config

[Jagannadha Sutradharudu Teki]

Added PHYS_SDRAM_1_SIZE config for respective board
DDR size.

zc70x - 1GB
zed - 512MB

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 2 +-
 include/configs/zynq_zc70x.h  | 2 ++
 include/configs/zynq_zed.h    | 2 ++
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 7e02289..0e732de 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -137,7 +137,7 @@
 
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_SDRAM_BASE		0
-#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
 
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
index 559cd19..a273005 100644
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@ -10,6 +10,8 @@
 #ifndef __CONFIG_ZYNQ_ZC70X_H
 #define __CONFIG_ZYNQ_ZC70X_H
 
+#define PHYS_SDRAM_1_SIZE		(1024 * 1024 * 1024)
+
 #define CONFIG_ZYNQ_SERIAL_UART1
 #define CONFIG_ZYNQ_GEM0
 #define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
index 1d3dcf7..e5cbab6 100644
--- a/include/configs/zynq_zed.h
+++ b/include/configs/zynq_zed.h
@@ -10,6 +10,8 @@
 #ifndef __CONFIG_ZYNQ_ZED_H
 #define __CONFIG_ZYNQ_ZED_H
 
+#define PHYS_SDRAM_1_SIZE		(512 * 1024 * 1024)
+
 #define CONFIG_ZYNQ_SERIAL_UART1
 #define CONFIG_ZYNQ_GEM0
 #define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
-- 
1.8.3

[U-Boot] [PATCH 15/34] zynq: Add PHYS_SDRAM_1_SIZE config

[Tom Rini]

On Tue, Nov 05, 2013 at 11:16:36PM +0530, Jagannadha Sutradharudu Teki wrote:

> Added PHYS_SDRAM_1_SIZE config for respective board
> DDR size.
> 
> zc70x - 1GB
> zed - 512MB
> 
> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
> ---
>  include/configs/zynq-common.h | 2 +-
>  include/configs/zynq_zc70x.h  | 2 ++
>  include/configs/zynq_zed.h    | 2 ++
>  3 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
> index 7e02289..0e732de 100644
> --- a/include/configs/zynq-common.h
> +++ b/include/configs/zynq-common.h
> @@ -137,7 +137,7 @@
>  
>  #define CONFIG_NR_DRAM_BANKS		1
>  #define CONFIG_SYS_SDRAM_BASE		0
> -#define CONFIG_SYS_SDRAM_SIZE		0x40000000
> +#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
>  
>  #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
>  #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
> diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
> index 559cd19..a273005 100644
> --- a/include/configs/zynq_zc70x.h
> +++ b/include/configs/zynq_zc70x.h
> @@ -10,6 +10,8 @@
>  #ifndef __CONFIG_ZYNQ_ZC70X_H
>  #define __CONFIG_ZYNQ_ZC70X_H
>  
> +#define PHYS_SDRAM_1_SIZE		(1024 * 1024 * 1024)
> +
>  #define CONFIG_ZYNQ_SERIAL_UART1
>  #define CONFIG_ZYNQ_GEM0
>  #define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
> diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
> index 1d3dcf7..e5cbab6 100644
> --- a/include/configs/zynq_zed.h
> +++ b/include/configs/zynq_zed.h
> @@ -10,6 +10,8 @@
>  #ifndef __CONFIG_ZYNQ_ZED_H
>  #define __CONFIG_ZYNQ_ZED_H
>  
> +#define PHYS_SDRAM_1_SIZE		(512 * 1024 * 1024)
> +
>  #define CONFIG_ZYNQ_SERIAL_UART1
>  #define CONFIG_ZYNQ_GEM0
>  #define CONFIG_ZYNQ_GEM_PHY_ADDR0	0

Just move CONFIG_SYS_SDRAM_SIZE to the per-board config.

-- 
Tom
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[U-Boot] [PATCH 16/34] zynq-common: Define exact TEXT_BASE

[Jagannadha Sutradharudu Teki]

Defined TEXT_BASE for u-boot starts from 0x4000000
w.r.t zynq memory-map.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 0e732de..e702820 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -133,7 +133,7 @@
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 
 /* Physical Memory map */
-#define CONFIG_SYS_TEXT_BASE		0
+#define CONFIG_SYS_TEXT_BASE		0x4000000
 
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_SDRAM_BASE		0
-- 
1.8.3

[U-Boot] [PATCH 17/34] zynq: zc70x: Add Catalyst 24WC08 EEPROM config support

[Jagannadha Sutradharudu Teki]

Adds configurations for Catalyst 24WC08 EEPROM, which
is present on the zynq boards.

Enable EEPROM support for zc70x boards.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 10 ++++++++++
 include/configs/zynq_zc70x.h  |  1 +
 2 files changed, 11 insertions(+)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index e702820..6b8b6c4 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -108,6 +108,16 @@
 # define CONFIG_SYS_I2C_SLAVE		1
 #endif
 
+/* EEPROM */
+#ifdef CONFIG_ZYNQ_EEPROM
+# define CONFIG_CMD_EEPROM
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+# define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+# define CONFIG_SYS_EEPROM_SIZE			1024 /* Bytes */
+#endif
+
 #define CONFIG_BOOTP_SERVERIP
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
index a273005..e928ceb 100644
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@ -21,6 +21,7 @@
 #define CONFIG_ZYNQ_QSPI
 #define CONFIG_ZYNQ_SDHCI0
 #define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_EEPROM
 #define CONFIG_ZYNQ_BOOT_FREEBSD
 
 #include <configs/zynq-common.h>
-- 
1.8.3

[U-Boot] [PATCH 18/34] zynq: Add zynq microzed board support

[Jagannadha Sutradharudu Teki]

MicroZed is a low-cost development board based on
the Xilinx Zynq-7000 All Programmable SoC.

APSOC:
- XC7Z010-1CLG400C
Memory:
- 1 GB of DDR3 SDRAM
- 128Mb of QSPI flash(S25FL128SAGBHI200)
- Micro SD card interface
Communication:
- 10/100/1000 Ethernet
- USB 2.0
- USB-UART
User I/O:
- 100 User I/O (50 per connector)
- Configurable as up to 48 LVDS pairs or 100 single-ended I/O
Misc:
- Xilinx PC4 JTAG configuration port
- PS JTAG pins accessible via Pmod
- 33.33 MHz oscillator
- User LED and push switch

For more info - http://zedboard.org/product/microzed

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 boards.cfg                      |  1 +
 include/configs/zynq_microzed.h | 26 ++++++++++++++++++++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 include/configs/zynq_microzed.h

diff --git a/boards.cfg b/boards.cfg
index 4a2286c..e85dc0e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -346,6 +346,7 @@ Active  arm         armv7          u8500       st-ericsson     u8500
 Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc70x				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zed				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
+Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_microzed			-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h
new file mode 100644
index 0000000..e65df2b
--- /dev/null
+++ b/include/configs/zynq_microzed.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Micro Zynq Evaluation and Development Board - MicroZedBoard
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_MICROZED_H
+#define __CONFIG_ZYNQ_MICROZED_H
+
+#define PHYS_SDRAM_1_SIZE		(1024 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_QSPI
+#define CONFIG_ZYNQ_SDHCI0
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_MICROZED_H */
-- 
1.8.3

[U-Boot] [PATCH 19/34] zynq: Add zynq_zc770 xm010 board support

[Jagannadha Sutradharudu Teki]

ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013

ZC770 XM010:
- 1GB DDR3
- 128 Mb Quad-SPI Flash
- 8 Mb SST SI flash
- Full size SD/MMC card cage
- 10/100/1000 Ethernet
- USB-UART

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 boards.cfg                   |  1 +
 include/configs/zynq_zc770.h | 30 ++++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+)
 create mode 100644 include/configs/zynq_zc770.h

diff --git a/boards.cfg b/boards.cfg
index e85dc0e..73b4843 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -347,6 +347,7 @@ Active  arm         armv7          vf610       freescale       vf610twr
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc70x				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zed				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_microzed			-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
+Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm010			zynq_zc770:ZC770_XM010                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
new file mode 100644
index 0000000..4870b3c
--- /dev/null
+++ b/include/configs/zynq_zc770.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration settings for the Xilinx Zynq ZC770 board.
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZC770_H
+#define __CONFIG_ZYNQ_ZC770_H
+
+#define PHYS_SDRAM_1_SIZE	(1024 * 1024 * 1024)
+
+#define CONFIG_SYS_NO_FLASH
+
+#if defined(CONFIG_ZC770_XM010)
+# define CONFIG_ZYNQ_SERIAL_UART1
+# define CONFIG_ZYNQ_GEM0
+# define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
+# define CONFIG_ZYNQ_SDHCI0
+# define CONFIG_ZYNQ_QSPI
+
+#else
+# define CONFIG_ZYNQ_SERIAL_UART0
+#endif
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZC770_H */
-- 
1.8.3

[U-Boot] [PATCH 20/34] zynq: Add zynq_zc770 xm013 board support

[Jagannadha Sutradharudu Teki]

ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013

ZC770 XM013:
- 1GB DDR3
- 128 Mb Quad-SPI Flash(dual parallel)
- USB-UART

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 boards.cfg                   | 1 +
 include/configs/zynq_zc770.h | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/boards.cfg b/boards.cfg
index 73b4843..11c9bb9 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -348,6 +348,7 @@ Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc70x				-
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zed				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_microzed			-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm010			zynq_zc770:ZC770_XM010                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
+Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm013			zynq_zc770:ZC770_XM013                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
index 4870b3c..bcd9a6d 100644
--- a/include/configs/zynq_zc770.h
+++ b/include/configs/zynq_zc770.h
@@ -21,6 +21,12 @@
 # define CONFIG_ZYNQ_SDHCI0
 # define CONFIG_ZYNQ_QSPI
 
+#elif defined(CONFIG_ZC770_XM013)
+# define CONFIG_ZYNQ_SERIAL_UART0
+# define CONFIG_ZYNQ_GEM1
+# define CONFIG_ZYNQ_GEM_PHY_ADDR1	7
+# define CONFIG_ZYNQ_QSPI
+
 #else
 # define CONFIG_ZYNQ_SERIAL_UART0
 #endif
-- 
1.8.3

[U-Boot] [PATCH 21/34] zynq: Add zynq_zc770 xm012 board support

[Jagannadha Sutradharudu Teki]

ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013

ZC770 XM012:
- 1GB DDR3
- 64MiB Numonyx NOR flash
- USB-UART

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 boards.cfg                    |  1 +
 include/configs/zynq-common.h | 16 ++++++++++++++++
 include/configs/zynq_zc770.h  |  4 ++++
 3 files changed, 21 insertions(+)

diff --git a/boards.cfg b/boards.cfg
index 11c9bb9..9afcfd1 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -348,6 +348,7 @@ Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc70x				-
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zed				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_microzed			-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm010			zynq_zc770:ZC770_XM010                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
+Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm012			zynq_zc770:ZC770_XM012                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm013			zynq_zc770:ZC770_XM013                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 6b8b6c4..ffe1b93 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -86,6 +86,22 @@
 # define CONFIG_SPI_FLASH_WINBOND
 #endif
 
+/* NOR */
+#ifndef CONFIG_SYS_NO_FLASH
+# define CONFIG_SYS_FLASH_BASE		0xE2000000
+# define CONFIG_SYS_FLASH_SIZE		(16 * 1024 * 1024)
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_MAX_FLASH_SECT	512
+# define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+# define CONFIG_SYS_FLASH_WRITE_TOUT	5000
+# define CONFIG_FLASH_SHOW_PROGRESS	10
+# define CONFIG_SYS_FLASH_CFI
+# undef CONFIG_SYS_FLASH_EMPTY_INFO
+# define CONFIG_FLASH_CFI_DRIVER
+# undef CONFIG_SYS_FLASH_PROTECTION
+# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
 /* MMC */
 #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
 # define CONFIG_MMC
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
index bcd9a6d..9e7ba77 100644
--- a/include/configs/zynq_zc770.h
+++ b/include/configs/zynq_zc770.h
@@ -21,6 +21,10 @@
 # define CONFIG_ZYNQ_SDHCI0
 # define CONFIG_ZYNQ_QSPI
 
+#elif defined(CONFIG_ZC770_XM012)
+# define CONFIG_ZYNQ_SERIAL_UART1
+# undef CONFIG_SYS_NO_FLASH
+
 #elif defined(CONFIG_ZC770_XM013)
 # define CONFIG_ZYNQ_SERIAL_UART0
 # define CONFIG_ZYNQ_GEM1
-- 
1.8.3

[U-Boot] [PATCH 22/34] nand: Add zynq nand controller driver support

[Jagannadha Sutradharudu Teki]

Added support for Zynq Nand controller driver.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 arch/arm/include/asm/arch-zynq/hardware.h |    2 +
 drivers/mtd/nand/Makefile                 |    1 +
 drivers/mtd/nand/zynq_nand.c              | 1200 +++++++++++++++++++++++++++++
 3 files changed, 1203 insertions(+)
 create mode 100644 drivers/mtd/nand/zynq_nand.c

diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index 05870ae..f2c76a6 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -20,6 +20,8 @@
 #define ZYNQ_SPI_BASEADDR0		0xE0006000
 #define ZYNQ_SPI_BASEADDR1		0xE0007000
 #define ZYNQ_QSPI_BASEADDR		0xE000D000
+#define ZYNQ_SMC_BASEADDR		0xE000E000
+#define ZYNQ_NAND_BASEADDR		0xE1000000
 #define ZYNQ_DDRC_BASEADDR		0xF8006000
 
 /* Reflect slcr offsets */
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index eb1eafa..fcd6160 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
 obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 obj-$(CONFIG_NAND_PLAT) += nand_plat.o
 obj-$(CONFIG_NAND_DOCG4) += docg4.o
+obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
 
 else  # minimal SPL drivers
 
diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c
new file mode 100644
index 0000000..3e168fc
--- /dev/null
+++ b/drivers/mtd/nand/zynq_nand.c
@@ -0,0 +1,1200 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Xilinx Zynq NAND Flash Controller Driver
+ * This driver is based on plat_nand.c and mxc_nand.c drivers
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand_ecc.h>
+#include <asm/arch/hardware.h>
+
+/* The NAND flash driver defines */
+#define ZYNQ_NAND_CMD_PHASE	1	/* End command valid in command phase */
+#define ZYNQ_NAND_DATA_PHASE	2	/* End command valid in data phase */
+#define ZYNQ_NAND_ECC_SIZE	512	/* Size of data for ECC operation */
+
+/* Flash memory controller operating parameters */
+#define ZYNQ_NAND_CLR_CONFIG	((0x1 << 1)  |	/* Disable interrupt */ \
+				(0x1 << 4)   |	/* Clear interrupt */ \
+				(0x1 << 6))	/* Disable ECC interrupt */
+
+/* Assuming 50MHz clock (20ns cycle time) and 3V operation */
+#define ZYNQ_NAND_SET_CYCLES	((0x2 << 20) |	/* t_rr from nand_cycles */ \
+				(0x2 << 17)  |	/* t_ar from nand_cycles */ \
+				(0x1 << 14)  |	/* t_clr from nand_cycles */ \
+				(0x3 << 11)  |	/* t_wp from nand_cycles */ \
+				(0x2 << 8)   |	/* t_rea from nand_cycles */ \
+				(0x5 << 4)   |	/* t_wc from nand_cycles */ \
+				(0x5 << 0))	/* t_rc from nand_cycles */
+
+#define ZYNQ_NAND_SET_OPMODE	0x0
+
+#define ZYNQ_NAND_DIRECT_CMD	((0x4 << 23) |	/* Chip 0 from interface 1 */ \
+				(0x2 << 21))	/* UpdateRegs operation */
+
+#define ZYNQ_NAND_ECC_CONFIG	((0x1 << 2)  |	/* ECC available on APB */ \
+				(0x1 << 4)   |	/* ECC read at end of page */ \
+				(0x0 << 5))	/* No Jumping */
+
+#define ZYNQ_NAND_ECC_CMD1	((0x80)      |	/* Write command */ \
+				(0x00 << 8)  |	/* Read command */ \
+				(0x30 << 16) |	/* Read End command */ \
+				(0x1 << 24))	/* Read End command calid */
+
+#define ZYNQ_NAND_ECC_CMD2	((0x85)      |	/* Write col change cmd */ \
+				(0x05 << 8)  |	/* Read col change cmd */ \
+				(0xE0 << 16) |	/* Read col change end cmd */ \
+				(0x1 << 24))	/* Read col change
+							end cmd valid */
+/* AXI Address definitions */
+#define START_CMD_SHIFT		3
+#define END_CMD_SHIFT		11
+#define END_CMD_VALID_SHIFT	20
+#define ADDR_CYCLES_SHIFT	21
+#define CLEAR_CS_SHIFT		21
+#define ECC_LAST_SHIFT		10
+#define COMMAND_PHASE		(0 << 19)
+#define DATA_PHASE		(1 << 19)
+
+#define ZYNQ_NAND_ECC_LAST	(1 << ECC_LAST_SHIFT)	/* Set ECC_Last */
+#define ZYNQ_NAND_CLEAR_CS	(1 << CLEAR_CS_SHIFT)	/* Clear chip select */
+
+/* ECC block registers bit position and bit mask */
+#define ZYNQ_NAND_ECC_BUSY	(1 << 6)	/* ECC block is busy */
+#define ZYNQ_NAND_ECC_MASK	0x00FFFFFF	/* ECC value mask */
+
+/* SMC register set */
+struct zynq_nand_smc_regs {
+	u32 csr;		/* 0x00 */
+	u32 reserved0[2];
+	u32 cfr;		/* 0x0C */
+	u32 dcr;		/* 0x10 */
+	u32 scr;		/* 0x14 */
+	u32 sor;		/* 0x18 */
+	u32 reserved1[249];
+	u32 esr;		/* 0x400 */
+	u32 emcr;		/* 0x404 */
+	u32 emcmd1r;		/* 0x408 */
+	u32 emcmd2r;		/* 0x40C */
+	u32 reserved2[2];
+	u32 eval0r;		/* 0x418 */
+};
+#define zynq_nand_smc_base	((struct zynq_nand_smc_regs *)ZYNQ_SMC_BASEADDR)
+
+/*
+ * struct zynq_nand_command_format - Defines NAND flash command format
+ * @start_cmd:		First cycle command (Start command)
+ * @end_cmd:		Second cycle command (Last command)
+ * @addr_cycles:	Number of address cycles required to send the address
+ * @end_cmd_valid:	The second cycle command is valid for cmd or data phase
+ */
+struct zynq_nand_command_format {
+	int start_cmd;
+	int end_cmd;
+	u8 addr_cycles;
+	u8 end_cmd_valid;
+};
+
+/*
+ * struct zynq_nand_info - Defines the NAND flash driver instance
+ * @parts:		Pointer to the mtd_partition structure
+ * @nand_base:		Virtual address of the NAND flash device
+ * @end_cmd_pending:	End command is pending
+ * @end_cmd:		End command
+ */
+struct zynq_nand_info {
+#ifdef CONFIG_MTD_PARTITIONS
+	struct mtd_partition	*parts;
+#endif
+	void __iomem		*nand_base;
+	unsigned long		end_cmd_pending;
+	unsigned long		end_cmd;
+};
+
+#define ONDIE_ECC_FEATURE_ADDR	0x90
+
+/*  The NAND flash operations command format */
+static const struct zynq_nand_command_format zynq_nand_commands[] = {
+	{NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
+	{NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
+	{NAND_CMD_READID, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+	{NAND_CMD_STATUS, NAND_CMD_NONE, 0, NAND_CMD_NONE},
+	{NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
+	{NAND_CMD_RNDIN, NAND_CMD_NONE, 2, NAND_CMD_NONE},
+	{NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
+	{NAND_CMD_RESET, NAND_CMD_NONE, 0, NAND_CMD_NONE},
+	{NAND_CMD_PARAM, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+	{NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+	{NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+	{NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
+	/* Add all the flash commands supported by the flash device and Linux
+	 * The cache program command is not supported by driver because driver
+	 * cant differentiate between page program and cached page program from
+	 * start command, these commands can be differentiated through end
+	 * command, which doesn't fit in to the driver design. The cache program
+	 * command is not supported by NAND subsystem also, look@1612 line
+	 * number (in nand_write_page function) of nand_base.c file.
+	 * {NAND_CMD_SEQIN, NAND_CMD_CACHEDPROG, 5, ZYNQ_NAND_YES}
+	 */
+};
+
+/* Define default oob placement schemes for large and small page devices */
+static struct nand_ecclayout nand_oob_16 = {
+	.eccbytes = 3,
+	.eccpos = {13, 14, 15},
+	.oobfree = {
+		{ .offset = 0, .length = 12 }
+	}
+};
+
+static struct nand_ecclayout nand_oob_64 = {
+	.eccbytes = 12,
+	.eccpos = {
+		   52, 53, 54, 55, 56, 57,
+		   58, 59, 60, 61, 62, 63},
+	.oobfree = {
+		{ .offset = 2, .length = 50 }
+	}
+};
+
+static struct nand_ecclayout ondie_nand_oob_64 = {
+	.eccbytes = 32,
+
+	.eccpos = {
+		8, 9, 10, 11, 12, 13, 14, 15,
+		24, 25, 26, 27, 28, 29, 30, 31,
+		40, 41, 42, 43, 44, 45, 46, 47,
+		56, 57, 58, 59, 60, 61, 62, 63
+	},
+
+	.oobfree = {
+		{ .offset = 4, .length = 4 },
+		{ .offset = 20, .length = 4 },
+		{ .offset = 36, .length = 4 },
+		{ .offset = 52, .length = 4 }
+	}
+};
+
+/* Generic flash bbt decriptors */
+static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
+static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+		NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 4,
+	.len = 4,
+	.veroffs = 20,
+	.maxblocks = 4,
+	.pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+		NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 4,
+	.len = 4,
+	.veroffs = 20,
+	.maxblocks = 4,
+	.pattern = mirror_pattern
+};
+
+/*
+ * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
+ *
+ * returns: status for command completion, -1 for Timeout
+ */
+static int zynq_nand_waitfor_ecc_completion(void)
+{
+	unsigned long timeout;
+	u32 status;
+
+	/* Wait max 10ms */
+	timeout = 10;
+	status = readl(&zynq_nand_smc_base->esr);
+	while (status & ZYNQ_NAND_ECC_BUSY) {
+		status = readl(&zynq_nand_smc_base->esr);
+		if (timeout == 0)
+			return -1;
+		timeout--;
+		udelay(1);
+	}
+
+	return status;
+}
+
+/*
+ * zynq_nand_init_nand_flash - Initialize NAND controller
+ * @option:	Device property flags
+ *
+ * This function initializes the NAND flash interface on the NAND controller.
+ *
+ * returns:	0 on success or error value on failure
+ */
+static int zynq_nand_init_nand_flash(int option)
+{
+	u32 status;
+
+	/* disable interrupts */
+	writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
+	/* Initialize the NAND interface by setting cycles and operation mode */
+	writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
+	if (option & NAND_BUSWIDTH_16)
+		writel((ZYNQ_NAND_SET_OPMODE | 0x1), &zynq_nand_smc_base->sor);
+	else
+		writel(ZYNQ_NAND_SET_OPMODE, &zynq_nand_smc_base->sor);
+
+	writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
+
+	/* Wait till the ECC operation is complete */
+	status = zynq_nand_waitfor_ecc_completion();
+	if (status < 0) {
+		printf("%s: Timeout\n", __func__);
+		return status;
+	}
+
+	/* Set the command1 and command2 register */
+	writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
+	writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
+
+	return 0;
+}
+
+/*
+ * zynq_nand_calculate_hwecc - Calculate Hardware ECC
+ * @mtd:	Pointer to the mtd_info structure
+ * @data:	Pointer to the page data
+ * @ecc_code:	Pointer to the ECC buffer where ECC data needs to be stored
+ *
+ * This function retrieves the Hardware ECC data from the controller and returns
+ * ECC data back to the MTD subsystem.
+ *
+ * returns:	0 on success or error value on failure
+ */
+static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
+		u8 *ecc_code)
+{
+	u32 ecc_value = 0;
+	u8 ecc_reg, ecc_byte;
+	u32 ecc_status;
+
+	/* Wait till the ECC operation is complete */
+	ecc_status = zynq_nand_waitfor_ecc_completion();
+	if (ecc_status < 0) {
+		printf("%s: Timeout\n", __func__);
+		return ecc_status;
+	}
+
+	for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
+		/* Read ECC value for each block */
+		ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
+		ecc_status = (ecc_value >> 24) & 0xFF;
+		/* ECC value valid */
+		if (ecc_status & 0x40) {
+			for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
+				/* Copy ECC bytes to MTD buffer */
+				*ecc_code = ecc_value & 0xFF;
+				ecc_value = ecc_value >> 8;
+				ecc_code++;
+			}
+		} else {
+			debug("%s: ecc status failed\n", __func__);
+		}
+	}
+	return 0;
+}
+
+/*
+ * onehot - onehot function
+ * @value:	value to check for onehot
+ *
+ * This function checks whether a value is onehot or not.
+ * onehot is if and only if onebit is set.
+ *
+ */
+static int onehot(unsigned short value)
+{
+	return ((value & (value-1)) == 0);
+}
+
+/*
+ * zynq_nand_correct_data - ECC correction function
+ * @mtd:	Pointer to the mtd_info structure
+ * @buf:	Pointer to the page data
+ * @read_ecc:	Pointer to the ECC value read from spare data area
+ * @calc_ecc:	Pointer to the calculated ECC value
+ *
+ * This function corrects the ECC single bit errors & detects 2-bit errors.
+ *
+ * returns:	0 if no ECC errors found
+ *		1 if single bit error found and corrected.
+ *		-1 if multiple ECC errors found.
+ */
+static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
+			unsigned char *read_ecc, unsigned char *calc_ecc)
+{
+	unsigned char bit_addr;
+	unsigned int byte_addr;
+	unsigned short ecc_odd, ecc_even;
+	unsigned short read_ecc_lower, read_ecc_upper;
+	unsigned short calc_ecc_lower, calc_ecc_upper;
+
+	read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
+	read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
+
+	calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
+	calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
+
+	ecc_odd = read_ecc_lower ^ calc_ecc_lower;
+	ecc_even = read_ecc_upper ^ calc_ecc_upper;
+
+	if ((ecc_odd == 0) && (ecc_even == 0))
+		return 0;       /* no error */
+	else if (ecc_odd == (~ecc_even & 0xfff)) {
+		/* bits [11:3] of error code is byte offset */
+		byte_addr = (ecc_odd >> 3) & 0x1ff;
+		/* bits [2:0] of error code is bit offset */
+		bit_addr = ecc_odd & 0x7;
+		/* Toggling error bit */
+		buf[byte_addr] ^= (1 << bit_addr);
+		return 1;
+	} else if (onehot(ecc_odd | ecc_even) == 1) {
+		return 1; /* one error in parity */
+	} else {
+		return -1; /* Uncorrectable error */
+	}
+}
+
+/*
+ * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @page:	page number to read
+ * @sndcmd:	flag whether to issue read command or not
+ */
+static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+			int page)
+{
+	unsigned long data_width = 4;
+	unsigned long data_phase_addr = 0;
+	u8 *p;
+
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+
+	p = chip->oob_poi;
+	chip->read_buf(mtd, p, (mtd->oobsize - data_width));
+	p += (mtd->oobsize - data_width);
+
+	data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+	chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+	chip->read_buf(mtd, p, data_width);
+
+	return 0;
+}
+
+/*
+ * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @page:	page number to write
+ */
+static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+			     int page)
+{
+	int status = 0;
+	const u8 *buf = chip->oob_poi;
+	unsigned long data_width = 4;
+	unsigned long data_phase_addr = 0;
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+	chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
+	buf += (mtd->oobsize - data_width);
+
+	data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+	chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+	chip->write_buf(mtd, buf, data_width);
+
+	/* Send command to program the OOB data */
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/*
+ * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
+ * @mtd:        mtd info structure
+ * @chip:       nand chip info structure
+ * @buf:        buffer to store read data
+ * @oob_required: must write chip->oob_poi to OOB
+ * @page:       page number to read
+ */
+static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+				   u8 *buf,  int oob_required, int page)
+{
+	unsigned long data_width = 4;
+	unsigned long data_phase_addr = 0;
+	u8 *p;
+
+	chip->read_buf(mtd, buf, mtd->writesize);
+
+	p = chip->oob_poi;
+	chip->read_buf(mtd, p, (mtd->oobsize - data_width));
+	p += (mtd->oobsize - data_width);
+
+	data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+	chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+
+	chip->read_buf(mtd, p, data_width);
+	return 0;
+}
+
+static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
+		struct nand_chip *chip, u8 *buf, int oob_required, int page)
+{
+	chip->read_buf(mtd, buf, mtd->writesize);
+	return 0;
+}
+
+static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
+				    struct nand_chip *chip, u32 data_offs,
+				    u32 readlen, u8 *buf)
+{
+	if (data_offs != 0) {
+		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
+		buf += data_offs;
+	}
+
+	chip->read_buf(mtd, buf, readlen);
+	return 0;
+}
+
+/*
+ * zynq_nand_write_page_raw - [Intern] raw page write function
+ * @mtd:        mtd info structure
+ * @chip:       nand chip info structure
+ * @buf:        data buffer
+ * @oob_required: must write chip->oob_poi to OOB
+ */
+static int zynq_nand_write_page_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, const u8 *buf, int oob_required)
+{
+	unsigned long data_width = 4;
+	unsigned long data_phase_addr = 0;
+	u8 *p;
+
+	chip->write_buf(mtd, buf, mtd->writesize);
+
+	p = chip->oob_poi;
+	chip->write_buf(mtd, p, (mtd->oobsize - data_width));
+	p += (mtd->oobsize - data_width);
+
+	data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+	chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+
+	chip->write_buf(mtd, p, data_width);
+
+	return 0;
+}
+
+/*
+ * nand_write_page_hwecc - Hardware ECC based page write function
+ * @mtd:	Pointer to the mtd info structure
+ * @chip:	Pointer to the NAND chip info structure
+ * @buf:	Pointer to the data buffer
+ * @oob_required: must write chip->oob_poi to OOB
+ *
+ * This functions writes data and hardware generated ECC values in to the page.
+ */
+static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
+	struct nand_chip *chip, const u8 *buf, int oob_required)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccsteps = chip->ecc.steps;
+	u8 *ecc_calc = chip->buffers->ecccalc;
+	const u8 *p = buf;
+	u32 *eccpos = chip->ecc.layout->eccpos;
+	unsigned long data_phase_addr = 0;
+	unsigned long data_width = 4;
+	u8 *oob_ptr;
+
+	for (; (eccsteps - 1); eccsteps--) {
+		chip->write_buf(mtd, p, eccsize);
+		p += eccsize;
+	}
+	chip->write_buf(mtd, p, (eccsize - data_width));
+	p += (eccsize - data_width);
+
+	/* Set ECC Last bit to 1 */
+	data_phase_addr = (unsigned long) chip->IO_ADDR_W;
+	data_phase_addr |= ZYNQ_NAND_ECC_LAST;
+	chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+	chip->write_buf(mtd, p, data_width);
+
+	/* Wait for ECC to be calculated and read the error values */
+	p = buf;
+	chip->ecc.calculate(mtd, p, &ecc_calc[0]);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
+
+	/* Clear ECC last bit */
+	data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+	data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
+	chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+
+	/* Write the spare area with ECC bytes */
+	oob_ptr = chip->oob_poi;
+	chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
+
+	data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+	chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+	oob_ptr += (mtd->oobsize - data_width);
+	chip->write_buf(mtd, oob_ptr, data_width);
+
+	return 0;
+}
+
+/*
+ * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
+ * write function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	data buffer
+ * @oob_required: must write chip->oob_poi to OOB
+ */
+static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
+	struct nand_chip *chip, const u8 *buf, int oob_required)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	u8 *ecc_calc = chip->buffers->ecccalc;
+	const u8 *p = buf;
+	u32 *eccpos = chip->ecc.layout->eccpos;
+
+	/* Software ecc calculation */
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		chip->oob_poi[eccpos[i]] = ecc_calc[i];
+
+	return chip->ecc.write_page_raw(mtd, chip, buf, 1);
+}
+
+/*
+ * nand_read_page_hwecc - Hardware ECC based page read function
+ * @mtd:	Pointer to the mtd info structure
+ * @chip:	Pointer to the NAND chip info structure
+ * @buf:	Pointer to the buffer to store read data
+ * @oob_required: must write chip->oob_poi to OOB
+ * @page:	page number to read
+ *
+ * This functions reads data and checks the data integrity by comparing hardware
+ * generated ECC values and read ECC values from spare area.
+ *
+ * returns:	0 always and updates ECC operation status in to MTD structure
+ */
+static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
+	struct nand_chip *chip, u8 *buf, int oob_required, int page)
+{
+	int i, stat, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	u8 *p = buf;
+	u8 *ecc_calc = chip->buffers->ecccalc;
+	u8 *ecc_code = chip->buffers->ecccode;
+	u32 *eccpos = chip->ecc.layout->eccpos;
+	unsigned long data_phase_addr = 0;
+	unsigned long data_width = 4;
+	u8 *oob_ptr;
+
+	for (; (eccsteps - 1); eccsteps--) {
+		chip->read_buf(mtd, p, eccsize);
+		p += eccsize;
+	}
+	chip->read_buf(mtd, p, (eccsize - data_width));
+	p += (eccsize - data_width);
+
+	/* Set ECC Last bit to 1 */
+	data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+	data_phase_addr |= ZYNQ_NAND_ECC_LAST;
+	chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+	chip->read_buf(mtd, p, data_width);
+
+	/* Read the calculated ECC value */
+	p = buf;
+	chip->ecc.calculate(mtd, p, &ecc_calc[0]);
+
+	/* Clear ECC last bit */
+	data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+	data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
+	chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+
+	/* Read the stored ECC value */
+	oob_ptr = chip->oob_poi;
+	chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
+
+	/* de-assert chip select */
+	data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+	chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+
+	oob_ptr += (mtd->oobsize - data_width);
+	chip->read_buf(mtd, oob_ptr, data_width);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
+
+	eccsteps = chip->ecc.steps;
+	p = buf;
+
+	/* Check ECC error for all blocks and correct if it is correctable */
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+		if (stat < 0)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+	}
+	return 0;
+}
+
+/*
+ * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
+ * read function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	buffer to store read data
+ * @page:	page number to read
+ */
+static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
+	struct nand_chip *chip, u8 *buf, int oob_required,  int page)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	u8 *p = buf;
+	u8 *ecc_calc = chip->buffers->ecccalc;
+	u8 *ecc_code = chip->buffers->ecccode;
+	u32 *eccpos = chip->ecc.layout->eccpos;
+
+	chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+	eccsteps = chip->ecc.steps;
+	p = buf;
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		int stat;
+
+		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+		if (stat < 0)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+	}
+	return 0;
+}
+
+/*
+ * zynq_nand_select_chip - Select the flash device
+ * @mtd:	Pointer to the mtd_info structure
+ * @chip:	Chip number to be selected
+ *
+ * This function is empty as the NAND controller handles chip select line
+ * internally based on the chip address passed in command and data phase.
+ */
+static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+	return;
+}
+
+/*
+ * zynq_nand_cmd_function - Send command to NAND device
+ * @mtd:	Pointer to the mtd_info structure
+ * @command:	The command to be sent to the flash device
+ * @column:	The column address for this command, -1 if none
+ * @page_addr:	The page address for this command, -1 if none
+ */
+static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
+				 int column, int page_addr)
+{
+	struct nand_chip *chip = mtd->priv;
+	const struct zynq_nand_command_format *curr_cmd = NULL;
+	struct zynq_nand_info *xnand;
+	void *cmd_addr;
+	unsigned long cmd_data = 0;
+	unsigned long cmd_phase_addr = 0;
+	unsigned long data_phase_addr = 0;
+	unsigned long end_cmd = 0;
+	unsigned long end_cmd_valid = 0;
+	unsigned long i;
+
+	xnand = (struct zynq_nand_info *)chip->priv;
+	if (xnand->end_cmd_pending) {
+		/* Check for end command if this command request is same as the
+		 * pending command then return
+		 */
+		if (xnand->end_cmd == command) {
+			xnand->end_cmd = 0;
+			xnand->end_cmd_pending = 0;
+			return;
+		}
+	}
+
+	/* Emulate NAND_CMD_READOOB for large page device */
+	if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
+	    (command == NAND_CMD_READOOB)) {
+		column += mtd->writesize;
+		command = NAND_CMD_READ0;
+	}
+
+	/* Get the command format */
+	for (i = 0; (zynq_nand_commands[i].start_cmd != NAND_CMD_NONE ||
+		zynq_nand_commands[i].end_cmd != NAND_CMD_NONE); i++) {
+		if (command == zynq_nand_commands[i].start_cmd)
+			curr_cmd = &zynq_nand_commands[i];
+	}
+	if (curr_cmd == NULL)
+		return;
+
+	/* Clear interrupt */
+	writel((1 << 4), &zynq_nand_smc_base->cfr);
+
+	/* Get the command phase address */
+	if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
+		end_cmd_valid = 1;
+
+	if (curr_cmd->end_cmd == NAND_CMD_NONE)
+		end_cmd = 0x0;
+	else
+		end_cmd = curr_cmd->end_cmd;
+
+	cmd_phase_addr = (unsigned long)xnand->nand_base	|
+			(curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT)	|
+			(end_cmd_valid << END_CMD_VALID_SHIFT)		|
+			(COMMAND_PHASE)					|
+			(end_cmd << END_CMD_SHIFT)			|
+			(curr_cmd->start_cmd << START_CMD_SHIFT);
+
+	cmd_addr = (void __iomem *)cmd_phase_addr;
+
+	/* Get the data phase address */
+	end_cmd_valid = 0;
+
+	data_phase_addr = (unsigned long)xnand->nand_base	|
+			(0x0 << CLEAR_CS_SHIFT)				|
+			(end_cmd_valid << END_CMD_VALID_SHIFT)		|
+			(DATA_PHASE)					|
+			(end_cmd << END_CMD_SHIFT)			|
+			(0x0 << ECC_LAST_SHIFT);
+
+	chip->IO_ADDR_R = (void  __iomem *)data_phase_addr;
+	chip->IO_ADDR_W = chip->IO_ADDR_R;
+
+	/* Command phase AXI Read & Write */
+	if (column != -1 && page_addr != -1) {
+		/* Adjust columns for 16 bit bus width */
+		if (chip->options & NAND_BUSWIDTH_16)
+			column >>= 1;
+		cmd_data = column;
+		if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
+			cmd_data |= page_addr << 16;
+			/* Another address cycle for devices > 128MiB */
+			if (chip->chipsize > (128 << 20)) {
+				writel(cmd_data, cmd_addr);
+				cmd_data = (page_addr >> 16);
+			}
+		} else {
+			cmd_data |= page_addr << 8;
+		}
+	}
+	/* Erase */
+	else if (page_addr != -1)
+		cmd_data = page_addr;
+	/* Change read/write column, read id etc */
+	else if (column != -1) {
+		/* Adjust columns for 16 bit bus width */
+		if ((chip->options & NAND_BUSWIDTH_16) &&
+		    ((command == NAND_CMD_READ0) ||
+		     (command == NAND_CMD_SEQIN) ||
+		     (command == NAND_CMD_RNDOUT) ||
+		     (command == NAND_CMD_RNDIN)))
+			column >>= 1;
+		cmd_data = column;
+	} else
+		;
+
+	writel(cmd_data, cmd_addr);
+
+	if (curr_cmd->end_cmd_valid) {
+		xnand->end_cmd = curr_cmd->end_cmd;
+		xnand->end_cmd_pending = 1;
+	}
+
+	ndelay(100);
+
+	if ((command == NAND_CMD_READ0) ||
+	    (command == NAND_CMD_RESET) ||
+	    (command == NAND_CMD_PARAM) ||
+	    (command == NAND_CMD_GET_FEATURES)) {
+		while (!chip->dev_ready(mtd))
+				;
+		return;
+	}
+}
+
+/*
+ * zynq_nand_read_buf - read chip data into buffer
+ * @mtd:        MTD device structure
+ * @buf:        buffer to store date
+ * @len:        number of bytes to read
+ */
+static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	const u32 *nand = chip->IO_ADDR_R;
+
+	/* Make sure that buf is 32 bit aligned */
+	if (((int)buf & 0x3) != 0) {
+		if (((int)buf & 0x1) != 0) {
+			if (len) {
+				*buf = readb(nand);
+				buf += 1;
+				len--;
+			}
+		}
+
+		if (((int)buf & 0x3) != 0) {
+			if (len >= 2) {
+				*(u16 *)buf = readw(nand);
+				buf += 2;
+				len -= 2;
+			}
+		}
+	}
+
+	/* copy aligned data */
+	while (len >= 4) {
+		*(u32 *)buf = readl(nand);
+		buf += 4;
+		len -= 4;
+	}
+
+	/* mop up any remaining bytes */
+	if (len) {
+		if (len >= 2) {
+			*(u16 *)buf = readw(nand);
+			buf += 2;
+			len -= 2;
+		}
+
+		if (len)
+			*buf = readb(nand);
+	}
+}
+
+/*
+ * zynq_nand_write_buf - write buffer to chip
+ * @mtd:        MTD device structure
+ * @buf:        data buffer
+ * @len:        number of bytes to write
+ */
+static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	const u32 *nand = chip->IO_ADDR_W;
+
+	/* Make sure that buf is 32 bit aligned */
+	if (((int)buf & 0x3) != 0) {
+		if (((int)buf & 0x1) != 0) {
+			if (len) {
+				writeb(*buf, nand);
+				buf += 1;
+				len--;
+			}
+		}
+
+		if (((int)buf & 0x3) != 0) {
+			if (len >= 2) {
+				writew(*(u16 *)buf, nand);
+				buf += 2;
+				len -= 2;
+			}
+		}
+	}
+
+	/* copy aligned data */
+	while (len >= 4) {
+		writel(*(u32 *)buf, nand);
+		buf += 4;
+		len -= 4;
+	}
+
+	/* mop up any remaining bytes */
+	if (len) {
+		if (len >= 2) {
+			writew(*(u16 *)buf, nand);
+			buf += 2;
+			len -= 2;
+		}
+
+		if (len)
+			writeb(*buf, nand);
+	}
+}
+
+/*
+ * zynq_nand_device_ready - Check device ready/busy line
+ * @mtd:	Pointer to the mtd_info structure
+ *
+ * returns:	0 on busy or 1 on ready state
+ */
+static int zynq_nand_device_ready(struct mtd_info *mtd)
+{
+	/* Check the raw_int_status1 bit */
+	if ((readl(&zynq_nand_smc_base->csr)) & 0x40) {
+		/* Clear the interrupt condition */
+		writel((1 << 4), &zynq_nand_smc_base->cfr);
+		return 1;
+	}
+	return 0;
+}
+
+static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
+{
+	struct zynq_nand_info *xnand;
+	struct mtd_info *mtd;
+	unsigned long ecc_page_size;
+	int err = -1;
+	u8 maf_id, dev_id, i;
+	u8 get_feature[4];
+	u8 set_feature[4] = {0x08, 0x00, 0x00, 0x00};
+	unsigned long ecc_cfg;
+	int ondie_ecc_enabled = 0;
+
+	xnand = calloc(1, sizeof(struct zynq_nand_info));
+	if (!xnand) {
+		printf("%s: failed to allocate\n", __func__);
+		goto free;
+	}
+
+	xnand->nand_base = (void *)ZYNQ_NAND_BASEADDR;
+	mtd = &nand_info[0];
+
+	nand_chip->priv = xnand;
+	mtd->priv = nand_chip;
+
+	/* Set address of NAND IO lines */
+	nand_chip->IO_ADDR_R = xnand->nand_base;
+	nand_chip->IO_ADDR_W = xnand->nand_base;
+
+	/* Set the driver entry points for MTD */
+	nand_chip->cmdfunc = zynq_nand_cmd_function;
+	nand_chip->dev_ready = zynq_nand_device_ready;
+	nand_chip->select_chip = zynq_nand_select_chip;
+
+	/* If we don't set this delay driver sets 20us by default */
+	nand_chip->chip_delay = 30;
+
+	/* Buffer read/write routines */
+	nand_chip->read_buf = zynq_nand_read_buf;
+	nand_chip->write_buf = zynq_nand_write_buf;
+
+	nand_chip->bbt_options = NAND_BBT_USE_FLASH;
+
+	/* Initialize the NAND flash interface on NAND controller */
+	if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
+		printf("%s: nand flash init failed\n", __func__);
+		goto free;
+	}
+
+	/* first scan to find the device and get the page size */
+	if (nand_scan_ident(mtd, 1, NULL)) {
+		printf("%s: nand_scan_ident failed\n", __func__);
+		goto fail;
+	}
+
+	/* Send the command for reading device ID */
+	nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+	nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+	/* Read manufacturer and device IDs */
+	maf_id = nand_chip->read_byte(mtd);
+	dev_id = nand_chip->read_byte(mtd);
+
+	if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
+				 (dev_id == 0xa1) || (dev_id == 0xb1) ||
+				 (dev_id == 0xaa) || (dev_id == 0xba) ||
+				 (dev_id == 0xda) || (dev_id == 0xca) ||
+				 (dev_id == 0xac) || (dev_id == 0xbc) ||
+				 (dev_id == 0xdc) || (dev_id == 0xcc) ||
+				 (dev_id == 0xa3) || (dev_id == 0xb3) ||
+				 (dev_id == 0xd3) || (dev_id == 0xc3))) {
+		nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
+						ONDIE_ECC_FEATURE_ADDR, -1);
+
+		for (i = 0; i < 4; i++)
+			writeb(set_feature[i], nand_chip->IO_ADDR_W);
+
+		/* wait for 1us after writing data with SET_FEATURES command */
+		ndelay(1000);
+
+		nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
+						ONDIE_ECC_FEATURE_ADDR, -1);
+		nand_chip->read_buf(mtd, get_feature, 4);
+
+		if (get_feature[0] & 0x08) {
+			debug("%s: OnDie ECC flash\n", __func__);
+			ondie_ecc_enabled = 1;
+		} else {
+			printf("%s: Unable to detect OnDie ECC\n", __func__);
+		}
+	}
+
+	if (ondie_ecc_enabled) {
+		/* bypass the controller ECC block */
+		ecc_cfg = readl(&zynq_nand_smc_base->emcr);
+		ecc_cfg &= ~0xc;
+		writel(ecc_cfg, &zynq_nand_smc_base->emcr);
+
+		/* The software ECC routines won't work
+		 * with the SMC controller
+		 */
+		nand_chip->ecc.mode = NAND_ECC_HW;
+		nand_chip->ecc.strength = 1;
+		nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
+		nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
+		nand_chip->ecc.write_page = zynq_nand_write_page_raw;
+		nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
+		nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
+		nand_chip->ecc.read_oob = zynq_nand_read_oob;
+		nand_chip->ecc.write_oob = zynq_nand_write_oob;
+		nand_chip->ecc.size = mtd->writesize;
+		nand_chip->ecc.bytes = 0;
+
+		/* NAND with on-die ECC supports subpage reads */
+		nand_chip->options |= NAND_SUBPAGE_READ;
+
+		/* On-Die ECC spare bytes offset 8 is used for ECC codes */
+		if (ondie_ecc_enabled) {
+			nand_chip->ecc.layout = &ondie_nand_oob_64;
+			/* Use the BBT pattern descriptors */
+			nand_chip->bbt_td = &bbt_main_descr;
+			nand_chip->bbt_md = &bbt_mirror_descr;
+		}
+	} else {
+		/* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
+		nand_chip->ecc.mode = NAND_ECC_HW;
+		nand_chip->ecc.strength = 1;
+		nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
+		nand_chip->ecc.bytes = 3;
+		nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
+		nand_chip->ecc.correct = zynq_nand_correct_data;
+		nand_chip->ecc.hwctl = NULL;
+		nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
+		nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
+		nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
+		nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
+		nand_chip->ecc.read_oob = zynq_nand_read_oob;
+		nand_chip->ecc.write_oob = zynq_nand_write_oob;
+
+		switch (mtd->writesize) {
+		case 512:
+			ecc_page_size = 0x1;
+			/* Set the ECC memory config register */
+			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
+			       &zynq_nand_smc_base->emcr);
+			break;
+		case 1024:
+			ecc_page_size = 0x2;
+			/* Set the ECC memory config register */
+			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
+			       &zynq_nand_smc_base->emcr);
+			break;
+		case 2048:
+			ecc_page_size = 0x3;
+			/* Set the ECC memory config register */
+			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
+			       &zynq_nand_smc_base->emcr);
+			break;
+		default:
+			/* The software ECC routines won't work with
+			 * the SMC controller
+			 */
+			nand_chip->ecc.mode = NAND_ECC_HW;
+			nand_chip->ecc.calculate = nand_calculate_ecc;
+			nand_chip->ecc.correct = nand_correct_data;
+			nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
+			/* nand_chip->ecc.read_subpage = nand_read_subpage; */
+			nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
+			nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
+			nand_chip->ecc.write_page_raw =
+						zynq_nand_write_page_raw;
+			nand_chip->ecc.read_oob = zynq_nand_read_oob;
+			nand_chip->ecc.write_oob = zynq_nand_write_oob;
+			nand_chip->ecc.size = 256;
+			nand_chip->ecc.bytes = 3;
+			break;
+		}
+
+		if (mtd->oobsize == 16)
+			nand_chip->ecc.layout = &nand_oob_16;
+		else if (mtd->oobsize == 64)
+			nand_chip->ecc.layout = &nand_oob_64;
+		else
+			;
+	}
+
+	/* second phase scan */
+	if (nand_scan_tail(mtd)) {
+		printf("%s: nand_scan_tailfailed\n", __func__);
+		goto fail;
+	}
+
+	if (nand_register(devnum))
+		goto fail;
+
+	return 0;
+fail:
+	nand_release(mtd);
+free:
+	kfree(xnand);
+	return err;
+}
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+void board_nand_init(void)
+{
+	struct nand_chip *nand = &nand_chip[0];
+
+	if (zynq_nand_init(nand, 0))
+		puts("ZYNQ NAND init failed\n");
+}
-- 
1.8.3

[U-Boot] [PATCH 22/34] nand: Add zynq nand controller driver support

[Scott Wood]

On Tue, 2013-11-05 at 23:16 +0530, Jagannadha Sutradharudu Teki wrote:
> +#define zynq_nand_smc_base	((struct zynq_nand_smc_regs *)ZYNQ_SMC_BASEADDR)

__iomem

Please consider running sparse on new code.

> +/*
> + * struct zynq_nand_command_format - Defines NAND flash command format
> + * @start_cmd:		First cycle command (Start command)
> + * @end_cmd:		Second cycle command (Last command)
> + * @addr_cycles:	Number of address cycles required to send the address
> + * @end_cmd_valid:	The second cycle command is valid for cmd or data phase
> + */
> +struct zynq_nand_command_format {
> +	int start_cmd;
> +	int end_cmd;
> +	u8 addr_cycles;
> +	u8 end_cmd_valid;
> +};

Why are the first two "int" and the second two "u8"?

> +
> +/*
> + * struct zynq_nand_info - Defines the NAND flash driver instance
> + * @parts:		Pointer to the mtd_partition structure
> + * @nand_base:		Virtual address of the NAND flash device
> + * @end_cmd_pending:	End command is pending
> + * @end_cmd:		End command
> + */
> +struct zynq_nand_info {
> +#ifdef CONFIG_MTD_PARTITIONS
> +	struct mtd_partition	*parts;
> +#endif
> +	void __iomem		*nand_base;
> +	unsigned long		end_cmd_pending;
> +	unsigned long		end_cmd;
> +};

Why long?

> +
> +#define ONDIE_ECC_FEATURE_ADDR	0x90
> +
> +/*  The NAND flash operations command format */
> +static const struct zynq_nand_command_format zynq_nand_commands[] = {
> +	{NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
> +	{NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
> +	{NAND_CMD_READID, NAND_CMD_NONE, 1, NAND_CMD_NONE},
> +	{NAND_CMD_STATUS, NAND_CMD_NONE, 0, NAND_CMD_NONE},
> +	{NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
> +	{NAND_CMD_RNDIN, NAND_CMD_NONE, 2, NAND_CMD_NONE},
> +	{NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
> +	{NAND_CMD_RESET, NAND_CMD_NONE, 0, NAND_CMD_NONE},
> +	{NAND_CMD_PARAM, NAND_CMD_NONE, 1, NAND_CMD_NONE},
> +	{NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE},
> +	{NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE},
> +	{NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},

I'm not sure that NAND_CMD_NONE is appropriate for end_cmd_valid -- it's
not a field that otherwise takes NAND_CMD_xxx values.  Just use zero.

> +	/* Add all the flash commands supported by the flash device and Linux
> +	 * The cache program command is not supported by driver because driver
> +	 * cant differentiate between page program and cached page program from
> +	 * start command, these commands can be differentiated through end
> +	 * command, which doesn't fit in to the driver design. The cache program
> +	 * command is not supported by NAND subsystem also, look at 1612 line
> +	 * number (in nand_write_page function) of nand_base.c file.
> +	 * {NAND_CMD_SEQIN, NAND_CMD_CACHEDPROG, 5, ZYNQ_NAND_YES}
> +	 */

What is ZYNQ_NAND_YES?

> +};
> +
> +/* Define default oob placement schemes for large and small page devices */
> +static struct nand_ecclayout nand_oob_16 = {
> +	.eccbytes = 3,
> +	.eccpos = {13, 14, 15},
> +	.oobfree = {
> +		{ .offset = 0, .length = 12 }
> +	}
> +};

Isn't your oobfree overlapping the bad block marker?

Normally (with small-page NAND) the marker is at offset 5 for 8-bit and
offset 0 for 16-bit, not at offset 12.

> +	/* Wait max 10ms */
> +	timeout = 10;
> +	status = readl(&zynq_nand_smc_base->esr);
> +	while (status & ZYNQ_NAND_ECC_BUSY) {
> +		status = readl(&zynq_nand_smc_base->esr);
> +		if (timeout == 0)
> +			return -1;
> +		timeout--;
> +		udelay(1);
> +	}

Comment says 10ms, code says 10us.

> +
> +	return status;
> +}
> +
> +/*
> + * zynq_nand_init_nand_flash - Initialize NAND controller
> + * @option:	Device property flags
> + *
> + * This function initializes the NAND flash interface on the NAND controller.
> + *
> + * returns:	0 on success or error value on failure
> + */
> +static int zynq_nand_init_nand_flash(int option)
> +{
> +	u32 status;
> +
> +	/* disable interrupts */
> +	writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
> +	/* Initialize the NAND interface by setting cycles and operation mode */
> +	writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
> +	if (option & NAND_BUSWIDTH_16)
> +		writel((ZYNQ_NAND_SET_OPMODE | 0x1), &zynq_nand_smc_base->sor);
> +	else
> +		writel(ZYNQ_NAND_SET_OPMODE, &zynq_nand_smc_base->sor);

That 0x1 should be defined symbolically.

> +		/* ECC value valid */
> +		if (ecc_status & 0x40) {

0x40 should be defined symbolically.

> +/*
> + * onehot - onehot function
> + * @value:	value to check for onehot
> + *
> + * This function checks whether a value is onehot or not.
> + * onehot is if and only if onebit is set.
> + *
> + */
> +static int onehot(unsigned short value)
> +{
> +	return ((value & (value-1)) == 0);
> +}

Too many parentheses, and need spaces around '-'.
Why "unsigned short"?
Why use an obscure (at least to software people) name for this, rather
than some variant of "power of 2", or even "one_bit_set"?
s/onebit/one bit/

Note that the above function will also return true if no bits are set,
which contradicts the definition in the comment (yes, I know you don't
call it under such circumstances).

Function should return bool.

> +/*
> + * zynq_nand_correct_data - ECC correction function
> + * @mtd:	Pointer to the mtd_info structure
> + * @buf:	Pointer to the page data
> + * @read_ecc:	Pointer to the ECC value read from spare data area
> + * @calc_ecc:	Pointer to the calculated ECC value
> + *
> + * This function corrects the ECC single bit errors & detects 2-bit errors.
> + *
> + * returns:	0 if no ECC errors found
> + *		1 if single bit error found and corrected.
> + *		-1 if multiple ECC errors found.
> + */
> +static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
> +			unsigned char *read_ecc, unsigned char *calc_ecc)
> +{
> +	unsigned char bit_addr;
> +	unsigned int byte_addr;
> +	unsigned short ecc_odd, ecc_even;
> +	unsigned short read_ecc_lower, read_ecc_upper;
> +	unsigned short calc_ecc_lower, calc_ecc_upper;
> +
> +	read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
> +	read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
> +
> +	calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
> +	calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
> +
> +	ecc_odd = read_ecc_lower ^ calc_ecc_lower;
> +	ecc_even = read_ecc_upper ^ calc_ecc_upper;
> +
> +	if ((ecc_odd == 0) && (ecc_even == 0))
> +		return 0;       /* no error */
> +	else if (ecc_odd == (~ecc_even & 0xfff)) {
> +		/* bits [11:3] of error code is byte offset */
> +		byte_addr = (ecc_odd >> 3) & 0x1ff;
> +		/* bits [2:0] of error code is bit offset */
> +		bit_addr = ecc_odd & 0x7;
> +		/* Toggling error bit */
> +		buf[byte_addr] ^= (1 << bit_addr);
> +		return 1;
> +	} else if (onehot(ecc_odd | ecc_even) == 1) {
> +		return 1; /* one error in parity */
> +	} else {
> +		return -1; /* Uncorrectable error */
> +	}
> +}

You don't need "else" after "return"...

> +
> +/*
> + * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function

The version in nand_base.c is replaceable and (perhaps) the most common
implementation, but this one isn't.

> + * @mtd:	mtd info structure
> + * @chip:	nand chip info structure
> + * @page:	page number to read
> + * @sndcmd:	flag whether to issue read command or not
> + */
> +static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
> +			int page)
> +{
> +	unsigned long data_width = 4;

Why long?

> +	unsigned long data_phase_addr = 0;
> +	u8 *p;
> +
> +	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
> +
> +	p = chip->oob_poi;
> +	chip->read_buf(mtd, p, (mtd->oobsize - data_width));
> +	p += (mtd->oobsize - data_width);

Unnecessary parentheses.  Likewise elsewhere in the patch.

> +static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
> +	struct nand_chip *chip, const u8 *buf, int oob_required)
> +{
> +	int i, eccsize = chip->ecc.size;
> +	int eccsteps = chip->ecc.steps;
> +	u8 *ecc_calc = chip->buffers->ecccalc;
> +	const u8 *p = buf;
> +	u32 *eccpos = chip->ecc.layout->eccpos;
> +	unsigned long data_phase_addr = 0;
> +	unsigned long data_width = 4;
> +	u8 *oob_ptr;
> +
> +	for (; (eccsteps - 1); eccsteps--) {
> +		chip->write_buf(mtd, p, eccsize);
> +		p += eccsize;
> +	}

Why is eccsteps initialized at the declaration rather than as part of
the loop?

> +/*
> + * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
> + * write function

Is there a reason you need both hwecc and swecc support?

More importantly, is there a reason why you need to duplicate these
functions for swecc?  I don't see any difference versus the original in
nand_base.c.

> +/*
> + * zynq_nand_select_chip - Select the flash device
> + * @mtd:	Pointer to the mtd_info structure
> + * @chip:	Chip number to be selected
> + *
> + * This function is empty as the NAND controller handles chip select line
> + * internally based on the chip address passed in command and data phase.
> + */
> +static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
> +{
> +	return;
> +}

"return;" is unnecessary

> +/*
> + * zynq_nand_cmd_function - Send command to NAND device
> + * @mtd:	Pointer to the mtd_info structure
> + * @command:	The command to be sent to the flash device
> + * @column:	The column address for this command, -1 if none
> + * @page_addr:	The page address for this command, -1 if none
> + */
> +static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
> +				 int column, int page_addr)
> +{
> +	struct nand_chip *chip = mtd->priv;
> +	const struct zynq_nand_command_format *curr_cmd = NULL;
> +	struct zynq_nand_info *xnand;
> +	void *cmd_addr;
> +	unsigned long cmd_data = 0;
> +	unsigned long cmd_phase_addr = 0;
> +	unsigned long data_phase_addr = 0;
> +	unsigned long end_cmd = 0;
> +	unsigned long end_cmd_valid = 0;
> +	unsigned long i;

Other than the addresses, why long?

> +
> +	xnand = (struct zynq_nand_info *)chip->priv;
> +	if (xnand->end_cmd_pending) {
> +		/* Check for end command if this command request is same as the
> +		 * pending command then return
> +		 */
> +		if (xnand->end_cmd == command) {
> +			xnand->end_cmd = 0;
> +			xnand->end_cmd_pending = 0;
> +			return;
> +		}
> +	}
> +
> +	/* Emulate NAND_CMD_READOOB for large page device */
> +	if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
> +	    (command == NAND_CMD_READOOB)) {
> +		column += mtd->writesize;
> +		command = NAND_CMD_READ0;
> +	}
> +
> +	/* Get the command format */
> +	for (i = 0; (zynq_nand_commands[i].start_cmd != NAND_CMD_NONE ||
> +		zynq_nand_commands[i].end_cmd != NAND_CMD_NONE); i++) {
> +		if (command == zynq_nand_commands[i].start_cmd)

Please do not line up the continuation line with the loop body.

Why not use "i < ARRAY_SIZE(zynq_nand_commands)" instead, and get rid of
the sentinel?

> +			curr_cmd = &zynq_nand_commands[i];
> +	}
> +	if (curr_cmd == NULL)
> +		return;
> +
> +	/* Clear interrupt */
> +	writel((1 << 4), &zynq_nand_smc_base->cfr);

1 << 4 should be defined symbolically.

> +	} else
> +		;

Get rid of that else.

> +	writel(cmd_data, cmd_addr);
> +
> +	if (curr_cmd->end_cmd_valid) {
> +		xnand->end_cmd = curr_cmd->end_cmd;
> +		xnand->end_cmd_pending = 1;
> +	}
> +
> +	ndelay(100);
> +
> +	if ((command == NAND_CMD_READ0) ||
> +	    (command == NAND_CMD_RESET) ||
> +	    (command == NAND_CMD_PARAM) ||
> +	    (command == NAND_CMD_GET_FEATURES)) {
> +		while (!chip->dev_ready(mtd))
> +				;

Timeout?

> +		return;
> +	}
> +}

That "return;" does nothing.

> +/*
> + * zynq_nand_read_buf - read chip data into buffer
> + * @mtd:        MTD device structure
> + * @buf:        buffer to store date
> + * @len:        number of bytes to read
> + */
> +static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
> +{
> +	struct nand_chip *chip = mtd->priv;
> +	const u32 *nand = chip->IO_ADDR_R;
> +
> +	/* Make sure that buf is 32 bit aligned */
> +	if (((int)buf & 0x3) != 0) {
> +		if (((int)buf & 0x1) != 0) {
> +			if (len) {
> +				*buf = readb(nand);
> +				buf += 1;
> +				len--;
> +			}
> +		}

Don't cast pointers to "int".  Use (unsigned) long or (u)intptr_t.

> +		if (((int)buf & 0x3) != 0) {
> +			if (len >= 2) {
> +				*(u16 *)buf = readw(nand);

I believe this violates C99 aliasing rules.

> +				buf += 2;
> +				len -= 2;
> +			}
> +		}
> +	}
> +
> +	/* copy aligned data */
> +	while (len >= 4) {
> +		*(u32 *)buf = readl(nand);

Likewise.

For why GCC doesn't complain (or at least a characterization of when it
doesn't complain), see this:
http://cellperformance.beyond3d.com/articles/2006/06/understanding-strict-aliasing.html

That said, I'm not sure how one would do this without violating strict
aliasing (other than with inline asm), and as long as this function
never gets inlined, GCC should produce code that's OK.

> +static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
> +{
> +	struct zynq_nand_info *xnand;
> +	struct mtd_info *mtd;
> +	unsigned long ecc_page_size;
> +	int err = -1;
> +	u8 maf_id, dev_id, i;
> +	u8 get_feature[4];
> +	u8 set_feature[4] = {0x08, 0x00, 0x00, 0x00};
> +	unsigned long ecc_cfg;
> +	int ondie_ecc_enabled = 0;

Does that 0x08 have a symbolic name?

> 	if (ondie_ecc_enabled) {
> +		/* bypass the controller ECC block */
> +		ecc_cfg = readl(&zynq_nand_smc_base->emcr);
> +		ecc_cfg &= ~0xc;
> +		writel(ecc_cfg, &zynq_nand_smc_base->emcr);
> +
> +		/* The software ECC routines won't work
> +		 * with the SMC controller
> +		 */
> +		nand_chip->ecc.mode = NAND_ECC_HW;
> +		nand_chip->ecc.strength = 1;
> +		nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
> +		nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
> +		nand_chip->ecc.write_page = zynq_nand_write_page_raw;
> +		nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
> +		nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
> +		nand_chip->ecc.read_oob = zynq_nand_read_oob;
> +		nand_chip->ecc.write_oob = zynq_nand_write_oob;
> +		nand_chip->ecc.size = mtd->writesize;
> +		nand_chip->ecc.bytes = 0;
> +
> +		/* NAND with on-die ECC supports subpage reads */
> +		nand_chip->options |= NAND_SUBPAGE_READ;
> +
> +		/* On-Die ECC spare bytes offset 8 is used for ECC codes */
> +		if (ondie_ecc_enabled) {
> +			nand_chip->ecc.layout = &ondie_nand_oob_64;
> +			/* Use the BBT pattern descriptors */
> +			nand_chip->bbt_td = &bbt_main_descr;
> +			nand_chip->bbt_md = &bbt_mirror_descr;
> +		}
> +	} else {
> +		/* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
> +		nand_chip->ecc.mode = NAND_ECC_HW;
> +		nand_chip->ecc.strength = 1;
> +		nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
> +		nand_chip->ecc.bytes = 3;
> +		nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
> +		nand_chip->ecc.correct = zynq_nand_correct_data;
> +		nand_chip->ecc.hwctl = NULL;
> +		nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
> +		nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
> +		nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
> +		nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
> +		nand_chip->ecc.read_oob = zynq_nand_read_oob;
> +		nand_chip->ecc.write_oob = zynq_nand_write_oob;
> +
> +		switch (mtd->writesize) {
> +		case 512:
> +			ecc_page_size = 0x1;
> +			/* Set the ECC memory config register */
> +			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
> +			       &zynq_nand_smc_base->emcr);
> +			break;
> +		case 1024:
> +			ecc_page_size = 0x2;
> +			/* Set the ECC memory config register */
> +			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
> +			       &zynq_nand_smc_base->emcr);
> +			break;
> +		case 2048:
> +			ecc_page_size = 0x3;
> +			/* Set the ECC memory config register */
> +			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
> +			       &zynq_nand_smc_base->emcr);
> +			break;
> +		default:
> +			/* The software ECC routines won't work with
> +			 * the SMC controller
> +			 */
> +			nand_chip->ecc.mode = NAND_ECC_HW;
> +			nand_chip->ecc.calculate = nand_calculate_ecc;
> +			nand_chip->ecc.correct = nand_correct_data;
> +			nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
> +			/* nand_chip->ecc.read_subpage = nand_read_subpage; */
> +			nand_chip->ecc.write_page = zynq_nand_write_page_swecc;

Why do you have NAND_ECC_HW together with zynq_nand_*_page_swecc?

> +			nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
> +			nand_chip->ecc.write_page_raw =
> +						zynq_nand_write_page_raw;
> +			nand_chip->ecc.read_oob = zynq_nand_read_oob;
> +			nand_chip->ecc.write_oob = zynq_nand_write_oob;
> +			nand_chip->ecc.size = 256;
> +			nand_chip->ecc.bytes = 3;
> +			break;
> +		}
> +
> +		if (mtd->oobsize == 16)
> +			nand_chip->ecc.layout = &nand_oob_16;
> +		else if (mtd->oobsize == 64)
> +			nand_chip->ecc.layout = &nand_oob_64;
> +		else
> +			;
> +	}

There seems to be some duplicated things above that do the same thing on
every possible code path (or even multiple times on the same codepath,
such as setting nand_chip->ecc.mode to NAND_ECC_HW).

And again, get rid of that do-nothing "else".

-Scott

[U-Boot] [PATCH 23/34] zynq-common: Define CONFIG_NAND_ZYNQ

[Jagannadha Sutradharudu Teki]

Defined CONFIG_NAND_ZYNQ for enabling zynq nand controller with
onfi detection support.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index ffe1b93..97b49d4 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -102,6 +102,16 @@
 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 
+/* NAND */
+#ifdef CONFIG_NAND_ZYNQ
+# define CONFIG_CMD_NAND
+# define CONFIG_CMD_NAND_LOCK_UNLOCK
+# define CONFIG_SYS_MAX_NAND_DEVICE	1
+# define CONFIG_SYS_NAND_SELF_INIT
+# define CONFIG_SYS_NAND_ONFI_DETECTION
+# define CONFIG_MTD_DEVICE
+#endif
+
 /* MMC */
 #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
 # define CONFIG_MMC
-- 
1.8.3

[U-Boot] [PATCH 23/34] zynq-common: Define CONFIG_NAND_ZYNQ

[Scott Wood]

On Tue, 2013-11-05 at 23:16 +0530, Jagannadha Sutradharudu Teki wrote:
> Defined CONFIG_NAND_ZYNQ for enabling zynq nand controller with
> onfi detection support.

Please add it to the README.

-Scott

[U-Boot] [PATCH 24/34] zynq: Add zynq_zc770 xm011 board support

[Jagannadha Sutradharudu Teki]

ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013

ZC770 XM011:
- 1GB DDR3
- 8 and 16-bit Micron NAND devices
- USB-UART

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 boards.cfg                   | 1 +
 include/configs/zynq_zc770.h | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/boards.cfg b/boards.cfg
index 9afcfd1..9ec9794 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -348,6 +348,7 @@ Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc70x				-
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zed				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_microzed			-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm010			zynq_zc770:ZC770_XM010                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
+Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm011			zynq_zc770:ZC770_XM011                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm012			zynq_zc770:ZC770_XM012                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm013			zynq_zc770:ZC770_XM013                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
index 9e7ba77..959122c 100644
--- a/include/configs/zynq_zc770.h
+++ b/include/configs/zynq_zc770.h
@@ -21,6 +21,10 @@
 # define CONFIG_ZYNQ_SDHCI0
 # define CONFIG_ZYNQ_QSPI
 
+#elif defined(CONFIG_ZC770_XM011)
+# define CONFIG_ZYNQ_SERIAL_UART1
+# define CONFIG_NAND_ZYNQ
+
 #elif defined(CONFIG_ZC770_XM012)
 # define CONFIG_ZYNQ_SERIAL_UART1
 # undef CONFIG_SYS_NO_FLASH
-- 
1.8.3

[U-Boot] [PATCH 25/34] zynq: Add support to find bootmode

[Jagannadha Sutradharudu Teki]

Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.

Added this functionality on board_late_init as it's not
needed for normal initializtion part.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 arch/arm/cpu/armv7/zynq/slcr.c             |  6 ++++++
 arch/arm/include/asm/arch-zynq/sys_proto.h |  1 +
 board/xilinx/zynq/board.c                  | 33 ++++++++++++++++++++++++++++++
 include/configs/zynq-common.h              |  1 +
 4 files changed, 41 insertions(+)

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 717ec65..b4c11c3 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -101,6 +101,12 @@ void zynq_slcr_devcfg_enable(void)
 	zynq_slcr_lock();
 }
 
+u32 zynq_slcr_get_boot_mode(void)
+{
+	/* Get the bootmode register value */
+	return readl(&slcr_base->boot_mode);
+}
+
 u32 zynq_slcr_get_idcode(void)
 {
 	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 110de90..8f925af 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -13,6 +13,7 @@ extern void zynq_slcr_cpu_reset(void);
 extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
 extern void zynq_slcr_devcfg_disable(void);
 extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_boot_mode(void);
 extern u32 zynq_slcr_get_idcode(void);
 extern void zynq_ddrc_init(void);
 
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 5119c09..7d1063d 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -12,6 +12,14 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Bootmode setting values */
+#define BOOT_MODES_MASK		0x0000000F
+#define QSPI_MODE		0x00000001
+#define NOR_FLASH_MODE		0x00000002
+#define NAND_FLASH_MODE		0x00000004
+#define SD_MODE			0x00000005
+#define JTAG_MODE		0x00000000
+
 #ifdef CONFIG_FPGA
 Xilinx_desc fpga;
 
@@ -59,6 +67,31 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	switch ((zynq_slcr_get_boot_mode()) & BOOT_MODES_MASK) {
+	case QSPI_MODE:
+		setenv("modeboot", "qspiboot");
+		break;
+	case NAND_FLASH_MODE:
+		setenv("modeboot", "nandboot");
+		break;
+	case NOR_FLASH_MODE:
+		setenv("modeboot", "norboot");
+		break;
+	case SD_MODE:
+		setenv("modeboot", "sdboot");
+		break;
+	case JTAG_MODE:
+		setenv("modeboot", "jtagboot");
+		break;
+	default:
+		setenv("modeboot", "");
+		break;
+	}
+
+	return 0;
+}
 
 #ifdef CONFIG_CMD_NET
 int board_eth_init(bd_t *bis)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 97b49d4..c823036 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -162,6 +162,7 @@
 
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_MAXARGS		15 /* max number of command args */
 #define CONFIG_SYS_CBSIZE		256 /* Console I/O Buffer Size */
-- 
1.8.3

[U-Boot] [PATCH 25/34] zynq: Add support to find bootmode

[Tom Rini]

On Tue, Nov 05, 2013 at 11:16:46PM +0530, Jagannadha Sutradharudu Teki wrote:

> Added support to find the bootmodes by reading
> slcr bootmode register. this can be helpful to
> autoboot the configurations w.r.t a specified bootmode.
> 
> Added this functionality on board_late_init as it's not
> needed for normal initializtion part.
> 
> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
[snip]
> +int board_late_init(void)
> +{
> +	switch ((zynq_slcr_get_boot_mode()) & BOOT_MODES_MASK) {
> +	case QSPI_MODE:
> +		setenv("modeboot", "qspiboot");
> +		break;
> +	case NAND_FLASH_MODE:
> +		setenv("modeboot", "nandboot");
> +		break;
> +	case NOR_FLASH_MODE:
> +		setenv("modeboot", "norboot");
> +		break;
> +	case SD_MODE:
> +		setenv("modeboot", "sdboot");
> +		break;
> +	case JTAG_MODE:
> +		setenv("modeboot", "jtagboot");
> +		break;
> +	default:
> +		setenv("modeboot", "");
> +		break;
> +	}

Please document this variable somewhere because I'd like to make use of
it on am335x/am43xx boards as well.

-- 
Tom
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[U-Boot] [PATCH 26/34] zynq-common: Define default environment

[Jagannadha Sutradharudu Teki]

Defined default env. for autoboot FIT image from
respective boot devices.

Default settings:
fit_image=fit.itb
load_addr=0x2000000
fit_size=0x800000
flash_off=0x100000
nor_flash_off=0xE2100000

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index c823036..9586261 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -153,7 +153,35 @@
 /* Environment */
 #define CONFIG_ENV_SIZE		0x10000 /* Env. sector size */
 #define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_SYS_LOAD_ADDR	0
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fit_image=fit.itb\0"		\
+	"load_addr=0x2000000\0"		\
+	"fit_size=0x800000\0"		\
+	"flash_off=0x100000\0"		\
+	"nor_flash_off=0xE2100000\0"	\
+	"fdt_high=0x20000000\0"		\
+	"initrd_high=0x20000000\0"	\
+	"qspiboot=echo Copying FIT from QSPI flash to RAM... && " \
+		"sf probe 0 0 0 && " \
+		"sf read ${load_addr} ${flash_off} ${fit_size} && " \
+		"bootm ${load_addr}\0" \
+	"norboot=echo Copying FIT from NOR flash to RAM... && " \
+		"cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
+		"bootm ${load_addr}\0" \
+	"nandboot=echo Copying FIT from NAND flash to RAM... && " \
+		"nand read ${load_addr} ${flash_off} ${fit_size} && " \
+		"bootm ${load_addr}\0" \
+	"sdboot=echo Copying FIT from SD to RAM... && " \
+		"fatload mmc 0 ${load_addr} ${fit_image} && " \
+		"bootm ${load_addr}\0" \
+	"jtagboot=echo TFTPing FIT to RAM... && " \
+		"tftp ${load_addr} ${fit_image} && " \
+		"bootm ${load_addr}\0"
+#define CONFIG_BOOTCOMMAND		"run $modeboot"
+#define CONFIG_BOOTDELAY		3 /* -1 to Disable autoboot */
+#define CONFIG_SYS_LOAD_ADDR		0 /* default? */
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_PROMPT		"zynq-uboot> "
-- 
1.8.3

[U-Boot] [PATCH 27/34] zynq-common: Change Env. Sector size to 128Kb

[Jagannadha Sutradharudu Teki]

Changed Env. Sector size from 0x10000 to 128Kb

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 9586261..f571349 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -150,8 +150,10 @@
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_MAY_FAIL
 
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
 /* Environment */
-#define CONFIG_ENV_SIZE		0x10000 /* Env. sector size */
 #define CONFIG_ENV_IS_NOWHERE
 
 /* Default environment */
-- 
1.8.3

[U-Boot] [PATCH 28/34] zynq-common: Define flash env. partition

[Jagannadha Sutradharudu Teki]

Last 128Kb sector of 1Mb flash is defined as u-boot
environment partition.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index f571349..aed9f1f 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -154,7 +154,21 @@
 #define CONFIG_ENV_SIZE			(128 << 10)
 
 /* Environment */
-#define CONFIG_ENV_IS_NOWHERE
+#ifndef CONFIG_ENV_IS_NOWHERE
+# ifndef CONFIG_SYS_NO_FLASH
+#  define CONFIG_ENV_IS_IN_FLASH
+# elif defined(CONFIG_ZYNQ_QSPI)
+#  define CONFIG_ENV_IS_IN_SPI_FLASH
+# elif defined(CONFIG_NAND_ZYNQ)
+#  define CONFIG_ENV_IS_IN_NAND
+# elif defined(CONFIG_SYS_NO_FLASH)
+#  define CONFIG_ENV_IS_NOWHERE
+# endif
+
+# define CONFIG_ENV_SECT_SIZE		CONFIG_ENV_SIZE
+# define CONFIG_ENV_OFFSET		0xE0000
+# define CONFIG_CMD_SAVEENV
+#endif
 
 /* Default environment */
 #define CONFIG_EXTRA_ENV_SETTINGS	\
-- 
1.8.3

[U-Boot] [PATCH 29/34] zynq-common: Define CONFIG_ENV_OVERWRITE

[Jagannadha Sutradharudu Teki]

Defined CONFIG_ENV_OVERWRITE, which allow to
overwrite serial baudrate and ethaddr.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index aed9f1f..1a907a1 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -153,6 +153,9 @@
 /* Total Size of Environment Sector */
 #define CONFIG_ENV_SIZE			(128 << 10)
 
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
 /* Environment */
 #ifndef CONFIG_ENV_IS_NOWHERE
 # ifndef CONFIG_SYS_NO_FLASH
-- 
1.8.3

[U-Boot] [PATCH 30/34] zynq-common: Define ethaddr in default env.

[Jagannadha Sutradharudu Teki]

Defined default ethaddr for zynq GEM as 00:0a:35:00:01:22

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 1a907a1..52c6f52 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -175,6 +175,7 @@
 
 /* Default environment */
 #define CONFIG_EXTRA_ENV_SETTINGS	\
+	"ethaddr=00:0a:35:00:01:22\0"	\
 	"fit_image=fit.itb\0"		\
 	"load_addr=0x2000000\0"		\
 	"fit_size=0x800000\0"		\
-- 
1.8.3

[U-Boot] [PATCH 30/34] zynq-common: Define ethaddr in default env.

[Tom Rini]

On Tue, Nov 05, 2013 at 11:16:51PM +0530, Jagannadha Sutradharudu Teki wrote:

> Defined default ethaddr for zynq GEM as 00:0a:35:00:01:22
> 
> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
> ---
>  include/configs/zynq-common.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
> index 1a907a1..52c6f52 100644
> --- a/include/configs/zynq-common.h
> +++ b/include/configs/zynq-common.h
> @@ -175,6 +175,7 @@
>  
>  /* Default environment */
>  #define CONFIG_EXTRA_ENV_SETTINGS	\
> +	"ethaddr=00:0a:35:00:01:22\0"	\
>  	"fit_image=fit.itb\0"		\
>  	"load_addr=0x2000000\0"		\
>  	"fit_size=0x800000\0"		\

NAK, this simply isn't allowed.

-- 
Tom
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[U-Boot] [PATCH 31/34] dts: zynq: Add basic fdt support

[Jagannadha Sutradharudu Teki]

This patch provides a basic fdt support for zynq u-boot.

zynq-7000.dtsi-> initial arch dts file
zynq-zed.dts -> initial zed board dts file
more devices should be added in subsequent patches.

u-boot build: once configuring of a board done
for building dtb with zynq-zed.dts as an input
zynq-uboot> make DEVICE_TREE=zynq-zed

Enabled CONFIG_OF_SEPARATE for building dtb separately.
There is a new binary called u-boot-dtb.bin which is a u-boot
with devicetree supported.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 arch/arm/dts/zynq-7000.dtsi   | 13 +++++++++++++
 board/xilinx/dts/zynq-zed.dts | 14 ++++++++++++++
 include/configs/zynq-common.h |  5 +++++
 3 files changed, 32 insertions(+)
 create mode 100644 arch/arm/dts/zynq-7000.dtsi
 create mode 100644 board/xilinx/dts/zynq-zed.dts

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
new file mode 100644
index 0000000..f20b8bd
--- /dev/null
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Xilinx Zynq 7000 DTSI
+ * Describes the hardware common to all Zynq 7000-based boards.
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zed.dts b/board/xilinx/dts/zynq-zed.dts
new file mode 100644
index 0000000..91a5deb
--- /dev/null
+++ b/board/xilinx/dts/zynq-zed.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZED board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZED Board";
+	compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+};
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 52c6f52..43d74e9 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -247,6 +247,11 @@
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
 
+/* FDT support */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
 /* Boot FreeBSD/vxWorks from an ELF image */
 #if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
 # define CONFIG_API
-- 
1.8.3

[U-Boot] [PATCH 32/34] gpio: zynq: Add dummy gpio routines

[Jagannadha Sutradharudu Teki]

GPIO dummy routines are required for fdt build, may be removed
these dependencies once the u-boot fdt is fully optimized.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 arch/arm/include/asm/arch-zynq/gpio.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-zynq/gpio.h

diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h
new file mode 100644
index 0000000..2dbba75
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/gpio.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ZYNQ_GPIO_H
+#define _ZYNQ_GPIO_H
+
+inline int gpio_get_value(unsigned gpio)
+{
+	return 0;
+}
+
+inline int gpio_set_value(unsigned gpio, int val)
+{
+	return 0;
+}
+
+inline int gpio_request(unsigned gpio, const char *label)
+{
+	return 0;
+}
+
+#endif /* _ZYNQ_GPIO_H */
-- 
1.8.3

[U-Boot] [PATCH 33/34] zynq-common: Enable verified boot(RSA)

[Jagannadha Sutradharudu Teki]

CONFIG_FIT_SIGNATURE - signature node support in FIT image
CONFIG_RSA - RSA lib support

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 include/configs/zynq-common.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 43d74e9..45fe75d 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -252,6 +252,10 @@
 #define CONFIG_OF_SEPARATE
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 
+/* RSA support */
+#define CONFIG_FIT_SIGNATURE
+#define CONFIG_RSA
+
 /* Boot FreeBSD/vxWorks from an ELF image */
 #if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
 # define CONFIG_API
-- 
1.8.3

[U-Boot] [PATCH 34/34] dts: zynq: Add more zynq dts files

[Jagannadha Sutradharudu Teki]

This patch adds initial dts support for supported
zynq boards.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 board/xilinx/dts/zynq-microzed.dts    | 14 ++++++++++++++
 board/xilinx/dts/zynq-zc702.dts       | 14 ++++++++++++++
 board/xilinx/dts/zynq-zc706.dts       | 14 ++++++++++++++
 board/xilinx/dts/zynq-zc770-xm010.dts | 14 ++++++++++++++
 board/xilinx/dts/zynq-zc770-xm011.dts | 14 ++++++++++++++
 board/xilinx/dts/zynq-zc770-xm012.dts | 14 ++++++++++++++
 board/xilinx/dts/zynq-zc770-xm013.dts | 14 ++++++++++++++
 7 files changed, 98 insertions(+)
 create mode 100644 board/xilinx/dts/zynq-microzed.dts
 create mode 100644 board/xilinx/dts/zynq-zc702.dts
 create mode 100644 board/xilinx/dts/zynq-zc706.dts
 create mode 100644 board/xilinx/dts/zynq-zc770-xm010.dts
 create mode 100644 board/xilinx/dts/zynq-zc770-xm011.dts
 create mode 100644 board/xilinx/dts/zynq-zc770-xm012.dts
 create mode 100644 board/xilinx/dts/zynq-zc770-xm013.dts

diff --git a/board/xilinx/dts/zynq-microzed.dts b/board/xilinx/dts/zynq-microzed.dts
new file mode 100644
index 0000000..6da71c1
--- /dev/null
+++ b/board/xilinx/dts/zynq-microzed.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx MicroZED board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq MicroZED Board";
+	compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zc702.dts b/board/xilinx/dts/zynq-zc702.dts
new file mode 100644
index 0000000..667dc28
--- /dev/null
+++ b/board/xilinx/dts/zynq-zc702.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC702 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC702 Board";
+	compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zc706.dts b/board/xilinx/dts/zynq-zc706.dts
new file mode 100644
index 0000000..526fc88
--- /dev/null
+++ b/board/xilinx/dts/zynq-zc706.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC706 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC706 Board";
+	compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zc770-xm010.dts b/board/xilinx/dts/zynq-zc770-xm010.dts
new file mode 100644
index 0000000..8b542a1
--- /dev/null
+++ b/board/xilinx/dts/zynq-zc770-xm010.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM010 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC770 XM010 Board";
+	compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zc770-xm011.dts b/board/xilinx/dts/zynq-zc770-xm011.dts
new file mode 100644
index 0000000..12a6d52
--- /dev/null
+++ b/board/xilinx/dts/zynq-zc770-xm011.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM011 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC770 XM011 Board";
+	compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zc770-xm012.dts b/board/xilinx/dts/zynq-zc770-xm012.dts
new file mode 100644
index 0000000..0379a07
--- /dev/null
+++ b/board/xilinx/dts/zynq-zc770-xm012.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM012 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC770 XM012 Board";
+	compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+};
diff --git a/board/xilinx/dts/zynq-zc770-xm013.dts b/board/xilinx/dts/zynq-zc770-xm013.dts
new file mode 100644
index 0000000..a4f9e05
--- /dev/null
+++ b/board/xilinx/dts/zynq-zc770-xm013.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM013 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC770 XM013 Board";
+	compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+};
-- 
1.8.3