[U-Boot] [RESEND PATCH v14 07/10] arm64: core support

[York Sun <yorksun@freescale.com>]

On 10/14/2013 08:34 PM, fenghua at phytium.com.cn wrote:
> From: David Feng <fenghua@phytium.com.cn>
> 
> Relocation code based on a patch by Scott Wood, which is:
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> 
> Signed-off-by: David Feng <fenghua@phytium.com.cn>
> ---
>  arch/arm/config.mk                      |    3 +-
>  arch/arm/cpu/armv8/Makefile             |   38 +++++
>  arch/arm/cpu/armv8/cache.S              |  130 +++++++++++++++++

<snip>

> diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
> new file mode 100644
> index 0000000..419f169
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/cache.S
> @@ -0,0 +1,130 @@
> +/*
> + * (C) Copyright 2013
> + * David Feng <fenghua@phytium.com.cn>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <asm-offsets.h>
> +#include <config.h>
> +#include <version.h>
> +#include <asm/macro.h>
> +#include <linux/linkage.h>
> +
> +/*
> + * void __asm_flush_dcache_level(level)
> + *
> + * clean and invalidate one level cache.
> + *
> + * x0: cache level
> + * x1~x9: clobbered
> + */
> +ENTRY(__asm_flush_dcache_level)
> +	lsl	x1, x0, #1
> +	msr	csselr_el1, x1		/* select cache level */
> +	isb				/* isb to sych the new cssr & csidr */
> +	mrs	x6, ccsidr_el1		/* read the new ccsidr */
> +	and	x2, x6, #7		/* x2 <- length of the cache lines */
> +	add	x2, x2, #4		/* add 4 (line length offset) */
> +	mov	x3, #0x3ff
> +	and	x3, x3, x6, lsr #3	/* x3 <- maximum number of way size */
> +	clz	w5, w3			/* bit position of way size */
> +	mov	x4, #0x7fff
> +	and	x4, x4, x1, lsr #13	/* x4 <- max number of the set size */

Shouldn't this x1 be x6?


> +	/* x1 <- cache level << 1 */
> +	/* x2 <- line length offset */
> +	/* x3 <- number of cache ways */
> +	/* x4 <- number of cache sets */
> +	/* x5 <- bit position of way size */
> +
> +loop_set:
> +	mov	x6, x3			/* create working copy of way size */
> +loop_way:
> +	lsl	x7, x6, x5
> +	orr	x9, x0, x7		/* map way and level to cisw value */

Shouldn't this x0 be x1?

> +	lsl	x7, x4, x2
> +	orr	x9, x9, x7		/* map set number to cisw value */
> +	dc	cisw, x9		/* clean & invalidate by set/way */
> +	subs	x6, x6, #1		/* decrement the way */
> +	b.ge	loop_way
> +	subs	x4, x4, #1		/* decrement the set */
> +	b.ge	loop_set
> +
> +	ret
> +ENDPROC(__asm_flush_dcache_level)
> +

I haven't been able to verify this change. It simply takes too long to
finish on emulator.

York