* [U-Boot] [PATCH] pcm051: Support for revision 3
@ 2013-11-19 10:22 Lars Poeschel
2013-11-19 20:08 ` Tom Rini
2013-12-04 22:04 ` [U-Boot] " Tom Rini
0 siblings, 2 replies; 5+ messages in thread
From: Lars Poeschel @ 2013-11-19 10:22 UTC (permalink / raw)
To: u-boot
From: Lars Poeschel <poeschel@lemonage.de>
Phytec sells revision or version 3 of pcm051. It is labeled 1358.3 on
the board. The difference for u-boot is that is has other DDR3 RAM on it:
1 x MT41K256M16HA125E instead of 2 x MT41J256M8HX15E on revisions 1 and
2. Both configurations are 512 MiB.
Configure your u-boot build with pcm051_rev3 for the new RAM and
pcm051_rev1 for the old RAM configuration. Board revision 2 has to use
pcm051_rev1 also.
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
---
board/phytec/pcm051/board.c | 53 ++++++++++++++++++++++++++++++++++++++++-----
boards.cfg | 3 ++-
2 files changed, 49 insertions(+), 7 deletions(-)
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index e40b0bd..629bc52 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -49,6 +49,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
return &dpll_ddr;
}
+#ifdef CONFIG_REV1
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J256M8HX15E_RD_DQS,
.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
@@ -82,6 +83,52 @@ static struct emif_regs ddr3_emif_reg_data = {
PHY_EN_DYN_PWRDN,
};
+void sdram_init(void)
+{
+ config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#else
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+ config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif
+
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
@@ -95,12 +142,6 @@ void set_mux_conf_regs(void)
enable_board_pin_mux();
}
-
-void sdram_init(void)
-{
- config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
#endif
/*
diff --git a/boards.cfg b/boards.cfg
index 9fc77fb..c2e24d6 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -244,7 +244,8 @@ Active arm armv7 - armltd vexpress
Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org>
Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org>
Active arm armv7 am33xx isee igep0033 igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
-Active arm armv7 am33xx phytec pcm051 pcm051 pcm051 Lars Poeschel <poeschel@lemonage.de>
+Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
+Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de>
Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
--
1.8.4.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] pcm051: Support for revision 3
2013-11-19 10:22 [U-Boot] [PATCH] pcm051: Support for revision 3 Lars Poeschel
@ 2013-11-19 20:08 ` Tom Rini
2013-11-21 10:05 ` Lars Poeschel
2013-12-04 22:04 ` [U-Boot] " Tom Rini
1 sibling, 1 reply; 5+ messages in thread
From: Tom Rini @ 2013-11-19 20:08 UTC (permalink / raw)
To: u-boot
On Tue, Nov 19, 2013 at 11:22:18AM +0100, Lars Poeschel wrote:
> From: Lars Poeschel <poeschel@lemonage.de>
>
> Phytec sells revision or version 3 of pcm051. It is labeled 1358.3 on
> the board. The difference for u-boot is that is has other DDR3 RAM on it:
> 1 x MT41K256M16HA125E instead of 2 x MT41J256M8HX15E on revisions 1 and
> 2. Both configurations are 512 MiB.
> Configure your u-boot build with pcm051_rev3 for the new RAM and
> pcm051_rev1 for the old RAM configuration. Board revision 2 has to use
> pcm051_rev1 also.
>
> Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
Is there no run-time way to tell if we're on rev1/2/3?
--
Tom
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] pcm051: Support for revision 3
2013-11-19 20:08 ` Tom Rini
@ 2013-11-21 10:05 ` Lars Poeschel
2013-11-21 13:18 ` Tom Rini
0 siblings, 1 reply; 5+ messages in thread
From: Lars Poeschel @ 2013-11-21 10:05 UTC (permalink / raw)
To: u-boot
Am Dienstag, 19. November 2013, 15:08:27 schrieb Tom Rini:
> On Tue, Nov 19, 2013 at 11:22:18AM +0100, Lars Poeschel wrote:
> > From: Lars Poeschel <poeschel@lemonage.de>
> >
> > Phytec sells revision or version 3 of pcm051. It is labeled 1358.3 on
> > the board. The difference for u-boot is that is has other DDR3 RAM on it:
> > 1 x MT41K256M16HA125E instead of 2 x MT41J256M8HX15E on revisions 1 and
> > 2. Both configurations are 512 MiB.
> > Configure your u-boot build with pcm051_rev3 for the new RAM and
> > pcm051_rev1 for the old RAM configuration. Board revision 2 has to use
> > pcm051_rev1 also.
> >
> > Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
>
> Is there no run-time way to tell if we're on rev1/2/3?
Unfortunately I am not aware of a 100% bullet proof one.
One way would be to read the AM3359 silicon ID. I have two boards here: rev1
and rev3. The phytec rev3 board has a newer silicon on it. I don't know about
rev2's silicon ID. And I am not sure if the rev3 silicon change directly
corresponds to the DDR RAM change and if all rev3 boards have the new silicon.
What I know for sure is that the RAM change was with rev3.
Nevertheless phytec itself supplies a patched barebox as bootloader. And they
have a compile time config option for different RAM configurations of the board.
And they even seem to have more RAM configurations than the two I have seen
yet.
Lars
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] pcm051: Support for revision 3
2013-11-21 10:05 ` Lars Poeschel
@ 2013-11-21 13:18 ` Tom Rini
0 siblings, 0 replies; 5+ messages in thread
From: Tom Rini @ 2013-11-21 13:18 UTC (permalink / raw)
To: u-boot
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 11/21/2013 05:05 AM, Lars Poeschel wrote:
> Am Dienstag, 19. November 2013, 15:08:27 schrieb Tom Rini:
>> On Tue, Nov 19, 2013 at 11:22:18AM +0100, Lars Poeschel wrote:
>>> From: Lars Poeschel <poeschel@lemonage.de>
>>>
>>> Phytec sells revision or version 3 of pcm051. It is labeled
>>> 1358.3 on the board. The difference for u-boot is that is has
>>> other DDR3 RAM on it: 1 x MT41K256M16HA125E instead of 2 x
>>> MT41J256M8HX15E on revisions 1 and 2. Both configurations are
>>> 512 MiB. Configure your u-boot build with pcm051_rev3 for the
>>> new RAM and pcm051_rev1 for the old RAM configuration. Board
>>> revision 2 has to use pcm051_rev1 also.
>>>
>>> Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
>>
>> Is there no run-time way to tell if we're on rev1/2/3?
>
> Unfortunately I am not aware of a 100% bullet proof one. One way
> would be to read the AM3359 silicon ID. I have two boards here:
> rev1 and rev3. The phytec rev3 board has a newer silicon on it. I
> don't know about rev2's silicon ID. And I am not sure if the rev3
> silicon change directly corresponds to the DDR RAM change and if
> all rev3 boards have the new silicon. What I know for sure is that
> the RAM change was with rev3. Nevertheless phytec itself supplies a
> patched barebox as bootloader. And they have a compile time config
> option for different RAM configurations of the board. And they even
> seem to have more RAM configurations than the two I have seen yet.
OK, thanks.
- --
Tom
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] pcm051: Support for revision 3
2013-11-19 10:22 [U-Boot] [PATCH] pcm051: Support for revision 3 Lars Poeschel
2013-11-19 20:08 ` Tom Rini
@ 2013-12-04 22:04 ` Tom Rini
1 sibling, 0 replies; 5+ messages in thread
From: Tom Rini @ 2013-12-04 22:04 UTC (permalink / raw)
To: u-boot
On Tue, Nov 19, 2013 at 11:22:18AM +0100, Lars Poeschel wrote:
> From: Lars Poeschel <poeschel@lemonage.de>
>
> Phytec sells revision or version 3 of pcm051. It is labeled 1358.3 on
> the board. The difference for u-boot is that is has other DDR3 RAM on it:
> 1 x MT41K256M16HA125E instead of 2 x MT41J256M8HX15E on revisions 1 and
> 2. Both configurations are 512 MiB.
> Configure your u-boot build with pcm051_rev3 for the new RAM and
> pcm051_rev1 for the old RAM configuration. Board revision 2 has to use
> pcm051_rev1 also.
>
> Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
Applied to u-boot-ti/master, after adapting to my change about not
touching some EMIF4D registers, :thanks!
--
Tom
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2013-11-19 10:22 [U-Boot] [PATCH] pcm051: Support for revision 3 Lars Poeschel
2013-11-19 20:08 ` Tom Rini
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2013-11-21 13:18 ` Tom Rini
2013-12-04 22:04 ` [U-Boot] " Tom Rini
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