[U-Boot] [PATCH 3/4] powerpc/t2080qds: add support for t2080qds board

[York Sun <yorksun@freescale.com>]

On 11/14/2013 03:32 AM, Shengzhou Liu wrote:
> The T2080QDS is a high-performance computing evaluation, development and
> test platform supporting the T2080 QorIQ Power Architecture processor.
> 
> T2080QDS feature overview
> Processor:
>  - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
> Memory:
>  - Single memory controller capable of supporting DDR3 and DDR3-LV devices
>  - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
> Ethernet interfaces:
>  - Two 1Gbps RGMII on-board ports
>  - Four 10Gbps XFI on-board cages
>  - 1Gbps/2.5Gbps SGMII Riser card
>  - 10Gbps XAUI Riser card
> Accelerator:
>  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
> SerDes:
>  - 16 lanes up to 10.3125GHz
>  - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
> IFC:
>  - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
> eSPI:
>  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
> USB:
>  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
> PCIE:
>  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
> SATA:
>  - Two SATA 2.0 ports on-board
> SRIO:
>  - Two Serial RapidIO 2.0 ports up to 5 GHz
> eSDHC:
>  - Supports SD/SDHC/SDXC/eMMC Card
> I2C:
>  - Four I2C controllers.
> UART:
>  - Dual 4-pins UART serial ports
> System Logic:
>  - QIXIS-II FPGA system controll
> Debug Features:
>  - Support Legacy, COP/JTAG, Aurora, Event and EVT
> 
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> ---
> Against master branch of upstream.

Clearly you are sharing most code between T2080 and T2081. I have seen
conditional code for CONFIG_PPC_T2081, but I don't see where this macro
is defined. Do you plan to post T2081QDS as a separated patch, or you
missed it in this one?

York