From: Andre Przywara <andre.przywara@linaro.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/9] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
Date: Tue, 26 Nov 2013 15:39:56 +0100 [thread overview]
Message-ID: <5294B2BC.3020002@linaro.org> (raw)
In-Reply-To: <1385024402-23585-4-git-send-email-marc.zyngier@arm.com>
On 11/21/2013 09:59 AM, Marc Zyngier wrote:
> A CP15 instruction execution can be reordered, requiring an
> isb to be sure it is executed in program order.
Makes sense ;-) and works on the VExpress TC2.
Albert, Tom, please apply for v2014.01.
Acked-by: Andre Przywara <andre.przywara@linaro.org>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> arch/arm/cpu/armv7/nonsec_virt.S | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
> index 29987cd..648066f 100644
> --- a/arch/arm/cpu/armv7/nonsec_virt.S
> +++ b/arch/arm/cpu/armv7/nonsec_virt.S
> @@ -47,6 +47,7 @@ _secure_monitor:
> #endif
>
> mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
> + isb
>
> #ifdef CONFIG_ARMV7_VIRT
> mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
>
next prev parent reply other threads:[~2013-11-26 14:39 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-21 8:59 [U-Boot] [PATCH 0/9] ARMv7: add PSCI support to u-boot Marc Zyngier
2013-11-21 8:59 ` [U-Boot] [PATCH 1/9] ARM: HYP/non-sec: fix alignment requirements for vectors Marc Zyngier
2013-11-21 10:19 ` Masahiro Yamada
2013-11-21 10:36 ` Marc Zyngier
2013-11-21 22:24 ` Andre Przywara
2013-11-21 8:59 ` [U-Boot] [PATCH 2/9] ARM: HYP/non-sec: move switch to non-sec to the last boot phase Marc Zyngier
2013-11-26 14:36 ` Andre Przywara
2013-11-21 8:59 ` [U-Boot] [PATCH 3/9] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1 Marc Zyngier
2013-11-22 1:51 ` Christoffer Dall
2013-11-22 10:56 ` Marc Zyngier
2013-11-22 16:53 ` Christoffer Dall
2013-12-30 3:10 ` [U-Boot] [PATCH 3/9] ARM: HYP/non-sec switch in bootm.c TigerLiu at viatech.com.cn
2013-12-30 4:57 ` Christoffer Dall
2013-12-30 5:15 ` TigerLiu at viatech.com.cn
2013-12-30 5:22 ` Christoffer Dall
2013-12-30 5:33 ` TigerLiu at viatech.com.cn
2013-11-26 14:39 ` Andre Przywara [this message]
2013-11-21 8:59 ` [U-Boot] [PATCH 4/9] ARM: non-sec: reset CNTVOFF to zero Marc Zyngier
2013-11-26 14:41 ` Andre Przywara
2013-11-26 14:46 ` Marc Zyngier
2013-11-21 8:59 ` [U-Boot] [PATCH 5/9] ARM: HYP/non-sec: add generic ARMv7 PSCI code Marc Zyngier
2013-11-21 8:59 ` [U-Boot] [PATCH 6/9] ARM: HYP/non-sec: make pen code sections depend on !ARMV7_PSCI Marc Zyngier
2014-06-04 1:51 ` [U-Boot] [PATCH 6/9] ARM: HYP/non-sec: make pen code sectionsdepend " TigerLiu at via-alliance.com
2013-11-21 9:00 ` [U-Boot] [PATCH 7/9] ARM: HYP/non-sec: add the option for a second-stage monitor Marc Zyngier
2013-11-21 9:00 ` [U-Boot] [PATCH 8/9] sunxi: HYP/non-sec: add sun7i PSCI backend Marc Zyngier
2013-11-21 9:00 ` [U-Boot] [PATCH 9/9] sunxi: HYP/non-sec: configure CNTFRQ on all CPUs Marc Zyngier
2013-11-21 14:28 ` [U-Boot] [PATCH 0/9] ARMv7: add PSCI support to u-boot Rob Herring
2013-11-21 15:04 ` Marc Zyngier
2013-11-22 1:54 ` Christoffer Dall
2013-11-22 3:58 ` Anup Patel
2013-11-22 8:42 ` [U-Boot] [linux-sunxi] " Ian Campbell
2013-11-22 9:00 ` Anup Patel
2013-11-22 16:49 ` Christoffer Dall
2013-11-22 10:25 ` [U-Boot] " Marc Zyngier
2013-11-22 10:51 ` Marc Zyngier
2013-11-22 8:40 ` [U-Boot] [linux-sunxi] " Ian Campbell
2013-11-22 8:56 ` Anup Patel
2013-11-22 10:49 ` Ian Campbell
2013-11-22 14:51 ` Marc Zyngier
2013-12-06 11:43 ` [U-Boot] " Andre Przywara
2013-12-06 12:12 ` Marc Zyngier
2013-12-06 12:59 ` [U-Boot] [linux-sunxi] " Ian Campbell
2013-12-06 15:44 ` Ian Campbell
2013-12-06 15:48 ` Andre Przywara
2013-12-06 17:21 ` Ian Campbell
2013-12-06 17:45 ` Marc Zyngier
2013-12-06 13:03 ` [U-Boot] " Andre Przywara
2013-12-06 16:00 ` Marc Zyngier
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