From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Przywara Date: Tue, 26 Nov 2013 15:39:56 +0100 Subject: [U-Boot] [PATCH 3/9] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1 In-Reply-To: <1385024402-23585-4-git-send-email-marc.zyngier@arm.com> References: <1385024402-23585-1-git-send-email-marc.zyngier@arm.com> <1385024402-23585-4-git-send-email-marc.zyngier@arm.com> Message-ID: <5294B2BC.3020002@linaro.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 11/21/2013 09:59 AM, Marc Zyngier wrote: > A CP15 instruction execution can be reordered, requiring an > isb to be sure it is executed in program order. Makes sense ;-) and works on the VExpress TC2. Albert, Tom, please apply for v2014.01. Acked-by: Andre Przywara > Signed-off-by: Marc Zyngier > --- > arch/arm/cpu/armv7/nonsec_virt.S | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S > index 29987cd..648066f 100644 > --- a/arch/arm/cpu/armv7/nonsec_virt.S > +++ b/arch/arm/cpu/armv7/nonsec_virt.S > @@ -47,6 +47,7 @@ _secure_monitor: > #endif > > mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) > + isb > > #ifdef CONFIG_ARMV7_VIRT > mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value >