From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Wed, 4 Dec 2013 15:43:18 -0800
Subject: [U-Boot] [PATCH] T4240: Address T4240/T4160 Rev2.0 DDR clock
 change
In-Reply-To: <1385616217-25883-1-git-send-email-tie-fei.zang@freescale.com>
References: <1385616217-25883-1-git-send-email-tie-fei.zang@freescale.com>
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On 11/27/2013 09:23 PM, Roy Zang wrote:
> MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
> It's 12 in Rev1.0, for Rev2.0 it uses 6.
> 
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> Reviewed-by: Yusong Sun <yorksun@freescale.com>
> ---


Applied to u-boot-mpc85xx/master. Thanks.

York