From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Thu, 12 Dec 2013 14:24:51 +0100 Subject: [U-Boot] am335x: cpsw: optimize cpsw_recv to increase network performance In-Reply-To: <52A9B800.5020402@streamunlimited.com> References: <52970F20.6070401@streamunlimited.com> <20131204220510.GJ420@bill-the-cat> <52A9752B.9090103@denx.de> <52A9ADFC.3050907@ti.com> <52A9B800.5020402@streamunlimited.com> Message-ID: <52A9B923.4020206@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 12.12.2013 14:20, Vladimir Koutny wrote: > > On 12/12/13 13:37, Tom Rini wrote: >> On 12/12/2013 03:34 AM, Stefan Roese wrote: >>> I just tested on dxr2 (AM3352 based board) with latest mainline >>> U-Boot. And the network performance is a bit better. But not as >>> good as yours. Here my numbers: >> >>> Without this patch: ~400 KiB/s With this patch: ~570 KiB/s >> >>> Any ideas what might be missing on my platform? Why the speed is >>> not as good? >> >> I only got a small increase as well until I also grabbed the dcache >> enable patch. I need to find some time today to clean out the TI >> queue again. >> > > Good point - indeed I had I/D caches enabled for other reasons already > (md5/sha1 caclulations, ..) Hmmm. I expected that caches are enabled already. Since I didn't see any "D-Cache disabled message" in the startup log. If this is not that case, then such cache support would be greatly appreciated. :) Thanks, Stefan