[U-Boot] [PATCH v3 0/8] SATA support for omap5_uevm and dra7_evm

[U-Boot] [PATCH v3 0/8] SATA support for omap5_uevm and dra7_evm

[Roger Quadros]

Hi,

This series adds SATA support for OMAP5 uevm and DRA7 evm.

Patches are also availabe at
 git at github.com:rogerq/u-boot.git	sata

v3:
- get rid of custom perror() macro, use printf
- Fixed coding sytle issues

v2:
- Address review comments in the RFC series
- Fix cache align error in the ahci driver
- Added dra7 support

cheers,
-roger

Roger Quadros (8):
  ahci: Error out with message on malloc() failure
  ahci: Fix cache align error messages
  ARM: OMAP5: Add Pipe3 PHY driver
  ARM: OMAP5: Add PRCM and Control information for SATA
  ARM: OMAP5: Add SATA platform glue
  ARM: omap5_uevm: Add SATA support
  ARM: DRA7xx: Add PRCM and Control information for SATA
  ARM: dra7_evm: Add SATA support

 arch/arm/cpu/armv7/omap-common/Makefile    |   5 +
 arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 231 +++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap-common/pipe3-phy.h |  36 +++++
 arch/arm/cpu/armv7/omap-common/sata.c      |  75 ++++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c       |   7 +
 arch/arm/include/asm/arch-omap5/clock.h    |   3 +
 arch/arm/include/asm/arch-omap5/omap.h     |   3 +
 arch/arm/include/asm/arch-omap5/sata.h     |  48 ++++++
 arch/arm/include/asm/omap_common.h         |   2 +
 board/ti/dra7xx/evm.c                      |   7 +
 board/ti/omap5_uevm/evm.c                  |   7 +
 drivers/block/ahci.c                       |  18 ++-
 include/configs/dra7xx_evm.h               |  11 ++
 include/configs/omap5_uevm.h               |  10 ++
 14 files changed, 457 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h
 create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c
 create mode 100644 arch/arm/include/asm/arch-omap5/sata.h

-- 
1.8.3.2

[U-Boot] [PATCH v3 1/8] ahci: Error out with message on malloc() failure

[Roger Quadros]

If malloc() fails, we don't want to continue in ahci_init() and
ahci_init_one(). Also print a more informative error message on
malloc() failures.

CC: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 drivers/block/ahci.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 0daad36..e24d634 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -379,6 +379,11 @@ static int ahci_init_one(pci_dev_t pdev)
 	int rc;
 
 	probe_ent = malloc(sizeof(struct ahci_probe_ent));
+	if (!probe_ent) {
+		printf("%s: No memory for probe_ent\n", __func__);
+		return -ENOMEM;
+	}
+
 	memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
 	probe_ent->dev = pdev;
 
@@ -503,7 +508,7 @@ static int ahci_port_start(u8 port)
 	mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
 	if (!mem) {
 		free(pp);
-		printf("No mem for table!\n");
+		printf("%s: No mem for table!\n", __func__);
 		return -ENOMEM;
 	}
 
@@ -638,8 +643,10 @@ static int ata_scsiop_inquiry(ccb *pccb)
 	/* Read id from sata */
 	port = pccb->target;
 	tmpid = malloc(ATA_ID_WORDS * 2);
-	if (!tmpid)
+	if (!tmpid) {
+		printf("%s: No memory for tmpid\n", __func__);
 		return -ENOMEM;
+	}
 
 	if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
 				ATA_ID_WORDS * 2, 0)) {
@@ -889,6 +896,11 @@ int ahci_init(u32 base)
 	u32 linkmap;
 
 	probe_ent = malloc(sizeof(struct ahci_probe_ent));
+	if (!probe_ent) {
+		printf("%s: No memory for probe_ent\n", __func__);
+		return -ENOMEM;
+	}
+
 	memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
 
 	probe_ent->host_flags = ATA_FLAG_SATA
-- 
1.8.3.2

[U-Boot] [PATCH v3 2/8] ahci: Fix cache align error messages

[Roger Quadros]

Align the ATA ID buffer to the cache-line boundary. This gets rid
of the below error mesages on ARM v7 platforms.

 scanning bus for devices...
 ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618
 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818

CC: Aneesh V <aneesh@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 drivers/block/ahci.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index e24d634..e64df4f 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -623,7 +623,7 @@ static int ata_scsiop_inquiry(ccb *pccb)
 		95 - 4,
 	};
 	u8 fis[20];
-	u16 *tmpid;
+	ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
 	u8 port;
 
 	/* Clean ccb data buffer */
@@ -642,16 +642,10 @@ static int ata_scsiop_inquiry(ccb *pccb)
 
 	/* Read id from sata */
 	port = pccb->target;
-	tmpid = malloc(ATA_ID_WORDS * 2);
-	if (!tmpid) {
-		printf("%s: No memory for tmpid\n", __func__);
-		return -ENOMEM;
-	}
 
 	if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
 				ATA_ID_WORDS * 2, 0)) {
 		debug("scsi_ahci: SCSI inquiry command failure.\n");
-		free(tmpid);
 		return -EIO;
 	}
 
-- 
1.8.3.2

[U-Boot] [PATCH v3 3/8] ARM: OMAP5: Add Pipe3 PHY driver

[Roger Quadros]

Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is
a driver for the Pipe3 PHY.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/cpu/armv7/omap-common/Makefile    |   4 +
 arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 231 +++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap-common/pipe3-phy.h |  36 +++++
 3 files changed, 271 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 4d3a165..bfaf814 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -17,6 +17,10 @@ obj-y	+= vc.o
 obj-y	+= abb.o
 endif
 
+ifneq ($(CONFIG_OMAP54XX),)
+COBJS	+= pipe3-phy.o
+endif
+
 ifeq ($(CONFIG_OMAP34XX),)
 obj-y	+= boot-common.o
 obj-y	+= lowlevel_init.o
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
new file mode 100644
index 0000000..b71d769
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
@@ -0,0 +1,231 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <sata.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include "pipe3-phy.h"
+
+/* PLLCTRL Registers */
+#define PLL_STATUS              0x00000004
+#define PLL_GO                  0x00000008
+#define PLL_CONFIGURATION1      0x0000000C
+#define PLL_CONFIGURATION2      0x00000010
+#define PLL_CONFIGURATION3      0x00000014
+#define PLL_CONFIGURATION4      0x00000020
+
+#define PLL_REGM_MASK           0x001FFE00
+#define PLL_REGM_SHIFT          9
+#define PLL_REGM_F_MASK         0x0003FFFF
+#define PLL_REGM_F_SHIFT        0
+#define PLL_REGN_MASK           0x000001FE
+#define PLL_REGN_SHIFT          1
+#define PLL_SELFREQDCO_MASK     0x0000000E
+#define PLL_SELFREQDCO_SHIFT    1
+#define PLL_SD_MASK             0x0003FC00
+#define PLL_SD_SHIFT            10
+#define SET_PLL_GO              0x1
+#define PLL_TICOPWDN            BIT(16)
+#define PLL_LDOPWDN             BIT(15)
+#define PLL_LOCK                0x2
+#define PLL_IDLE                0x1
+
+/* PHY POWER CONTROL Register */
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK         0x003FC000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT        0xE
+
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK        0xFFC00000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT       0x16
+
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON       0x3
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF      0x0
+
+
+#define PLL_IDLE_TIME   100     /* in milliseconds */
+#define PLL_LOCK_TIME   100     /* in milliseconds */
+
+static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
+{
+	return __raw_readl(addr + offset);
+}
+
+static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
+		u32 data)
+{
+	__raw_writel(data, addr + offset);
+}
+
+static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
+									*pipe3)
+{
+	u32 rate;
+	struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
+
+	rate = get_sys_clk_freq();
+
+	for (; dpll_map->rate; dpll_map++) {
+		if (rate == dpll_map->rate)
+			return &dpll_map->params;
+	}
+
+	printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
+	       __func__, rate);
+	return NULL;
+}
+
+
+static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
+{
+	u32 val;
+	int timeout = PLL_LOCK_TIME;
+
+	do {
+		mdelay(1);
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+		if (val & PLL_LOCK)
+			break;
+	} while (--timeout);
+
+	if (!(val & PLL_LOCK)) {
+		printf("%s: DPLL failed to lock\n", __func__);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
+{
+	u32                     val;
+	struct pipe3_dpll_params *dpll_params;
+
+	dpll_params = omap_pipe3_get_dpll_params(phy);
+	if (!dpll_params) {
+		printf("%s: Invalid DPLL parameters\n", __func__);
+		return -EINVAL;
+	}
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+	val &= ~PLL_REGN_MASK;
+	val |= dpll_params->n << PLL_REGN_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+	val &= ~PLL_SELFREQDCO_MASK;
+	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+	val &= ~PLL_REGM_MASK;
+	val |= dpll_params->m << PLL_REGM_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
+	val &= ~PLL_REGM_F_MASK;
+	val |= dpll_params->mf << PLL_REGM_F_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
+	val &= ~PLL_SD_MASK;
+	val |= dpll_params->sd << PLL_SD_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
+
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
+
+	return omap_pipe3_wait_lock(phy);
+}
+
+static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
+{
+	u32 val, rate;
+
+	val = readl(phy->power_reg);
+
+	rate = get_sys_clk_freq();
+	rate = rate/1000000;
+
+	if (on) {
+		val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
+		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+		val |= rate <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+	} else {
+		val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
+		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+	}
+
+	writel(val, phy->power_reg);
+}
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy)
+{
+	int ret;
+	u32 val;
+
+	/* Program the DPLL only if not locked */
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+	if (!(val & PLL_LOCK)) {
+		ret = omap_pipe3_dpll_program(phy);
+		if (ret)
+			return ret;
+	} else {
+		/* else just bring it out of IDLE mode */
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+		if (val & PLL_IDLE) {
+			val &= ~PLL_IDLE;
+			omap_pipe3_writel(phy->pll_ctrl_base,
+					  PLL_CONFIGURATION2, val);
+			ret = omap_pipe3_wait_lock(phy);
+			if (ret)
+				return ret;
+		}
+	}
+
+	/* Power up the PHY */
+	omap_control_phy_power(phy, 1);
+
+	return 0;
+}
+
+int phy_pipe3_power_off(struct omap_pipe3 *phy)
+{
+	u32 val;
+	int timeout = PLL_IDLE_TIME;
+
+	/* Power down the PHY */
+	omap_control_phy_power(phy, 0);
+
+	/* Put DPLL in IDLE mode */
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+	val |= PLL_IDLE;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+	/* wait for LDO and Oscillator to power down */
+	do {
+		mdelay(1);
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
+			break;
+	} while (--timeout);
+
+	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
+		printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
+		       __func__, val);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h
new file mode 100644
index 0000000..441f49a
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h
@@ -0,0 +1,36 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __OMAP_PIPE3_PHY_H
+#define __OMAP_PIPE3_PHY_H
+
+struct pipe3_dpll_params {
+	u16     m;
+	u8      n;
+	u8      freq:3;
+	u8      sd;
+	u32     mf;
+};
+
+struct pipe3_dpll_map {
+	unsigned long rate;
+	struct pipe3_dpll_params params;
+};
+
+struct omap_pipe3 {
+	void __iomem            *pll_ctrl_base;
+	void __iomem		*power_reg;
+	struct pipe3_dpll_map   *dpll_map;
+};
+
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy);
+int phy_pipe3_power_off(struct omap_pipe3 *pipe3);
+
+#endif /* __OMAP_PIPE3_PHY_H */
-- 
1.8.3.2

[U-Boot] [PATCH v3 4/8] ARM: OMAP5: Add PRCM and Control information for SATA

[Roger Quadros]

Adds the necessary PRCM and Control register information for
SATA on OMAP5.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/cpu/armv7/omap5/prcm-regs.c    | 4 ++++
 arch/arm/include/asm/arch-omap5/clock.h | 3 +++
 arch/arm/include/asm/arch-omap5/omap.h  | 3 +++
 arch/arm/include/asm/omap_common.h      | 2 ++
 4 files changed, 12 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 304ac1c..5c60d74 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = {
 	.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
 	.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
 	.cm_l3init_p1500_clkctrl = 0x4a009378,
+	.cm_l3init_sata_clkctrl = 0x4a009388,
 	.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
 	.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+	.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
 
 	/* cm2.l4per */
 	.cm_l4per_clkstctrl = 0x4a009400,
@@ -296,6 +298,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_status				= 0x4A002134,
 	.control_std_fuse_opp_vdd_mpu_2		= 0x4A0021B4,
 	.control_phy_power_usb 			= 0x4A002370,
+	.control_phy_power_sata			= 0x4A002374,
 	.control_padconf_core_base		= 0x4A002800,
 	.control_paconf_global			= 0x4A002DA0,
 	.control_paconf_mode			= 0x4A002DA4,
@@ -698,6 +701,7 @@ struct prcm_regs const omap5_es2_prcm = {
 	.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
 	.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
 	.cm_l3init_p1500_clkctrl = 0x4a009678,
+	.cm_l3init_sata_clkctrl = 0x4a009688,
 	.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
 	.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
 	.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 8869b50..2dfe4ef 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -137,6 +137,9 @@
 #define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(1 << 25)
 
+/* CM_L3INIT_SATA_CLKCTRL */
+#define SATA_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
 /* CM_WKUP_GPTIMER1_CLKCTRL */
 #define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
 
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 414d37a..150db0f 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -64,6 +64,9 @@
 /* QSPI */
 #define QSPI_BASE		0x4B300000
 
+/* SATA */
+#define DWC_AHSATA_BASE		0x4A140000
+
 /*
  * Hardware Register Details
  */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 8a395e8..382da90 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -226,6 +226,7 @@ struct prcm_regs {
 	u32 cm_l3init_hsusbotg_clkctrl;
 	u32 cm_l3init_hsusbtll_clkctrl;
 	u32 cm_l3init_p1500_clkctrl;
+	u32 cm_l3init_sata_clkctrl;
 	u32 cm_l3init_fsusb_clkctrl;
 	u32 cm_l3init_ocp2scp1_clkctrl;
 	u32 cm_l3init_ocp2scp3_clkctrl;
@@ -366,6 +367,7 @@ struct omap_sys_ctrl_regs {
 	u32 control_ldosram_mpu_voltage_ctrl;
 	u32 control_ldosram_core_voltage_ctrl;
 	u32 control_usbotghs_ctrl;
+	u32 control_phy_power_sata;
 	u32 control_padconf_core_base;
 	u32 control_paconf_global;
 	u32 control_paconf_mode;
-- 
1.8.3.2

[U-Boot] [PATCH v3 5/8] ARM: OMAP5: Add SATA platform glue

[Roger Quadros]

Add platform glue logic for the SATA controller.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/cpu/armv7/omap-common/Makefile |  1 +
 arch/arm/cpu/armv7/omap-common/sata.c   | 75 +++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap5/sata.h  | 48 +++++++++++++++++++++
 3 files changed, 124 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c
 create mode 100644 arch/arm/include/asm/arch-omap5/sata.h

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index bfaf814..679c1a1 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -19,6 +19,7 @@ endif
 
 ifneq ($(CONFIG_OMAP54XX),)
 COBJS	+= pipe3-phy.o
+obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
 endif
 
 ifeq ($(CONFIG_OMAP34XX),)
diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c
new file mode 100644
index 0000000..f5468c4
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/sata.c
@@ -0,0 +1,75 @@
+/*
+ * TI SATA platform driver
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sata.h>
+#include <asm/io.h>
+#include "pipe3-phy.h"
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+	{12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
+	{16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
+	{19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
+	{20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
+	{26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
+	{38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
+	{ },                                    /* Terminator */
+};
+
+struct omap_pipe3 sata_phy = {
+	.pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
+	/* .power_reg is updated at runtime */
+	.dpll_map = dpll_map_sata,
+};
+
+int omap_sata_init(void)
+{
+	int ret;
+	u32 val;
+
+	u32 const clk_domains_sata[] = {
+		0
+	};
+
+	u32 const clk_modules_hw_auto_sata[] = {
+		(*prcm)->cm_l3init_ocp2scp3_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_sata[] = {
+		(*prcm)->cm_l3init_sata_clkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains_sata,
+			 clk_modules_hw_auto_sata,
+			 clk_modules_explicit_en_sata,
+			 0);
+
+	/* Enable optional functional clock for SATA */
+	setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
+		     SATA_CLKCTRL_OPTFCLKEN_MASK);
+
+	sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
+
+	/* Power up the PHY */
+	phy_pipe3_power_on(&sata_phy);
+
+	/* Enable SATA module, No Idle, No Standby */
+	val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
+	writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
+
+	ret = ahci_init(DWC_AHSATA_BASE);
+	scsi_scan(1);
+
+	return ret;
+}
diff --git a/arch/arm/include/asm/arch-omap5/sata.h b/arch/arm/include/asm/arch-omap5/sata.h
new file mode 100644
index 0000000..2ca8947
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/sata.h
@@ -0,0 +1,48 @@
+/*
+ * SATA Wrapper Register map
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TI_SATA_H
+#define _TI_SATA_H
+
+/* SATA Wrapper module */
+#define TI_SATA_WRAPPER_BASE		(OMAP54XX_L4_CORE_BASE + 0x141100)
+/* SATA PHY Module */
+#define TI_SATA_PLLCTRL_BASE		(OMAP54XX_L4_CORE_BASE + 0x96800)
+
+/* SATA Wrapper register offsets */
+#define TI_SATA_SYSCONFIG			0x00
+#define TI_SATA_CDRLOCK				0x04
+
+/* Register Set */
+#define TI_SATA_SYSCONFIG_OVERRIDE0		(1 << 16)
+#define TI_SATA_SYSCONFIG_STANDBY_MASK		(0x3 << 4)
+#define TI_SATA_SYSCONFIG_IDLE_MASK		(0x3 << 2)
+
+/* Standby modes */
+#define TI_SATA_STANDBY_FORCE			0x0
+#define TI_SATA_STANDBY_NO			(0x1 << 4)
+#define TI_SATA_STANDBY_SMART_WAKE		(0x3 << 4)
+#define TI_SATA_STANDBY_SMART			(0x2 << 4)
+
+/* Idle modes */
+#define TI_SATA_IDLE_FORCE			0x0
+#define TI_SATA_IDLE_NO				(0x1 << 2)
+#define TI_SATA_IDLE_SMART_WAKE			(0x3 << 2)
+#define TI_SATA_IDLE_SMART			(0x2 << 2)
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int omap_sata_init(void);
+#else
+static inline int omap_sata_init(void)
+{
+	return 0;
+}
+#endif /* CONFIG_SCSI_AHCI_PLAT */
+
+#endif /* _TI_SATA_H */
-- 
1.8.3.2

[U-Boot] [PATCH v3 6/8] ARM: omap5_uevm: Add SATA support

[Roger Quadros]

The uevm has a SATA port. Inititialize the SATA controller.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 board/ti/omap5_uevm/evm.c    |  7 +++++++
 include/configs/omap5_uevm.h | 10 ++++++++++
 2 files changed, 17 insertions(+)

diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index bb3a699..af854da 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -20,6 +20,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/ehci.h>
 #include <asm/ehci-omap.h>
+#include <asm/arch/sata.h>
 
 #define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
 #define DIE_ID_REG_OFFSET	0x200
@@ -67,6 +68,12 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	omap_sata_init();
+	return 0;
+}
+
 int board_eth_init(bd_t *bis)
 {
 	return 0;
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 4d3a800..2f128b8 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -69,4 +69,14 @@
 /* Max time to hold reset on this board, see doc/README.omap-reset-time */
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
 #endif /* __CONFIG_OMAP5_EVM_H */
-- 
1.8.3.2

[U-Boot] [PATCH v3 7/8] ARM: DRA7xx: Add PRCM and Control information for SATA

[Roger Quadros]

Adds the necessary PRCM and Control register information for
SATA on DRA7xx.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/cpu/armv7/omap5/prcm-regs.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 5c60d74..77c428b 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -376,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 
 struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_status				= 0x4A002134,
+	.control_phy_power_sata			= 0x4A002374,
 	.control_core_mac_id_0_lo		= 0x4A002514,
 	.control_core_mac_id_0_hi		= 0x4A002518,
 	.control_core_mac_id_1_lo		= 0x4A00251C,
@@ -895,9 +896,11 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_l3init_hsusbhost_clkctrl		= 0x4a009340,
 	.cm_l3init_hsusbotg_clkctrl		= 0x4a009348,
 	.cm_l3init_hsusbtll_clkctrl		= 0x4a009350,
+	.cm_l3init_sata_clkctrl			= 0x4a009388,
 	.cm_gmac_clkstctrl			= 0x4a0093c0,
 	.cm_gmac_gmac_clkctrl			= 0x4a0093d0,
 	.cm_l3init_ocp2scp1_clkctrl		= 0x4a0093e0,
+	.cm_l3init_ocp2scp3_clkctrl		= 0x4a0093e8,
 
 	/* cm2.l4per */
 	.cm_l4per_clkstctrl			= 0x4a009700,
-- 
1.8.3.2

[U-Boot] [PATCH v3 8/8] ARM: dra7_evm: Add SATA support

[Roger Quadros]

The evm has a SATA port. Enable SATA configuration and
inititialize the SATA controller.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 board/ti/dra7xx/evm.c        |  7 +++++++
 include/configs/dra7xx_evm.h | 11 +++++++++++
 2 files changed, 18 insertions(+)

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 9657c75..9ae88c5 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -14,6 +14,7 @@
 #include <palmas.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sata.h>
 
 #include "mux_data.h"
 
@@ -77,6 +78,12 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	omap_sata_init();
+	return 0;
+}
+
 /**
  * @brief misc_init_r - Configure EVM board specific configurations
  * such as power configurations, ethernet initialization as phase2 of
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index a9f39f2..6fadffb 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -78,4 +78,15 @@
 #define CONFIG_OMAP_USB_PHY
 #define CONFIG_OMAP_USB2PHY2_HOST
 
+/* SATA */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
-- 
1.8.3.2

[U-Boot] [PATCH v3 0/8] SATA support for omap5_uevm and dra7_evm

[Enric Balletbo Serra]

Hi Roger,

2013/11/11 Roger Quadros <rogerq@ti.com>:
> Hi,
>
> This series adds SATA support for OMAP5 uevm and DRA7 evm.
>
> Patches are also availabe at
>  git at github.com:rogerq/u-boot.git       sata
>
> v3:
> - get rid of custom perror() macro, use printf
> - Fixed coding sytle issues
>
> v2:
> - Address review comments in the RFC series
> - Fix cache align error in the ahci driver
> - Added dra7 support
>
> cheers,
> -roger
>
> Roger Quadros (8):
>   ahci: Error out with message on malloc() failure
>   ahci: Fix cache align error messages
>   ARM: OMAP5: Add Pipe3 PHY driver
>   ARM: OMAP5: Add PRCM and Control information for SATA
>   ARM: OMAP5: Add SATA platform glue
>   ARM: omap5_uevm: Add SATA support
>   ARM: DRA7xx: Add PRCM and Control information for SATA
>   ARM: dra7_evm: Add SATA support
>
>  arch/arm/cpu/armv7/omap-common/Makefile    |   5 +
>  arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 231 +++++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/omap-common/pipe3-phy.h |  36 +++++
>  arch/arm/cpu/armv7/omap-common/sata.c      |  75 ++++++++++
>  arch/arm/cpu/armv7/omap5/prcm-regs.c       |   7 +
>  arch/arm/include/asm/arch-omap5/clock.h    |   3 +
>  arch/arm/include/asm/arch-omap5/omap.h     |   3 +
>  arch/arm/include/asm/arch-omap5/sata.h     |  48 ++++++
>  arch/arm/include/asm/omap_common.h         |   2 +
>  board/ti/dra7xx/evm.c                      |   7 +
>  board/ti/omap5_uevm/evm.c                  |   7 +
>  drivers/block/ahci.c                       |  18 ++-
>  include/configs/dra7xx_evm.h               |  11 ++
>  include/configs/omap5_uevm.h               |  10 ++
>  14 files changed, 457 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c
>  create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h
>  create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c
>  create mode 100644 arch/arm/include/asm/arch-omap5/sata.h
>
> --
> 1.8.3.2
>

I've tested the patches in my board and worked for me.

Note, but, although the patches apply cleanly in current master branch
the build is broken due this commit:

commit 4e1aa8437ae5baed2be79fff09aa70a293e61467
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
Date:   Thu Oct 17 17:34:48 2013 +0900

    armv7: convert makefiles to Kbuild style


You should apply the following change in your patch number 3
(U-Boot-v3-3-8-ARM-OMAP5-Add-Pipe3-PHY-driver.patch)

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile
b/arch/arm/cpu/armv7/omap-common/Makefile
index 679c1a1..59f5352 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -18,7 +18,7 @@ obj-y += abb.o
 endif

 ifneq ($(CONFIG_OMAP54XX),)
-COBJS  += pipe3-phy.o
+obj-y  += pipe3-phy.o
 obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
 endif

And rebase the patch number 5
(U-Boot-v3-5-8-ARM-OMAP5-Add-SATA-platform-glue.patch) as after the
change doesn't apply.

Despite this:

Tested-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>

Cheers,
   Enric

[U-Boot] [PATCH v3 0/8] SATA support for omap5_uevm and dra7_evm

[Tom Rini]

On Mon, Nov 11, 2013 at 04:56:36PM +0200, Roger Quadros wrote:

> Hi,
> 
> This series adds SATA support for OMAP5 uevm and DRA7 evm.
> 
> Patches are also availabe at
>  git at github.com:rogerq/u-boot.git	sata
> 
> v3:
> - get rid of custom perror() macro, use printf
> - Fixed coding sytle issues
> 
> v2:
> - Address review comments in the RFC series
> - Fix cache align error in the ahci driver
> - Added dra7 support
> 
> cheers,
> -roger
> 
> Roger Quadros (8):
>   ahci: Error out with message on malloc() failure
>   ahci: Fix cache align error messages
>   ARM: OMAP5: Add Pipe3 PHY driver
>   ARM: OMAP5: Add PRCM and Control information for SATA
>   ARM: OMAP5: Add SATA platform glue
>   ARM: omap5_uevm: Add SATA support
>   ARM: DRA7xx: Add PRCM and Control information for SATA
>   ARM: dra7_evm: Add SATA support

Applied to u-boot-ti/master, thanks!

-- 
Tom
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[U-Boot] [PATCH v3 0/8] SATA support for omap5_uevm and dra7_evm

[Enric Balletbo Serra]

Hi Roger,

2013/12/4 Tom Rini <trini@ti.com>:
> On Mon, Nov 11, 2013 at 04:56:36PM +0200, Roger Quadros wrote:
>
>> Hi,
>>
>> This series adds SATA support for OMAP5 uevm and DRA7 evm.
>>
>> Patches are also availabe at
>>  git at github.com:rogerq/u-boot.git     sata
>>
>> v3:
>> - get rid of custom perror() macro, use printf
>> - Fixed coding sytle issues
>>
>> v2:
>> - Address review comments in the RFC series
>> - Fix cache align error in the ahci driver
>> - Added dra7 support
>>
>> cheers,
>> -roger
>>
>> Roger Quadros (8):
>>   ahci: Error out with message on malloc() failure
>>   ahci: Fix cache align error messages
>>   ARM: OMAP5: Add Pipe3 PHY driver
>>   ARM: OMAP5: Add PRCM and Control information for SATA
>>   ARM: OMAP5: Add SATA platform glue
>>   ARM: omap5_uevm: Add SATA support
>>   ARM: DRA7xx: Add PRCM and Control information for SATA
>>   ARM: dra7_evm: Add SATA support
>
> Applied to u-boot-ti/master, thanks!
>

Now that this will go to mainline, I wonder to know if there is any
plan to add SPL support to boot from SATA ?

Thanks,
   Enric


> --
> Tom
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

[U-Boot] [PATCH v3 0/8] SATA support for omap5_uevm and dra7_evm

[Tom Rini]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 12/18/2013 06:31 AM, Enric Balletbo Serra wrote:
> Hi Roger,
> 
> 2013/12/4 Tom Rini <trini@ti.com>:
>> On Mon, Nov 11, 2013 at 04:56:36PM +0200, Roger Quadros wrote:
>>
>>> Hi,
>>>
>>> This series adds SATA support for OMAP5 uevm and DRA7 evm.
>>>
>>> Patches are also availabe at
>>>  git at github.com:rogerq/u-boot.git     sata
>>>
>>> v3:
>>> - get rid of custom perror() macro, use printf
>>> - Fixed coding sytle issues
>>>
>>> v2:
>>> - Address review comments in the RFC series
>>> - Fix cache align error in the ahci driver
>>> - Added dra7 support
>>>
>>> cheers,
>>> -roger
>>>
>>> Roger Quadros (8):
>>>   ahci: Error out with message on malloc() failure
>>>   ahci: Fix cache align error messages
>>>   ARM: OMAP5: Add Pipe3 PHY driver
>>>   ARM: OMAP5: Add PRCM and Control information for SATA
>>>   ARM: OMAP5: Add SATA platform glue
>>>   ARM: omap5_uevm: Add SATA support
>>>   ARM: DRA7xx: Add PRCM and Control information for SATA
>>>   ARM: dra7_evm: Add SATA support
>>
>> Applied to u-boot-ti/master, thanks!
>>
> 
> Now that this will go to mainline, I wonder to know if there is any
> plan to add SPL support to boot from SATA ?

I've talked ever so briefly with Dan Murphy about this because his
series that adds USB host support gets us ever further towards SATA SPL
support as both talk in block_dev_desc_t.  I don't think anyone is
working on this today, but my gut says it shouldn't be too hard to add
on top.

- -- 
Tom
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