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* [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
  2013-11-12 12:27 [U-Boot] [PATCH V2 0/7] SMDK5420: Add support for FIMD and DP Ajay Kumar
@ 2013-11-12 12:27 ` Ajay Kumar
  2013-12-19 20:38   ` Simon Glass
  0 siblings, 1 reply; 4+ messages in thread
From: Ajay Kumar @ 2013-11-12 12:27 UTC (permalink / raw)
  To: u-boot

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
---
 arch/arm/cpu/armv7/exynos/clock.c         | 74 +++++++++++++++++++++++++++++--
 arch/arm/cpu/armv7/exynos/exynos5_setup.h |  2 +-
 arch/arm/include/asm/arch-exynos/clk.h    |  1 +
 3 files changed, 73 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index b52e61a..60ca7ea 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 	 * VPLL_CON: MIDV [24:16]
 	 * BPLL_CON: MIDV [25:16]: Exynos5
 	 */
-	if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+	if (pllreg == APLL || pllreg == MPLL ||
+					pllreg == BPLL || pllreg == SPLL)
 		mask = 0x3ff;
 	else
 		mask = 0x1ff;
@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
 		r = readl(&clk->rpll_con0);
 		k = readl(&clk->rpll_con1);
 		break;
+	case SPLL:
+		r = readl(&clk->spll_con0);
+		break;
 	default:
 		printf("Unsupported PLL (%d)\n", pllreg);
 		return 0;
@@ -1038,6 +1042,40 @@ static unsigned long exynos5_get_lcd_clk(void)
 	return pclk;
 }
 
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_DISP10
+	 * FIMD1_SEL [4]
+	 * 0: SCLK_RPLL
+	 * 1: SCLK_SPLL
+	 */
+	sel = readl(&clk->src_disp10);
+	sel &= (1 << 4);
+
+	if (sel)
+		sclk = get_pll_clk(SPLL);
+	else
+		sclk = get_pll_clk(RPLL);
+
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_disp10);
+	ratio = ratio & 0xf;
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
 void exynos4_set_lcd_clk(void)
 {
 	struct exynos4_clock *clk =
@@ -1162,6 +1200,33 @@ void exynos5_set_lcd_clk(void)
 	writel(cfg, &clk->div_disp1_0);
 }
 
+void exynos5420_set_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned int cfg;
+
+	/*
+	 * CLK_SRC_DISP10
+	 * FIMD1_SEL [4]
+	 * 0: SCLK_RPLL
+	 * 1: SCLK_SPLL
+	 */
+	cfg = readl(&clk->src_disp10);
+	cfg &= ~(0x1 << 4);
+	cfg |= (0 << 4);
+	writel(cfg, &clk->src_disp10);
+
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO		[3:0]
+	 */
+	cfg = readl(&clk->div_disp10);
+	cfg &= ~(0xf << 0);
+	cfg |= (0 << 0);
+	writel(cfg, &clk->div_disp10);
+}
+
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =
@@ -1657,14 +1722,17 @@ unsigned long get_lcd_clk(void)
 {
 	if (cpu_is_exynos4())
 		return exynos4_get_lcd_clk();
-	else
-		return exynos5_get_lcd_clk();
+	else if (proid_is_exynos5420())
+		return exynos5420_get_lcd_clk();
+	return exynos5_get_lcd_clk();
 }
 
 void set_lcd_clk(void)
 {
 	if (cpu_is_exynos4())
 		exynos4_set_lcd_clk();
+	else if (proid_is_exynos5420())
+		exynos5420_set_lcd_clk();
 	else
 		exynos5_set_lcd_clk();
 }
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 8e05a00..70b1c04 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -780,7 +780,7 @@
 #define CLK_SRC_TOP2_VAL	0x11101000
 #define CLK_SRC_TOP3_VAL	0x11111111
 #define CLK_SRC_TOP4_VAL	0x11110111
-#define CLK_SRC_TOP5_VAL	0x11111100
+#define CLK_SRC_TOP5_VAL	0x11111101
 #define CLK_SRC_TOP6_VAL	0x11110111
 #define CLK_SRC_TOP7_VAL	0x00022200
 
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index cdeef32..98faae7 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -15,6 +15,7 @@
 #define VPLL	4
 #define BPLL	5
 #define RPLL	6
+#define SPLL	7
 
 enum pll_src_bit {
 	EXYNOS_SRC_MPLL = 6,
-- 
1.7.12.4

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
  2013-11-12 12:27 ` [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 Ajay Kumar
@ 2013-12-19 20:38   ` Simon Glass
  0 siblings, 0 replies; 4+ messages in thread
From: Simon Glass @ 2013-12-19 20:38 UTC (permalink / raw)
  To: u-boot

On 12 November 2013 05:27, Ajay Kumar <ajaykumar.rs@samsung.com> wrote:
> Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
> exynos video driver.
> Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
>
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>

Acked-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
       [not found] <52C28453.8080705@samsung.com>
@ 2014-01-02  0:39 ` Minkyu Kang
  2014-01-02  5:39   ` Ajay kumar
  0 siblings, 1 reply; 4+ messages in thread
From: Minkyu Kang @ 2014-01-02  0:39 UTC (permalink / raw)
  To: u-boot

On 12/11/13 21:27, Ajay Kumar wrote:
> Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by

I think, they are not callback functions.

> exynos video driver.
> Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
> 
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> ---
>  arch/arm/cpu/armv7/exynos/clock.c         | 74 +++++++++++++++++++++++++++++--
>  arch/arm/cpu/armv7/exynos/exynos5_setup.h |  2 +-
>  arch/arm/include/asm/arch-exynos/clk.h    |  1 +
>  3 files changed, 73 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index b52e61a..60ca7ea 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
>  	 * VPLL_CON: MIDV [24:16]
>  	 * BPLL_CON: MIDV [25:16]: Exynos5
>  	 */
> -	if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
> +	if (pllreg == APLL || pllreg == MPLL ||
> +					pllreg == BPLL || pllreg == SPLL)
>  		mask = 0x3ff;
>  	else
>  		mask = 0x1ff;
> @@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
>  		r = readl(&clk->rpll_con0);
>  		k = readl(&clk->rpll_con1);
>  		break;
> +	case SPLL:
> +		r = readl(&clk->spll_con0);
> +		break;
>  	default:
>  		printf("Unsupported PLL (%d)\n", pllreg);
>  		return 0;
> @@ -1038,6 +1042,40 @@ static unsigned long exynos5_get_lcd_clk(void)
>  	return pclk;
>  }
>  
> +static unsigned long exynos5420_get_lcd_clk(void)
> +{
> +	struct exynos5420_clock *clk =
> +		(struct exynos5420_clock *)samsung_get_base_clock();
> +	unsigned long pclk, sclk;
> +	unsigned int sel;
> +	unsigned int ratio;
> +
> +	/*
> +	 * CLK_SRC_DISP10
> +	 * FIMD1_SEL [4]
> +	 * 0: SCLK_RPLL
> +	 * 1: SCLK_SPLL
> +	 */
> +	sel = readl(&clk->src_disp10);
> +	sel &= (1 << 4);
> +
> +	if (sel)
> +		sclk = get_pll_clk(SPLL);
> +	else
> +		sclk = get_pll_clk(RPLL);
> +
> +	/*
> +	 * CLK_DIV_DISP10
> +	 * FIMD1_RATIO [3:0]
> +	 */
> +	ratio = readl(&clk->div_disp10);
> +	ratio = ratio & 0xf;
> +
> +	pclk = sclk / (ratio + 1);
> +
> +	return pclk;
> +}
> +
>  void exynos4_set_lcd_clk(void)
>  {
>  	struct exynos4_clock *clk =
> @@ -1162,6 +1200,33 @@ void exynos5_set_lcd_clk(void)
>  	writel(cfg, &clk->div_disp1_0);
>  }
>  
> +void exynos5420_set_lcd_clk(void)
> +{
> +	struct exynos5420_clock *clk =
> +		(struct exynos5420_clock *)samsung_get_base_clock();
> +	unsigned int cfg;
> +
> +	/*
> +	 * CLK_SRC_DISP10
> +	 * FIMD1_SEL [4]
> +	 * 0: SCLK_RPLL
> +	 * 1: SCLK_SPLL
> +	 */
> +	cfg = readl(&clk->src_disp10);
> +	cfg &= ~(0x1 << 4);
> +	cfg |= (0 << 4);
> +	writel(cfg, &clk->src_disp10);
> +
> +	/*
> +	 * CLK_DIV_DISP10
> +	 * FIMD1_RATIO		[3:0]
> +	 */
> +	cfg = readl(&clk->div_disp10);
> +	cfg &= ~(0xf << 0);
> +	cfg |= (0 << 0);
> +	writel(cfg, &clk->div_disp10);
> +}
> +
>  void exynos4_set_mipi_clk(void)
>  {
>  	struct exynos4_clock *clk =
> @@ -1657,14 +1722,17 @@ unsigned long get_lcd_clk(void)
>  {
>  	if (cpu_is_exynos4())
>  		return exynos4_get_lcd_clk();
> -	else
> -		return exynos5_get_lcd_clk();
> +	else if (proid_is_exynos5420())

please don't mix cpu_is... and proid_is..
please refer other functions.

> +		return exynos5420_get_lcd_clk();
> +	return exynos5_get_lcd_clk();
>  }
>  
>  void set_lcd_clk(void)
>  {
>  	if (cpu_is_exynos4())
>  		exynos4_set_lcd_clk();
> +	else if (proid_is_exynos5420())
> +		exynos5420_set_lcd_clk();

ditto.

>  	else
>  		exynos5_set_lcd_clk();
>  }
> diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> index 8e05a00..70b1c04 100644
> --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> @@ -780,7 +780,7 @@
>  #define CLK_SRC_TOP2_VAL	0x11101000
>  #define CLK_SRC_TOP3_VAL	0x11111111
>  #define CLK_SRC_TOP4_VAL	0x11110111
> -#define CLK_SRC_TOP5_VAL	0x11111100
> +#define CLK_SRC_TOP5_VAL	0x11111101
>  #define CLK_SRC_TOP6_VAL	0x11110111
>  #define CLK_SRC_TOP7_VAL	0x00022200
>  
> diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
> index cdeef32..98faae7 100644
> --- a/arch/arm/include/asm/arch-exynos/clk.h
> +++ b/arch/arm/include/asm/arch-exynos/clk.h
> @@ -15,6 +15,7 @@
>  #define VPLL	4
>  #define BPLL	5
>  #define RPLL	6
> +#define SPLL	7
>  
>  enum pll_src_bit {
>  	EXYNOS_SRC_MPLL = 6,
> 

Thanks,
Minkyu Kang.

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
  2014-01-02  0:39 ` [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 Minkyu Kang
@ 2014-01-02  5:39   ` Ajay kumar
  0 siblings, 0 replies; 4+ messages in thread
From: Ajay kumar @ 2014-01-02  5:39 UTC (permalink / raw)
  To: u-boot

Hi Minkyu,


On Thu, Jan 2, 2014 at 6:09 AM, Minkyu Kang <mk7.kang@samsung.com> wrote:

> On 12/11/13 21:27, Ajay Kumar wrote:
> > Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
>
> I think, they are not callback functions.

Ok. I will change the comment.

> > exynos video driver.
> > Also, configure ACLK_400_DISP1 as the parent for
> MUX_ACLK_400_DISP1_SUB_SEL.
> >
> > Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> > ---
> >  arch/arm/cpu/armv7/exynos/clock.c         | 74
> +++++++++++++++++++++++++++++--
> >  arch/arm/cpu/armv7/exynos/exynos5_setup.h |  2 +-
> >  arch/arm/include/asm/arch-exynos/clk.h    |  1 +
> >  3 files changed, 73 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> > index b52e61a..60ca7ea 100644
> > --- a/arch/arm/cpu/armv7/exynos/clock.c
> > +++ b/arch/arm/cpu/armv7/exynos/clock.c
> > @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int
> r, unsigned int k)
> >        * VPLL_CON: MIDV [24:16]
> >        * BPLL_CON: MIDV [25:16]: Exynos5
> >        */
> > -     if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
> > +     if (pllreg == APLL || pllreg == MPLL ||
> > +                                     pllreg == BPLL || pllreg == SPLL)
> >               mask = 0x3ff;
> >       else
> >               mask = 0x1ff;
> > @@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int
> pllreg)
> >               r = readl(&clk->rpll_con0);
> >               k = readl(&clk->rpll_con1);
> >               break;
> > +     case SPLL:
> > +             r = readl(&clk->spll_con0);
> > +             break;
> >       default:
> >               printf("Unsupported PLL (%d)\n", pllreg);
> >               return 0;
> > @@ -1038,6 +1042,40 @@ static unsigned long exynos5_get_lcd_clk(void)
> >       return pclk;
> >  }
> >
> > +static unsigned long exynos5420_get_lcd_clk(void)
> > +{
> > +     struct exynos5420_clock *clk =
> > +             (struct exynos5420_clock *)samsung_get_base_clock();
> > +     unsigned long pclk, sclk;
> > +     unsigned int sel;
> > +     unsigned int ratio;
> > +
> > +     /*
> > +      * CLK_SRC_DISP10
> > +      * FIMD1_SEL [4]
> > +      * 0: SCLK_RPLL
> > +      * 1: SCLK_SPLL
> > +      */
> > +     sel = readl(&clk->src_disp10);
> > +     sel &= (1 << 4);
> > +
> > +     if (sel)
> > +             sclk = get_pll_clk(SPLL);
> > +     else
> > +             sclk = get_pll_clk(RPLL);
> > +
> > +     /*
> > +      * CLK_DIV_DISP10
> > +      * FIMD1_RATIO [3:0]
> > +      */
> > +     ratio = readl(&clk->div_disp10);
> > +     ratio = ratio & 0xf;
> > +
> > +     pclk = sclk / (ratio + 1);
> > +
> > +     return pclk;
> > +}
> > +
> >  void exynos4_set_lcd_clk(void)
> >  {
> >       struct exynos4_clock *clk =
> > @@ -1162,6 +1200,33 @@ void exynos5_set_lcd_clk(void)
> >       writel(cfg, &clk->div_disp1_0);
> >  }
> >
> > +void exynos5420_set_lcd_clk(void)
> > +{
> > +     struct exynos5420_clock *clk =
> > +             (struct exynos5420_clock *)samsung_get_base_clock();
> > +     unsigned int cfg;
> > +
> > +     /*
> > +      * CLK_SRC_DISP10
> > +      * FIMD1_SEL [4]
> > +      * 0: SCLK_RPLL
> > +      * 1: SCLK_SPLL
> > +      */
> > +     cfg = readl(&clk->src_disp10);
> > +     cfg &= ~(0x1 << 4);
> > +     cfg |= (0 << 4);
> > +     writel(cfg, &clk->src_disp10);
> > +
> > +     /*
> > +      * CLK_DIV_DISP10
> > +      * FIMD1_RATIO          [3:0]
> > +      */
> > +     cfg = readl(&clk->div_disp10);
> > +     cfg &= ~(0xf << 0);
> > +     cfg |= (0 << 0);
> > +     writel(cfg, &clk->div_disp10);
> > +}
> > +
> >  void exynos4_set_mipi_clk(void)
> >  {
> >       struct exynos4_clock *clk =
> > @@ -1657,14 +1722,17 @@ unsigned long get_lcd_clk(void)
> >  {
> >       if (cpu_is_exynos4())
> >               return exynos4_get_lcd_clk();
> > -     else
> > -             return exynos5_get_lcd_clk();
> > +     else if (proid_is_exynos5420())
>
> please don't mix cpu_is... and proid_is..
> please refer other functions.
>
> Ok. I will change it.

> > +             return exynos5420_get_lcd_clk();
> > +     return exynos5_get_lcd_clk();
> >  }
> >
> >  void set_lcd_clk(void)
> >  {
> >       if (cpu_is_exynos4())
> >               exynos4_set_lcd_clk();
> > +     else if (proid_is_exynos5420())
> > +             exynos5420_set_lcd_clk();
>
> ditto.
>
> Ok.

> >       else
> >               exynos5_set_lcd_clk();
> >  }
> > diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> > index 8e05a00..70b1c04 100644
> > --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> > +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> > @@ -780,7 +780,7 @@
> >  #define CLK_SRC_TOP2_VAL     0x11101000
> >  #define CLK_SRC_TOP3_VAL     0x11111111
> >  #define CLK_SRC_TOP4_VAL     0x11110111
> > -#define CLK_SRC_TOP5_VAL     0x11111100
> > +#define CLK_SRC_TOP5_VAL     0x11111101
> >  #define CLK_SRC_TOP6_VAL     0x11110111
> >  #define CLK_SRC_TOP7_VAL     0x00022200
> >
> > diff --git a/arch/arm/include/asm/arch-exynos/clk.h
> b/arch/arm/include/asm/arch-exynos/clk.h
> > index cdeef32..98faae7 100644
> > --- a/arch/arm/include/asm/arch-exynos/clk.h
> > +++ b/arch/arm/include/asm/arch-exynos/clk.h
> > @@ -15,6 +15,7 @@
> >  #define VPLL 4
> >  #define BPLL 5
> >  #define RPLL 6
> > +#define SPLL 7
> >
> >  enum pll_src_bit {
> >       EXYNOS_SRC_MPLL = 6,
> >
>
> Thanks,
> Minkyu Kang.
>
>
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot


Thanks and regards,
Ajay Kumar

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2014-01-02  5:39 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
     [not found] <52C28453.8080705@samsung.com>
2014-01-02  0:39 ` [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 Minkyu Kang
2014-01-02  5:39   ` Ajay kumar
2013-11-12 12:27 [U-Boot] [PATCH V2 0/7] SMDK5420: Add support for FIMD and DP Ajay Kumar
2013-11-12 12:27 ` [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 Ajay Kumar
2013-12-19 20:38   ` Simon Glass

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