From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Thu, 2 Jan 2014 15:43:59 -0800
Subject: [U-Boot] [PATCH] board/t1040qds: Relax IFC FPGA timings
In-Reply-To: <1386830341-25526-1-git-send-email-prabhakar@freescale.com>
References: <1386830341-25526-1-git-send-email-prabhakar@freescale.com>
Message-ID: <52C5F9BF.8050707@freescale.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On 12/11/2013 10:39 PM, Prabhakar Kushwaha wrote:
> Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion)
> is 0 i.e. 0 ns hold time on writes. This may not work on higher clock
> freqencies.
> 
> So, Increase TCH as 0x8 i.e. 8 ip_clk.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---

Applied to u-boot-mpc85xx/master. Thanks.

York