* [U-Boot] [PATCH v6 01/12] sf: Add extended read commands support
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
2014-01-04 15:04 ` [U-Boot] [PATCH v6 02/12] sf: Add quad read/write " Jagannadha Sutradharudu Teki
` (10 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
Current sf uses FAST_READ command, this patch adds support to
use the different/extended read command.
This implementation will determine the fastest command by taking
the supported commands from the flash and the controller, controller
is always been a priority.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/sf_internal.h | 2 +
drivers/mtd/spi/sf_ops.c | 2 +-
drivers/mtd/spi/sf_probe.c | 190 +++++++++++++++++++++++-------------------
include/spi.h | 8 ++
include/spi_flash.h | 10 +++
5 files changed, 126 insertions(+), 86 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index d291746..938a78e 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -36,6 +36,8 @@
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_ARRAY_FAST 0x0b
+#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
+#define CMD_READ_DUAL_IO_FAST 0xbb
#define CMD_READ_ID 0x9f
/* Bank addr access commands */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index e316a69..49ceef0 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -285,7 +285,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
return 0;
}
- cmd[0] = CMD_READ_ARRAY_FAST;
+ cmd[0] = flash->read_cmd;
cmd[4] = 0x00;
while (len) {
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index b863a98..c0baac6 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
* @ext_jedec: Device ext_jedec ID
* @sector_size: Sector size of this device
* @nr_sectors: No.of sectors on this device
+ * @e_rd_cmd: Enum list for read commands
* @flags: Importent param, for flash specific behaviour
*/
struct spi_flash_params {
@@ -35,110 +36,111 @@ struct spi_flash_params {
u16 ext_jedec;
u32 sector_size;
u32 nr_sectors;
+ u8 e_rd_cmd;
u16 flags;
};
static const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K},
- {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K},
- {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K},
- {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K},
- {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K},
- {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K},
- {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K},
- {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, SECT_4K},
+ {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
+ {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
+ {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */
- {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0},
- {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K},
- {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0},
- {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0},
+ {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
+ {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
+ {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K},
- {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K},
+ {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0},
- {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0},
- {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0},
- {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0},
- {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0},
- {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0},
- {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0},
- {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0},
- {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0},
- {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0},
+ {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
+ {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
+ {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
+ {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
+ {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
+ {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
+ {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0, 0},
+ {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0, 0},
+ {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0, 0},
+ {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0, 0},
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
- {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0},
- {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0},
- {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0},
- {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0},
- {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0},
- {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0},
- {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0},
- {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0},
- {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0},
- {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, 0},
- {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, 0},
- {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0},
- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0},
+ {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
+ {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
+ {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
+ {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
+ {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0, 0},
+ {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0, 0},
+ {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0, 0},
+ {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0, 0},
+ {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0, 0},
+ {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_EXTN, 0},
+ {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_EXTN, 0},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0, 0},
+ {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0, 0},
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
- {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0},
- {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0},
- {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0},
- {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0},
- {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0},
- {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0},
- {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0},
- {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0},
- {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, SECT_4K},
- {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, SECT_4K},
- {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, SECT_4K},
- {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, SECT_4K},
- {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, SECT_4K},
- {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, SECT_4K},
- {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, SECT_4K},
- {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, SECT_4K},
- {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K},
- {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K},
- {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K},
- {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K},
+ {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
+ {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
+ {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
+ {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
+ {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
+ {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
+ {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
+ {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
+ {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, 0, SECT_4K},
+ {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, 0, SECT_4K},
+ {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
+ {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
+ {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
+ {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_SST /* SST */
- {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WP},
- {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WP},
- {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WP},
- {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WP},
- {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K},
- {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WP},
- {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WP},
- {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WP},
- {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WP},
- {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WP},
+ {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
+ {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
+ {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
+ {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
+ {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
+ {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
+ {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
+ {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
+ {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
- {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0},
- {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0},
- {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0},
- {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K},
- {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K},
- {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K},
- {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K},
- {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, SECT_4K},
- {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, SECT_4K},
- {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, SECT_4K},
- {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, SECT_4K},
- {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, SECT_4K},
- {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, SECT_4K},
- {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, SECT_4K},
- {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, SECT_4K},
- {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, SECT_4K},
- {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, SECT_4K},
- {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, SECT_4K},
+ {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
+ {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
+ {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
+ {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, 0, SECT_4K},
+ {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, 0, SECT_4K},
+ {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, 0, SECT_4K},
+ {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, 0, SECT_4K},
#endif
/*
* Note:
@@ -155,12 +157,20 @@ static const struct spi_flash_params spi_flash_params_table[] = {
*/
};
+/* Read commands array */
+static u8 spi_read_cmds_array[] = {
+ CMD_READ_ARRAY_SLOW,
+ CMD_READ_DUAL_OUTPUT_FAST,
+ CMD_READ_DUAL_IO_FAST,
+};
+
static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
u8 *idcode)
{
const struct spi_flash_params *params;
struct spi_flash *flash;
int i;
+ u8 cmd;
u16 jedec = idcode[1] << 8 | idcode[2];
u16 ext_jedec = idcode[3] << 8 | idcode[4];
@@ -222,6 +232,16 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
flash->erase_size = flash->sector_size;
}
+ /* Look for the fastest read cmd */
+ cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
+ if (cmd) {
+ cmd = spi_read_cmds_array[cmd - 1];
+ flash->read_cmd = cmd;
+ } else {
+ /* Go for for default supported read cmd */
+ flash->read_cmd = CMD_READ_ARRAY_FAST;
+ }
+
/* Poll cmd seclection */
flash->poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
diff --git a/include/spi.h b/include/spi.h
index aba7922..31195a3 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -31,6 +31,12 @@
#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
+/* SPI RX operation modes */
+#define SPI_OPM_RX_AS 1 << 0
+#define SPI_OPM_RX_DOUT 1 << 1
+#define SPI_OPM_RX_DIO 1 << 2
+#define SPI_OPM_RX_EXTN SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | SPI_OPM_RX_DIO
+
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
@@ -43,6 +49,7 @@
*
* @bus: ID of the bus that the slave is attached to.
* @cs: ID of the chip select connected to the slave.
+ * @op_mode_rx: SPI RX operation mode.
* @wordlen: Size of SPI word in number of bits
* @max_write_size: If non-zero, the maximum number of bytes which can
* be written@once, excluding command bytes.
@@ -51,6 +58,7 @@
struct spi_slave {
unsigned int bus;
unsigned int cs;
+ u8 op_mode_rx;
unsigned int wordlen;
unsigned int max_write_size;
void *memory_map;
diff --git a/include/spi_flash.h b/include/spi_flash.h
index afc3a58..692e143 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -19,6 +19,14 @@
#include <linux/types.h>
#include <linux/compiler.h>
+/* Enum list - Extended read commands */
+enum spi_read_cmds {
+ ARRAY_SLOW = 1 << 0,
+ DUAL_OUTPUT_FAST = 1 << 1,
+ DUAL_IO_FAST = 1 << 2,
+};
+#define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
+
/**
* struct spi_flash - SPI flash structure
*
@@ -33,6 +41,7 @@
* @bank_curr: Current flash bank
* @poll_cmd: Poll cmd - for flash erase/program
* @erase_cmd: Erase cmd 4K, 32K, 64K
+ * @read_cmd: Read cmd - Array Fast and Extn read
* @memory_map: Address of read-only SPI flash access
* @read: Flash read ops: Read len bytes@offset into buf
* Supported cmds: Fast Array Read
@@ -57,6 +66,7 @@ struct spi_flash {
#endif
u8 poll_cmd;
u8 erase_cmd;
+ u8 read_cmd;
void *memory_map;
int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 02/12] sf: Add quad read/write commands support
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
2014-01-04 15:04 ` [U-Boot] [PATCH v6 01/12] sf: Add extended read commands support Jagannadha Sutradharudu Teki
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
2014-01-04 15:04 ` [U-Boot] [PATCH v6 03/12] sf: ops: Add configuration register writing support Jagannadha Sutradharudu Teki
` (9 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
This patch add quad commands support like
- QUAD_PAGE_PROGRAM => for write program
- QUAD_OUTPUT_FAST ->> for read program
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/sf_internal.h | 2 +
drivers/mtd/spi/sf_ops.c | 2 +-
drivers/mtd/spi/sf_probe.c | 178 ++++++++++++++++++++++--------------------
include/spi.h | 9 ++-
include/spi_flash.h | 11 ++-
5 files changed, 113 insertions(+), 89 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 938a78e..dcc9014 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -28,6 +28,7 @@
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS 0x05
+#define CMD_QUAD_PAGE_PROGRAM 0x32
#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG 0x35
@@ -38,6 +39,7 @@
#define CMD_READ_ARRAY_FAST 0x0b
#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
#define CMD_READ_DUAL_IO_FAST 0xbb
+#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
#define CMD_READ_ID 0x9f
/* Bank addr access commands */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 49ceef0..3d304ce 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -210,7 +210,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
page_size = flash->page_size;
- cmd[0] = CMD_PAGE_PROGRAM;
+ cmd[0] = flash->write_cmd;
for (actual = 0; actual < len; actual += chunk_len) {
#ifdef CONFIG_SPI_FLASH_BAR
ret = spi_flash_bank(flash, offset);
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index c0baac6..3fa7363 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -42,105 +42,105 @@ struct spi_flash_params {
static const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
- {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
- {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
+ {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
+ {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */
- {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
- {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
- {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
+ {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
+ {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
+ {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
- {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
- {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
- {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
- {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
- {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
- {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0, 0},
- {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0, 0},
- {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0, 0},
- {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0, 0},
+ {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
+ {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
+ {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
+ {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
+ {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
+ {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
+ {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0, 0},
+ {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0, 0},
+ {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0, 0},
+ {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0, 0},
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
- {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
- {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
- {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
- {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
- {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0, 0},
- {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0, 0},
- {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0, 0},
- {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0, 0},
- {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0, 0},
- {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_EXTN, 0},
- {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_EXTN, 0},
- {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0, 0},
- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0, 0},
+ {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
+ {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
+ {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
+ {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
+ {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0, 0},
+ {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0, 0},
+ {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0, 0},
+ {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0, 0},
+ {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0, 0},
+ {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0, 0},
+ {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0, 0},
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
- {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
- {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
- {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
- {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
- {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
- {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
- {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
- {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
- {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, 0, SECT_4K},
- {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, 0, SECT_4K},
- {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, 0, SECT_4K},
- {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, 0, SECT_4K},
- {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
- {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
- {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
- {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
+ {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
+ {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
+ {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
+ {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
+ {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
+ {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
+ {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
+ {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
+ {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, 0, SECT_4K},
+ {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, 0, SECT_4K},
+ {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
+ {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
+ {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
+ {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_SST /* SST */
- {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
- {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
- {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
- {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
- {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
- {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
- {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
- {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
- {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
+ {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
+ {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
+ {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
+ {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
+ {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
+ {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
+ {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
+ {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
+ {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
- {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
- {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
- {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
- {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, 0, SECT_4K},
- {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, 0, SECT_4K},
- {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, 0, SECT_4K},
- {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, 0, SECT_4K},
- {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
+ {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
+ {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
+ {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, 0, SECT_4K},
+ {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, 0, SECT_4K},
+ {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, 0, SECT_4K},
+ {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, 0, SECT_4K},
#endif
/*
* Note:
@@ -162,6 +162,7 @@ static u8 spi_read_cmds_array[] = {
CMD_READ_ARRAY_SLOW,
CMD_READ_DUAL_OUTPUT_FAST,
CMD_READ_DUAL_IO_FAST,
+ CMD_READ_QUAD_OUTPUT_FAST,
};
static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
@@ -242,6 +243,13 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
flash->read_cmd = CMD_READ_ARRAY_FAST;
}
+ /* Not require to look for fastest only two write cmds yet */
+ if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
+ flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
+ else
+ /* Go for default supported write cmd */
+ flash->write_cmd = CMD_PAGE_PROGRAM;
+
/* Poll cmd seclection */
flash->poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
diff --git a/include/spi.h b/include/spi.h
index 31195a3..5dd490a 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -31,11 +31,16 @@
#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
+/* SPI TX operation modes */
+#define SPI_OPM_TX_QPP 1 << 0
+
/* SPI RX operation modes */
#define SPI_OPM_RX_AS 1 << 0
#define SPI_OPM_RX_DOUT 1 << 1
#define SPI_OPM_RX_DIO 1 << 2
-#define SPI_OPM_RX_EXTN SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | SPI_OPM_RX_DIO
+#define SPI_OPM_RX_QOF 1 << 3
+#define SPI_OPM_RX_EXTN SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
+ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
@@ -50,6 +55,7 @@
* @bus: ID of the bus that the slave is attached to.
* @cs: ID of the chip select connected to the slave.
* @op_mode_rx: SPI RX operation mode.
+ * @op_mode_tx: SPI TX operation mode.
* @wordlen: Size of SPI word in number of bits
* @max_write_size: If non-zero, the maximum number of bytes which can
* be written@once, excluding command bytes.
@@ -59,6 +65,7 @@ struct spi_slave {
unsigned int bus;
unsigned int cs;
u8 op_mode_rx;
+ u8 op_mode_tx;
unsigned int wordlen;
unsigned int max_write_size;
void *memory_map;
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 692e143..43b4d23 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -19,13 +19,18 @@
#include <linux/types.h>
#include <linux/compiler.h>
-/* Enum list - Extended read commands */
+/* No enum list for write commands only QPP */
+#define WR_QPP 1 << 0
+
+/* Enum list - Full read commands */
enum spi_read_cmds {
ARRAY_SLOW = 1 << 0,
DUAL_OUTPUT_FAST = 1 << 1,
DUAL_IO_FAST = 1 << 2,
+ QUAD_OUTPUT_FAST = 1 << 3,
};
#define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
+#define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST
/**
* struct spi_flash - SPI flash structure
@@ -41,7 +46,8 @@ enum spi_read_cmds {
* @bank_curr: Current flash bank
* @poll_cmd: Poll cmd - for flash erase/program
* @erase_cmd: Erase cmd 4K, 32K, 64K
- * @read_cmd: Read cmd - Array Fast and Extn read
+ * @read_cmd: Read cmd - Array Fast, Extn read and quad read.
+ * @write_cmd: Write cmd - page and quad program.
* @memory_map: Address of read-only SPI flash access
* @read: Flash read ops: Read len bytes@offset into buf
* Supported cmds: Fast Array Read
@@ -67,6 +73,7 @@ struct spi_flash {
u8 poll_cmd;
u8 erase_cmd;
u8 read_cmd;
+ u8 write_cmd;
void *memory_map;
int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 03/12] sf: ops: Add configuration register writing support
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
2014-01-04 15:04 ` [U-Boot] [PATCH v6 01/12] sf: Add extended read commands support Jagannadha Sutradharudu Teki
2014-01-04 15:04 ` [U-Boot] [PATCH v6 02/12] sf: Add quad read/write " Jagannadha Sutradharudu Teki
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
2014-01-04 15:04 ` [U-Boot] [PATCH v6 04/12] sf: Set quad enable bit support Jagannadha Sutradharudu Teki
` (8 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
This patch provides support to program a flash config register.
Configuration register contains the control bits used to configure
the different configurations and security features of a device.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/sf_ops.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 3d304ce..39e06ec 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -38,6 +38,30 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
return 0;
}
+static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
+{
+ u8 data[2];
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_READ_STATUS;
+ ret = spi_flash_read_common(flash, &cmd, 1, &data[0], 1);
+ if (ret < 0) {
+ debug("SF: fail to read status register\n");
+ return ret;
+ }
+
+ cmd = CMD_WRITE_STATUS;
+ data[1] = cr;
+ ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
+ if (ret) {
+ debug("SF: fail to write config register\n");
+ return ret;
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 04/12] sf: Set quad enable bit support
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
` (2 preceding siblings ...)
2014-01-04 15:04 ` [U-Boot] [PATCH v6 03/12] sf: ops: Add configuration register writing support Jagannadha Sutradharudu Teki
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
2014-01-04 15:04 ` [U-Boot] [PATCH v6 05/12] sf: probe: Enable RD_FULL and WR_QPP Jagannadha Sutradharudu Teki
` (7 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
This patch provides support to set the quad enable bit on flash.
quad enable bit needs to set before performing any quad IO
operations on respective SPI flashes.
Currently added set quad enable bit for winbond and spansion flash
devices. stmicro flash doesn't require to set as qeb is volatile.
remaining flash devices support will add in future patches.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/sf_internal.h | 10 ++++++++--
drivers/mtd/spi/sf_ops.c | 26 ++++++++++++++++++++++++++
drivers/mtd/spi/sf_probe.c | 28 ++++++++++++++++++++++++++++
3 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index dcc9014..dca34f7 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -12,6 +12,11 @@
#define SPI_FLASH_16MB_BOUN 0x1000000
+/* CFI Manufacture ID's */
+#define SPI_FLASH_CFI_MFR_SPANSION 0x01
+#define SPI_FLASH_CFI_MFR_STMICRO 0x20
+#define SPI_FLASH_CFI_MFR_WINBOND 0xef
+
/* SECT flags */
#define SECT_4K (1 << 1)
#define SECT_32K (1 << 2)
@@ -52,6 +57,7 @@
/* Common status */
#define STATUS_WIP 0x01
+#define STATUS_QEB_WINSPAN (1 << 1)
#define STATUS_PEC 0x80
/* Flash timeout values */
@@ -93,8 +99,8 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
/* Program the status register */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
-/* Set quad enbale bit */
-int spi_flash_set_qeb(struct spi_flash *flash);
+/* Set quad enbale bit for winbond and spansion flashes */
+int spi_flash_set_qeb_winspan(struct spi_flash *flash);
/* Enable writing on the SPI flash */
static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 39e06ec..827f719 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -38,6 +38,7 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
return 0;
}
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
{
u8 data[2];
@@ -62,6 +63,31 @@ static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
return 0;
}
+int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_READ_CONFIG;
+ ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
+ if (ret < 0) {
+ debug("SF: fail to read config register\n");
+ return ret;
+ }
+
+ if (qeb_status & STATUS_QEB_WINSPAN) {
+ debug("SF: Quad enable bit is already set\n");
+ } else {
+ ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 3fa7363..8b2972c 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -165,6 +165,25 @@ static u8 spi_read_cmds_array[] = {
CMD_READ_QUAD_OUTPUT_FAST,
};
+static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
+{
+ switch (idcode0) {
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+ case SPI_FLASH_CFI_MFR_SPANSION:
+ case SPI_FLASH_CFI_MFR_WINBOND:
+ return spi_flash_set_qeb_winspan(flash);
+#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ case SPI_FLASH_CFI_MFR_STMICRO:
+ debug("SF: QEB is volatile for %02x flash\n", idcode0);
+ return 0;
+#endif
+ default:
+ printf("SF: Need set QEB func for %02x flash\n", idcode0);
+ return -1;
+ }
+}
+
static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
u8 *idcode)
{
@@ -250,6 +269,15 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
/* Go for default supported write cmd */
flash->write_cmd = CMD_PAGE_PROGRAM;
+ /* Set the quad enable bit - only for quad commands */
+ if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
+ (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
+ if (spi_flash_set_qeb(flash, idcode[0])) {
+ debug("SF: Fail to set QEB for %02x\n", idcode[0]);
+ return NULL;
+ }
+ }
+
/* Poll cmd seclection */
flash->poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 05/12] sf: probe: Enable RD_FULL and WR_QPP
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
` (3 preceding siblings ...)
2014-01-04 15:04 ` [U-Boot] [PATCH v6 04/12] sf: Set quad enable bit support Jagannadha Sutradharudu Teki
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
2014-01-04 15:04 ` [U-Boot] [PATCH v6 06/12] sf: Separate the flash params table Jagannadha Sutradharudu Teki
` (6 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
This patch enabled RD_FULL and WR_QPP for supported flashes
in micron, winbond and spansion.
Remaining parts will be add in future patches.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/sf_probe.c | 60 +++++++++++++++++++++++-----------------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 8b2972c..f24bc1b 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -78,15 +78,15 @@ static const struct spi_flash_params spi_flash_params_table[] = {
{"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
{"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
{"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
- {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0, 0},
- {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0, 0},
- {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0, 0},
- {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0, 0},
- {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0, 0},
+ {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
+ {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
+ {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP},
+ {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
{"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP},
{"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
- {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0, 0},
- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0, 0},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, RD_FULL, WR_QPP},
+ {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
{"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
@@ -97,18 +97,18 @@ static const struct spi_flash_params spi_flash_params_table[] = {
{"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
{"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
{"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
- {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, 0, SECT_4K},
- {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, 0, SECT_4K},
- {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, 0, SECT_4K},
- {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, 0, SECT_4K},
- {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
- {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
- {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
- {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
+ {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_SST /* SST */
{"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
@@ -130,17 +130,17 @@ static const struct spi_flash_params spi_flash_params_table[] = {
{"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
{"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
{"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, 0, SECT_4K},
- {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, 0, SECT_4K},
- {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, 0, SECT_4K},
- {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, 0, SECT_4K},
- {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
#endif
/*
* Note:
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 06/12] sf: Separate the flash params table
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
` (4 preceding siblings ...)
2014-01-04 15:04 ` [U-Boot] [PATCH v6 05/12] sf: probe: Enable RD_FULL and WR_QPP Jagannadha Sutradharudu Teki
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
2014-01-04 15:04 ` [U-Boot] [PATCH v6 07/12] sf: Add QUAD_IO_FAST read support Jagannadha Sutradharudu Teki
` (5 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
Moved the flash params table from sf_probe.c and
placed on to sf_params.c, hence flash params file will
alter based on new addons.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/Makefile | 4 +-
drivers/mtd/spi/sf_params.c | 130 +++++++++++++++++++++++++++++++++++++++
drivers/mtd/spi/sf_probe.c | 146 +-------------------------------------------
include/spi_flash.h | 23 +++++++
4 files changed, 158 insertions(+), 145 deletions(-)
create mode 100644 drivers/mtd/spi/sf_params.c
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 26483a2..9e18fb4 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -10,8 +10,8 @@ obj-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
endif
-obj-$(CONFIG_CMD_SF) += sf.o
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o sf_ops.o
+obj-$(CONFIG_CMD_SF) += sf.o
+obj-$(CONFIG_SPI_FLASH) += sf_params.o sf_probe.o sf_ops.o
obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
new file mode 100644
index 0000000..ad101fb
--- /dev/null
+++ b/drivers/mtd/spi/sf_params.c
@@ -0,0 +1,130 @@
+/*
+ * SPI flash Params table
+ *
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi_flash.h>
+
+#include "sf_internal.h"
+
+/* SPI/QSPI flash device params structure */
+const struct spi_flash_params spi_flash_params_table[] = {
+#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
+ {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
+ {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
+ {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_EON /* EON */
+ {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
+ {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
+ {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
+#endif
+#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
+ {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
+ {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
+ {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
+ {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
+ {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
+ {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
+ {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
+ {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0, 0},
+ {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0, 0},
+ {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0, 0},
+ {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0, 0},
+#endif
+#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
+ {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
+ {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
+ {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
+ {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
+ {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
+ {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
+ {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP},
+ {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, RD_FULL, WR_QPP},
+ {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
+#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
+ {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
+ {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
+ {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
+ {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
+ {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
+ {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
+ {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
+ {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
+ {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_SST /* SST */
+ {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
+ {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
+ {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
+ {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
+ {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
+ {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
+ {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
+ {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
+ {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
+#endif
+#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
+ {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
+ {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
+ {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
+ {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
+#endif
+ /*
+ * Note:
+ * Below paired flash devices has similar spi_flash params.
+ * (S25FL129P_64K, S25FL128S_64K)
+ * (W25Q80BL, W25Q80BV)
+ * (W25Q16CL, W25Q16DV)
+ * (W25Q32BV, W25Q32FV_SPI)
+ * (W25Q64CV, W25Q64FV_SPI)
+ * (W25Q128BV, W25Q128FV_SPI)
+ * (W25Q32DW, W25Q32FV_QPI)
+ * (W25Q64DW, W25Q64FV_QPI)
+ * (W25Q128FW, W25Q128FV_QPI)
+ */
+};
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index f24bc1b..d95c8b9 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -19,144 +19,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/**
- * struct spi_flash_params - SPI/QSPI flash device params structure
- *
- * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
- * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
- * @ext_jedec: Device ext_jedec ID
- * @sector_size: Sector size of this device
- * @nr_sectors: No.of sectors on this device
- * @e_rd_cmd: Enum list for read commands
- * @flags: Importent param, for flash specific behaviour
- */
-struct spi_flash_params {
- const char *name;
- u32 jedec;
- u16 ext_jedec;
- u32 sector_size;
- u32 nr_sectors;
- u8 e_rd_cmd;
- u16 flags;
-};
-
-static const struct spi_flash_params spi_flash_params_table[] = {
-#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
- {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
- {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_EON /* EON */
- {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
- {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
- {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
-#endif
-#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
- {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
- {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
- {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
- {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
- {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
- {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0, 0},
- {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0, 0},
- {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0, 0},
- {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0, 0},
-#endif
-#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
- {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
- {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
- {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
- {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
- {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
- {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
- {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
- {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP},
- {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
- {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP},
- {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
- {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, RD_FULL, WR_QPP},
- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
-#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
- {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
- {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
- {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
- {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
- {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
- {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
- {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
- {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
- {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
- {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
- {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
- {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_SST /* SST */
- {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
- {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
- {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
- {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
- {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
- {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
- {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
- {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
- {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
-#endif
-#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
- {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
- {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
- {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
- {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
-#endif
- /*
- * Note:
- * Below paired flash devices has similar spi_flash params.
- * (S25FL129P_64K, S25FL128S_64K)
- * (W25Q80BL, W25Q80BV)
- * (W25Q16CL, W25Q16DV)
- * (W25Q32BV, W25Q32FV_SPI)
- * (W25Q64CV, W25Q64FV_SPI)
- * (W25Q128BV, W25Q128FV_SPI)
- * (W25Q32DW, W25Q32FV_QPI)
- * (W25Q64DW, W25Q64FV_QPI)
- * (W25Q128FW, W25Q128FV_QPI)
- */
-};
-
/* Read commands array */
static u8 spi_read_cmds_array[] = {
CMD_READ_ARRAY_SLOW,
@@ -189,14 +51,12 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
{
const struct spi_flash_params *params;
struct spi_flash *flash;
- int i;
u8 cmd;
u16 jedec = idcode[1] << 8 | idcode[2];
u16 ext_jedec = idcode[3] << 8 | idcode[4];
- /* Get the flash id (jedec = manuf_id + dev_id, ext_jedec) */
- for (i = 0; i < ARRAY_SIZE(spi_flash_params_table); i++) {
- params = &spi_flash_params_table[i];
+ params = spi_flash_params_table;
+ for (; params->name != NULL; params++) {
if ((params->jedec >> 16) == idcode[0]) {
if ((params->jedec & 0xFFFF) == jedec) {
if (params->ext_jedec == 0)
@@ -207,7 +67,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
}
}
- if (i == ARRAY_SIZE(spi_flash_params_table)) {
+ if (!params->name) {
printf("SF: Unsupported flash IDs: ");
printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
idcode[0], jedec, ext_jedec);
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 43b4d23..c3f5a5e 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -33,6 +33,29 @@ enum spi_read_cmds {
#define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST
/**
+ * struct spi_flash_params - SPI/QSPI flash device params structure
+ *
+ * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
+ * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
+ * @ext_jedec: Device ext_jedec ID
+ * @sector_size: Sector size of this device
+ * @nr_sectors: No.of sectors on this device
+ * @e_rd_cmd: Enum list for read commands
+ * @flags: Importent param, for flash specific behaviour
+ */
+struct spi_flash_params {
+ const char *name;
+ u32 jedec;
+ u16 ext_jedec;
+ u32 sector_size;
+ u32 nr_sectors;
+ u8 e_rd_cmd;
+ u16 flags;
+};
+
+extern const struct spi_flash_params spi_flash_params_table[];
+
+/**
* struct spi_flash - SPI flash structure
*
* @spi: SPI slave
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 07/12] sf: Add QUAD_IO_FAST read support
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
` (5 preceding siblings ...)
2014-01-04 15:04 ` [U-Boot] [PATCH v6 06/12] sf: Separate the flash params table Jagannadha Sutradharudu Teki
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
2014-01-04 15:04 ` [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles Jagannadha Sutradharudu Teki
` (4 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
This patch adds support QUAD_IO_FAST read command.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/sf_probe.c | 2 ++
include/spi.h | 4 +++-
include/spi_flash.h | 3 ++-
4 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index dca34f7..7be0292 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -45,6 +45,7 @@
#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
#define CMD_READ_DUAL_IO_FAST 0xbb
#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
+#define CMD_READ_QUAD_IO_FAST 0xeb
#define CMD_READ_ID 0x9f
/* Bank addr access commands */
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index d95c8b9..a049e72 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -25,6 +25,7 @@ static u8 spi_read_cmds_array[] = {
CMD_READ_DUAL_OUTPUT_FAST,
CMD_READ_DUAL_IO_FAST,
CMD_READ_QUAD_OUTPUT_FAST,
+ CMD_READ_QUAD_IO_FAST,
};
static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
@@ -131,6 +132,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
/* Set the quad enable bit - only for quad commands */
if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
+ (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
if (spi_flash_set_qeb(flash, idcode[0])) {
debug("SF: Fail to set QEB for %02x\n", idcode[0]);
diff --git a/include/spi.h b/include/spi.h
index 5dd490a..c8a9d87 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -39,8 +39,10 @@
#define SPI_OPM_RX_DOUT 1 << 1
#define SPI_OPM_RX_DIO 1 << 2
#define SPI_OPM_RX_QOF 1 << 3
+#define SPI_OPM_RX_QIOF 1 << 4
#define SPI_OPM_RX_EXTN SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
- SPI_OPM_RX_DIO | SPI_OPM_RX_QOF
+ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
+ SPI_OPM_RX_QIOF
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
diff --git a/include/spi_flash.h b/include/spi_flash.h
index c3f5a5e..d24e40a 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -28,9 +28,10 @@ enum spi_read_cmds {
DUAL_OUTPUT_FAST = 1 << 1,
DUAL_IO_FAST = 1 << 2,
QUAD_OUTPUT_FAST = 1 << 3,
+ QUAD_IO_FAST = 1 << 4,
};
#define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
-#define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST
+#define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST
/**
* struct spi_flash_params - SPI/QSPI flash device params structure
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
` (6 preceding siblings ...)
2014-01-04 15:04 ` [U-Boot] [PATCH v6 07/12] sf: Add QUAD_IO_FAST read support Jagannadha Sutradharudu Teki
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
2014-01-06 7:04 ` Sourav Poddar
2014-01-04 15:04 ` [U-Boot] [PATCH v6 09/12] sf: Add macronix set QEB support Jagannadha Sutradharudu Teki
` (3 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
Discovered the read dummy_cycles based on the configured
read command.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/sf_internal.h | 2 ++
drivers/mtd/spi/sf_ops.c | 10 ++++++----
drivers/mtd/spi/sf_probe.c | 12 ++++++++++++
include/spi_flash.h | 2 ++
4 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 7be0292..a9f5a81 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,6 +10,8 @@
#ifndef _SF_INTERNAL_H_
#define _SF_INTERNAL_H_
+#define SPI_FLASH_3B_ADDR_LEN 3
+#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN 0x1000000
/* CFI Manufacture ID's */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 827f719..dda75b1 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <malloc.h>
#include <spi.h>
#include <spi_flash.h>
#include <watchdog.h>
@@ -216,7 +217,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
{
u32 erase_size;
- u8 cmd[4];
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
erase_size = flash->erase_size;
@@ -255,7 +256,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
{
unsigned long byte_addr, page_size;
size_t chunk_len, actual;
- u8 cmd[4];
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
page_size = flash->page_size;
@@ -317,7 +318,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5], bank_sel = 0;
+ u8 *cmd, bank_sel = 0;
u32 remain_len, read_len;
int ret = -1;
@@ -335,8 +336,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
return 0;
}
+ cmd = malloc(SPI_FLASH_CMD_LEN + flash->dummy_cycles);
+ memset(cmd, 0, SPI_FLASH_CMD_LEN + flash->dummy_cycles);
cmd[0] = flash->read_cmd;
- cmd[4] = 0x00;
while (len) {
#ifdef CONFIG_SPI_FLASH_BAR
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index a049e72..b070adc 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -140,6 +140,18 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
}
}
+ /* Read dummy cycles */
+ switch (flash->read_cmd) {
+ case CMD_READ_QUAD_IO_FAST:
+ flash->dummy_cycles = 2;
+ break;
+ case CMD_READ_ARRAY_SLOW:
+ flash->dummy_cycles = 0;
+ break;
+ default:
+ flash->dummy_cycles = 1;
+ }
+
/* Poll cmd seclection */
flash->poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
diff --git a/include/spi_flash.h b/include/spi_flash.h
index d24e40a..bdd4141 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -72,6 +72,7 @@ extern const struct spi_flash_params spi_flash_params_table[];
* @erase_cmd: Erase cmd 4K, 32K, 64K
* @read_cmd: Read cmd - Array Fast, Extn read and quad read.
* @write_cmd: Write cmd - page and quad program.
+ * @dummy_cycles: Dummy cycles for read operation.
* @memory_map: Address of read-only SPI flash access
* @read: Flash read ops: Read len bytes at offset into buf
* Supported cmds: Fast Array Read
@@ -98,6 +99,7 @@ struct spi_flash {
u8 erase_cmd;
u8 read_cmd;
u8 write_cmd;
+ u8 dummy_cycles;
void *memory_map;
int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles
2014-01-04 15:04 ` [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles Jagannadha Sutradharudu Teki
@ 2014-01-06 7:04 ` Sourav Poddar
2014-01-06 10:18 ` Jagan Teki
0 siblings, 1 reply; 21+ messages in thread
From: Sourav Poddar @ 2014-01-06 7:04 UTC (permalink / raw)
To: u-boot
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
> Discovered the read dummy_cycles based on the configured
> read command.
>
> Signed-off-by: Jagannadha Sutradharudu Teki<jaganna@xilinx.com>
> ---
> drivers/mtd/spi/sf_internal.h | 2 ++
> drivers/mtd/spi/sf_ops.c | 10 ++++++----
> drivers/mtd/spi/sf_probe.c | 12 ++++++++++++
> include/spi_flash.h | 2 ++
> 4 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
> index 7be0292..a9f5a81 100644
> --- a/drivers/mtd/spi/sf_internal.h
> +++ b/drivers/mtd/spi/sf_internal.h
> @@ -10,6 +10,8 @@
> #ifndef _SF_INTERNAL_H_
> #define _SF_INTERNAL_H_
>
> +#define SPI_FLASH_3B_ADDR_LEN 3
> +#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
> #define SPI_FLASH_16MB_BOUN 0x1000000
>
> /* CFI Manufacture ID's */
> diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
> index 827f719..dda75b1 100644
> --- a/drivers/mtd/spi/sf_ops.c
> +++ b/drivers/mtd/spi/sf_ops.c
> @@ -9,6 +9,7 @@
> */
>
> #include<common.h>
> +#include<malloc.h>
> #include<spi.h>
> #include<spi_flash.h>
> #include<watchdog.h>
> @@ -216,7 +217,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
> int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
> {
> u32 erase_size;
> - u8 cmd[4];
> + u8 cmd[SPI_FLASH_CMD_LEN];
> int ret = -1;
>
> erase_size = flash->erase_size;
> @@ -255,7 +256,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
> {
> unsigned long byte_addr, page_size;
> size_t chunk_len, actual;
> - u8 cmd[4];
> + u8 cmd[SPI_FLASH_CMD_LEN];
> int ret = -1;
>
> page_size = flash->page_size;
> @@ -317,7 +318,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
> int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
> size_t len, void *data)
> {
> - u8 cmd[5], bank_sel = 0;
> + u8 *cmd, bank_sel = 0;
> u32 remain_len, read_len;
> int ret = -1;
>
> @@ -335,8 +336,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
> return 0;
> }
>
> + cmd = malloc(SPI_FLASH_CMD_LEN + flash->dummy_cycles);
> + memset(cmd, 0, SPI_FLASH_CMD_LEN + flash->dummy_cycles);
> cmd[0] = flash->read_cmd;
> - cmd[4] = 0x00;
>
> while (len) {
> #ifdef CONFIG_SPI_FLASH_BAR
> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> index a049e72..b070adc 100644
> --- a/drivers/mtd/spi/sf_probe.c
> +++ b/drivers/mtd/spi/sf_probe.c
> @@ -140,6 +140,18 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
> }
> }
>
> + /* Read dummy cycles */
> + switch (flash->read_cmd) {
> + case CMD_READ_QUAD_IO_FAST:
> + flash->dummy_cycles = 2;
> + break;
> + case CMD_READ_ARRAY_SLOW:
> + flash->dummy_cycles = 0;
> + break;
> + default:
> + flash->dummy_cycles = 1;
> + }
> +
what about dummy cycles for dual i/o(0xbb), it has 4 clock bit dummy
cycles(macronix), so
by your code you keep it to 1(8 bit) dummy cycle. ?
> /* Poll cmd seclection */
> flash->poll_cmd = CMD_READ_STATUS;
> #ifdef CONFIG_SPI_FLASH_STMICRO
> diff --git a/include/spi_flash.h b/include/spi_flash.h
> index d24e40a..bdd4141 100644
> --- a/include/spi_flash.h
> +++ b/include/spi_flash.h
> @@ -72,6 +72,7 @@ extern const struct spi_flash_params spi_flash_params_table[];
> * @erase_cmd: Erase cmd 4K, 32K, 64K
> * @read_cmd: Read cmd - Array Fast, Extn read and quad read.
> * @write_cmd: Write cmd - page and quad program.
> + * @dummy_cycles: Dummy cycles for read operation.
> * @memory_map: Address of read-only SPI flash access
> * @read: Flash read ops: Read len bytes at offset into buf
> * Supported cmds: Fast Array Read
> @@ -98,6 +99,7 @@ struct spi_flash {
> u8 erase_cmd;
> u8 read_cmd;
> u8 write_cmd;
> + u8 dummy_cycles;
>
> void *memory_map;
> int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles
2014-01-06 7:04 ` Sourav Poddar
@ 2014-01-06 10:18 ` Jagan Teki
2014-01-06 10:21 ` Sourav Poddar
0 siblings, 1 reply; 21+ messages in thread
From: Jagan Teki @ 2014-01-06 10:18 UTC (permalink / raw)
To: u-boot
Hi Sourav,
On Mon, Jan 6, 2014 at 12:34 PM, Sourav Poddar <sourav.poddar@ti.com> wrote:
> On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
>>
>> Discovered the read dummy_cycles based on the configured
>> read command.
>>
>> Signed-off-by: Jagannadha Sutradharudu Teki<jaganna@xilinx.com>
>> ---
>> drivers/mtd/spi/sf_internal.h | 2 ++
>> drivers/mtd/spi/sf_ops.c | 10 ++++++----
>> drivers/mtd/spi/sf_probe.c | 12 ++++++++++++
>> include/spi_flash.h | 2 ++
>> 4 files changed, 22 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
>> index 7be0292..a9f5a81 100644
>> --- a/drivers/mtd/spi/sf_internal.h
>> +++ b/drivers/mtd/spi/sf_internal.h
>> @@ -10,6 +10,8 @@
>> #ifndef _SF_INTERNAL_H_
>> #define _SF_INTERNAL_H_
>>
>> +#define SPI_FLASH_3B_ADDR_LEN 3
>> +#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
>> #define SPI_FLASH_16MB_BOUN 0x1000000
>>
>> /* CFI Manufacture ID's */
>> diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
>> index 827f719..dda75b1 100644
>> --- a/drivers/mtd/spi/sf_ops.c
>> +++ b/drivers/mtd/spi/sf_ops.c
>> @@ -9,6 +9,7 @@
>> */
>>
>> #include<common.h>
>> +#include<malloc.h>
>> #include<spi.h>
>> #include<spi_flash.h>
>> #include<watchdog.h>
>> @@ -216,7 +217,7 @@ int spi_flash_write_common(struct spi_flash *flash,
>> const u8 *cmd,
>> int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t
>> len)
>> {
>> u32 erase_size;
>> - u8 cmd[4];
>> + u8 cmd[SPI_FLASH_CMD_LEN];
>> int ret = -1;
>>
>> erase_size = flash->erase_size;
>> @@ -255,7 +256,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash,
>> u32 offset,
>> {
>> unsigned long byte_addr, page_size;
>> size_t chunk_len, actual;
>> - u8 cmd[4];
>> + u8 cmd[SPI_FLASH_CMD_LEN];
>> int ret = -1;
>>
>> page_size = flash->page_size;
>> @@ -317,7 +318,7 @@ int spi_flash_read_common(struct spi_flash *flash,
>> const u8 *cmd,
>> int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
>> size_t len, void *data)
>> {
>> - u8 cmd[5], bank_sel = 0;
>> + u8 *cmd, bank_sel = 0;
>> u32 remain_len, read_len;
>> int ret = -1;
>>
>> @@ -335,8 +336,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash,
>> u32 offset,
>> return 0;
>> }
>>
>> + cmd = malloc(SPI_FLASH_CMD_LEN + flash->dummy_cycles);
>> + memset(cmd, 0, SPI_FLASH_CMD_LEN + flash->dummy_cycles);
>> cmd[0] = flash->read_cmd;
>> - cmd[4] = 0x00;
>>
>> while (len) {
>> #ifdef CONFIG_SPI_FLASH_BAR
>> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
>> index a049e72..b070adc 100644
>> --- a/drivers/mtd/spi/sf_probe.c
>> +++ b/drivers/mtd/spi/sf_probe.c
>> @@ -140,6 +140,18 @@ static struct spi_flash
>> *spi_flash_validate_params(struct spi_slave *spi,
>> }
>> }
>>
>> + /* Read dummy cycles */
>> + switch (flash->read_cmd) {
>> + case CMD_READ_QUAD_IO_FAST:
>> + flash->dummy_cycles = 2;
>> + break;
>> + case CMD_READ_ARRAY_SLOW:
>> + flash->dummy_cycles = 0;
>> + break;
>> + default:
>> + flash->dummy_cycles = 1;
>> + }
>> +
>
> what about dummy cycles for dual i/o(0xbb), it has 4 clock bit dummy
> cycles(macronix), so
> by your code you keep it to 1(8 bit) dummy cycle. ?
Yes- Actually i miss used the names here.
These are dummy_byte_count
Ex: Except fast reads (array, dual and quad fast)
dummy_byte_count = dummy_cycles * no.of lines
dual i/o (4 dummy_cycles) - 4 * 2 = 1 dummy_byte
quad i/o (4 dummy_cycles) - 4 * 4 = 2 dummy_byte
fast, dual and quad fast have 8 dummy_cycles means 1 byte dummy the
reason why I am not including
no.of lines here is irrespective of fast(1 line), dual(2 lines) and
quad(4 lines) only data can travel among the difference lines
but the cmd,inst, dummy can travel only on single line. this can be
opposite in i/o commands.
Hope you understand - I just said based on my knowledge.
I will change the dummy_cycles into dummy_bytes - nevertheless everything same.
--
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles
2014-01-06 10:18 ` Jagan Teki
@ 2014-01-06 10:21 ` Sourav Poddar
2014-01-06 10:30 ` Jagan Teki
0 siblings, 1 reply; 21+ messages in thread
From: Sourav Poddar @ 2014-01-06 10:21 UTC (permalink / raw)
To: u-boot
On Monday 06 January 2014 03:48 PM, Jagan Teki wrote:
> Hi Sourav,
>
> On Mon, Jan 6, 2014 at 12:34 PM, Sourav Poddar<sourav.poddar@ti.com> wrote:
>> On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
>>> Discovered the read dummy_cycles based on the configured
>>> read command.
>>>
>>> Signed-off-by: Jagannadha Sutradharudu Teki<jaganna@xilinx.com>
>>> ---
>>> drivers/mtd/spi/sf_internal.h | 2 ++
>>> drivers/mtd/spi/sf_ops.c | 10 ++++++----
>>> drivers/mtd/spi/sf_probe.c | 12 ++++++++++++
>>> include/spi_flash.h | 2 ++
>>> 4 files changed, 22 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
>>> index 7be0292..a9f5a81 100644
>>> --- a/drivers/mtd/spi/sf_internal.h
>>> +++ b/drivers/mtd/spi/sf_internal.h
>>> @@ -10,6 +10,8 @@
>>> #ifndef _SF_INTERNAL_H_
>>> #define _SF_INTERNAL_H_
>>>
>>> +#define SPI_FLASH_3B_ADDR_LEN 3
>>> +#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
>>> #define SPI_FLASH_16MB_BOUN 0x1000000
>>>
>>> /* CFI Manufacture ID's */
>>> diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
>>> index 827f719..dda75b1 100644
>>> --- a/drivers/mtd/spi/sf_ops.c
>>> +++ b/drivers/mtd/spi/sf_ops.c
>>> @@ -9,6 +9,7 @@
>>> */
>>>
>>> #include<common.h>
>>> +#include<malloc.h>
>>> #include<spi.h>
>>> #include<spi_flash.h>
>>> #include<watchdog.h>
>>> @@ -216,7 +217,7 @@ int spi_flash_write_common(struct spi_flash *flash,
>>> const u8 *cmd,
>>> int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t
>>> len)
>>> {
>>> u32 erase_size;
>>> - u8 cmd[4];
>>> + u8 cmd[SPI_FLASH_CMD_LEN];
>>> int ret = -1;
>>>
>>> erase_size = flash->erase_size;
>>> @@ -255,7 +256,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash,
>>> u32 offset,
>>> {
>>> unsigned long byte_addr, page_size;
>>> size_t chunk_len, actual;
>>> - u8 cmd[4];
>>> + u8 cmd[SPI_FLASH_CMD_LEN];
>>> int ret = -1;
>>>
>>> page_size = flash->page_size;
>>> @@ -317,7 +318,7 @@ int spi_flash_read_common(struct spi_flash *flash,
>>> const u8 *cmd,
>>> int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
>>> size_t len, void *data)
>>> {
>>> - u8 cmd[5], bank_sel = 0;
>>> + u8 *cmd, bank_sel = 0;
>>> u32 remain_len, read_len;
>>> int ret = -1;
>>>
>>> @@ -335,8 +336,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash,
>>> u32 offset,
>>> return 0;
>>> }
>>>
>>> + cmd = malloc(SPI_FLASH_CMD_LEN + flash->dummy_cycles);
>>> + memset(cmd, 0, SPI_FLASH_CMD_LEN + flash->dummy_cycles);
>>> cmd[0] = flash->read_cmd;
>>> - cmd[4] = 0x00;
>>>
>>> while (len) {
>>> #ifdef CONFIG_SPI_FLASH_BAR
>>> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
>>> index a049e72..b070adc 100644
>>> --- a/drivers/mtd/spi/sf_probe.c
>>> +++ b/drivers/mtd/spi/sf_probe.c
>>> @@ -140,6 +140,18 @@ static struct spi_flash
>>> *spi_flash_validate_params(struct spi_slave *spi,
>>> }
>>> }
>>>
>>> + /* Read dummy cycles */
>>> + switch (flash->read_cmd) {
>>> + case CMD_READ_QUAD_IO_FAST:
>>> + flash->dummy_cycles = 2;
>>> + break;
>>> + case CMD_READ_ARRAY_SLOW:
>>> + flash->dummy_cycles = 0;
>>> + break;
>>> + default:
>>> + flash->dummy_cycles = 1;
>>> + }
>>> +
>> what about dummy cycles for dual i/o(0xbb), it has 4 clock bit dummy
>> cycles(macronix), so
>> by your code you keep it to 1(8 bit) dummy cycle. ?
> Yes- Actually i miss used the names here.
> These are dummy_byte_count
>
> Ex: Except fast reads (array, dual and quad fast)
> dummy_byte_count = dummy_cycles * no.of lines
> dual i/o (4 dummy_cycles) - 4 * 2 = 1 dummy_byte
> quad i/o (4 dummy_cycles) - 4 * 4 = 2 dummy_byte
>
is this calculation documented in any of the flash sheet?
> fast, dual and quad fast have 8 dummy_cycles means 1 byte dummy the
> reason why I am not including
> no.of lines here is irrespective of fast(1 line), dual(2 lines) and
> quad(4 lines) only data can travel among the difference lines
> but the cmd,inst, dummy can travel only on single line. this can be
> opposite in i/o commands.
>
> Hope you understand - I just said based on my knowledge.
> I will change the dummy_cycles into dummy_bytes - nevertheless everything same.
>
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles
2014-01-06 10:21 ` Sourav Poddar
@ 2014-01-06 10:30 ` Jagan Teki
2014-01-06 10:35 ` Sourav Poddar
0 siblings, 1 reply; 21+ messages in thread
From: Jagan Teki @ 2014-01-06 10:30 UTC (permalink / raw)
To: u-boot
On Mon, Jan 6, 2014 at 3:51 PM, Sourav Poddar <sourav.poddar@ti.com> wrote:
> On Monday 06 January 2014 03:48 PM, Jagan Teki wrote:
>>
>> Hi Sourav,
>>
>> On Mon, Jan 6, 2014 at 12:34 PM, Sourav Poddar<sourav.poddar@ti.com>
>> wrote:
>>>
>>> On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
>>>>
>>>> Discovered the read dummy_cycles based on the configured
>>>> read command.
>>>>
>>>> Signed-off-by: Jagannadha Sutradharudu Teki<jaganna@xilinx.com>
>>>> ---
>>>> drivers/mtd/spi/sf_internal.h | 2 ++
>>>> drivers/mtd/spi/sf_ops.c | 10 ++++++----
>>>> drivers/mtd/spi/sf_probe.c | 12 ++++++++++++
>>>> include/spi_flash.h | 2 ++
>>>> 4 files changed, 22 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/mtd/spi/sf_internal.h
>>>> b/drivers/mtd/spi/sf_internal.h
>>>> index 7be0292..a9f5a81 100644
>>>> --- a/drivers/mtd/spi/sf_internal.h
>>>> +++ b/drivers/mtd/spi/sf_internal.h
>>>> @@ -10,6 +10,8 @@
>>>> #ifndef _SF_INTERNAL_H_
>>>> #define _SF_INTERNAL_H_
>>>>
>>>> +#define SPI_FLASH_3B_ADDR_LEN 3
>>>> +#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
>>>> #define SPI_FLASH_16MB_BOUN 0x1000000
>>>>
>>>> /* CFI Manufacture ID's */
>>>> diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
>>>> index 827f719..dda75b1 100644
>>>> --- a/drivers/mtd/spi/sf_ops.c
>>>> +++ b/drivers/mtd/spi/sf_ops.c
>>>> @@ -9,6 +9,7 @@
>>>> */
>>>>
>>>> #include<common.h>
>>>> +#include<malloc.h>
>>>> #include<spi.h>
>>>> #include<spi_flash.h>
>>>> #include<watchdog.h>
>>>> @@ -216,7 +217,7 @@ int spi_flash_write_common(struct spi_flash *flash,
>>>> const u8 *cmd,
>>>> int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset,
>>>> size_t
>>>> len)
>>>> {
>>>> u32 erase_size;
>>>> - u8 cmd[4];
>>>> + u8 cmd[SPI_FLASH_CMD_LEN];
>>>> int ret = -1;
>>>>
>>>> erase_size = flash->erase_size;
>>>> @@ -255,7 +256,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash,
>>>> u32 offset,
>>>> {
>>>> unsigned long byte_addr, page_size;
>>>> size_t chunk_len, actual;
>>>> - u8 cmd[4];
>>>> + u8 cmd[SPI_FLASH_CMD_LEN];
>>>> int ret = -1;
>>>>
>>>> page_size = flash->page_size;
>>>> @@ -317,7 +318,7 @@ int spi_flash_read_common(struct spi_flash *flash,
>>>> const u8 *cmd,
>>>> int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
>>>> size_t len, void *data)
>>>> {
>>>> - u8 cmd[5], bank_sel = 0;
>>>> + u8 *cmd, bank_sel = 0;
>>>> u32 remain_len, read_len;
>>>> int ret = -1;
>>>>
>>>> @@ -335,8 +336,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash,
>>>> u32 offset,
>>>> return 0;
>>>> }
>>>>
>>>> + cmd = malloc(SPI_FLASH_CMD_LEN + flash->dummy_cycles);
>>>> + memset(cmd, 0, SPI_FLASH_CMD_LEN + flash->dummy_cycles);
>>>> cmd[0] = flash->read_cmd;
>>>> - cmd[4] = 0x00;
>>>>
>>>> while (len) {
>>>> #ifdef CONFIG_SPI_FLASH_BAR
>>>> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
>>>> index a049e72..b070adc 100644
>>>> --- a/drivers/mtd/spi/sf_probe.c
>>>> +++ b/drivers/mtd/spi/sf_probe.c
>>>> @@ -140,6 +140,18 @@ static struct spi_flash
>>>> *spi_flash_validate_params(struct spi_slave *spi,
>>>> }
>>>> }
>>>>
>>>> + /* Read dummy cycles */
>>>> + switch (flash->read_cmd) {
>>>> + case CMD_READ_QUAD_IO_FAST:
>>>> + flash->dummy_cycles = 2;
>>>> + break;
>>>> + case CMD_READ_ARRAY_SLOW:
>>>> + flash->dummy_cycles = 0;
>>>> + break;
>>>> + default:
>>>> + flash->dummy_cycles = 1;
>>>> + }
>>>> +
>>>
>>> what about dummy cycles for dual i/o(0xbb), it has 4 clock bit dummy
>>> cycles(macronix), so
>>> by your code you keep it to 1(8 bit) dummy cycle. ?
>>
>> Yes- Actually i miss used the names here.
>> These are dummy_byte_count
>>
>> Ex: Except fast reads (array, dual and quad fast)
>> dummy_byte_count = dummy_cycles * no.of lines
>> dual i/o (4 dummy_cycles) - 4 * 2 = 1 dummy_byte
>> quad i/o (4 dummy_cycles) - 4 * 4 = 2 dummy_byte
>>
> is this calculation documented in any of the flash sheet?
I haven't see the exact calculation but ie. how the I/O operation usually works.
quad read - cmd, 3byte_inst, 1 dummy_byte(8 dummy_cycles) goes on
single line and data goes in 4 lines
quad i/o - except cmd(1 lines) remaining goes in 4 lines.
>
>> fast, dual and quad fast have 8 dummy_cycles means 1 byte dummy the
>> reason why I am not including
>> no.of lines here is irrespective of fast(1 line), dual(2 lines) and
>> quad(4 lines) only data can travel among the difference lines
>> but the cmd,inst, dummy can travel only on single line. this can be
>> opposite in i/o commands.
>>
>> Hope you understand - I just said based on my knowledge.
>> I will change the dummy_cycles into dummy_bytes - nevertheless everything
>> same.
>>
>
--
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles
2014-01-06 10:30 ` Jagan Teki
@ 2014-01-06 10:35 ` Sourav Poddar
2014-01-06 10:37 ` Jagan Teki
0 siblings, 1 reply; 21+ messages in thread
From: Sourav Poddar @ 2014-01-06 10:35 UTC (permalink / raw)
To: u-boot
On Monday 06 January 2014 04:00 PM, Jagan Teki wrote:
> On Mon, Jan 6, 2014 at 3:51 PM, Sourav Poddar<sourav.poddar@ti.com> wrote:
>> On Monday 06 January 2014 03:48 PM, Jagan Teki wrote:
>>> Hi Sourav,
>>>
>>> On Mon, Jan 6, 2014 at 12:34 PM, Sourav Poddar<sourav.poddar@ti.com>
>>> wrote:
>>>> On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
>>>>> Discovered the read dummy_cycles based on the configured
>>>>> read command.
>>>>>
>>>>> Signed-off-by: Jagannadha Sutradharudu Teki<jaganna@xilinx.com>
>>>>> ---
>>>>> drivers/mtd/spi/sf_internal.h | 2 ++
>>>>> drivers/mtd/spi/sf_ops.c | 10 ++++++----
>>>>> drivers/mtd/spi/sf_probe.c | 12 ++++++++++++
>>>>> include/spi_flash.h | 2 ++
>>>>> 4 files changed, 22 insertions(+), 4 deletions(-)
>>>>>
>>>>> diff --git a/drivers/mtd/spi/sf_internal.h
>>>>> b/drivers/mtd/spi/sf_internal.h
>>>>> index 7be0292..a9f5a81 100644
>>>>> --- a/drivers/mtd/spi/sf_internal.h
>>>>> +++ b/drivers/mtd/spi/sf_internal.h
>>>>> @@ -10,6 +10,8 @@
>>>>> #ifndef _SF_INTERNAL_H_
>>>>> #define _SF_INTERNAL_H_
>>>>>
>>>>> +#define SPI_FLASH_3B_ADDR_LEN 3
>>>>> +#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
>>>>> #define SPI_FLASH_16MB_BOUN 0x1000000
>>>>>
>>>>> /* CFI Manufacture ID's */
>>>>> diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
>>>>> index 827f719..dda75b1 100644
>>>>> --- a/drivers/mtd/spi/sf_ops.c
>>>>> +++ b/drivers/mtd/spi/sf_ops.c
>>>>> @@ -9,6 +9,7 @@
>>>>> */
>>>>>
>>>>> #include<common.h>
>>>>> +#include<malloc.h>
>>>>> #include<spi.h>
>>>>> #include<spi_flash.h>
>>>>> #include<watchdog.h>
>>>>> @@ -216,7 +217,7 @@ int spi_flash_write_common(struct spi_flash *flash,
>>>>> const u8 *cmd,
>>>>> int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset,
>>>>> size_t
>>>>> len)
>>>>> {
>>>>> u32 erase_size;
>>>>> - u8 cmd[4];
>>>>> + u8 cmd[SPI_FLASH_CMD_LEN];
>>>>> int ret = -1;
>>>>>
>>>>> erase_size = flash->erase_size;
>>>>> @@ -255,7 +256,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash,
>>>>> u32 offset,
>>>>> {
>>>>> unsigned long byte_addr, page_size;
>>>>> size_t chunk_len, actual;
>>>>> - u8 cmd[4];
>>>>> + u8 cmd[SPI_FLASH_CMD_LEN];
>>>>> int ret = -1;
>>>>>
>>>>> page_size = flash->page_size;
>>>>> @@ -317,7 +318,7 @@ int spi_flash_read_common(struct spi_flash *flash,
>>>>> const u8 *cmd,
>>>>> int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
>>>>> size_t len, void *data)
>>>>> {
>>>>> - u8 cmd[5], bank_sel = 0;
>>>>> + u8 *cmd, bank_sel = 0;
>>>>> u32 remain_len, read_len;
>>>>> int ret = -1;
>>>>>
>>>>> @@ -335,8 +336,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash,
>>>>> u32 offset,
>>>>> return 0;
>>>>> }
>>>>>
>>>>> + cmd = malloc(SPI_FLASH_CMD_LEN + flash->dummy_cycles);
>>>>> + memset(cmd, 0, SPI_FLASH_CMD_LEN + flash->dummy_cycles);
>>>>> cmd[0] = flash->read_cmd;
>>>>> - cmd[4] = 0x00;
>>>>>
>>>>> while (len) {
>>>>> #ifdef CONFIG_SPI_FLASH_BAR
>>>>> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
>>>>> index a049e72..b070adc 100644
>>>>> --- a/drivers/mtd/spi/sf_probe.c
>>>>> +++ b/drivers/mtd/spi/sf_probe.c
>>>>> @@ -140,6 +140,18 @@ static struct spi_flash
>>>>> *spi_flash_validate_params(struct spi_slave *spi,
>>>>> }
>>>>> }
>>>>>
>>>>> + /* Read dummy cycles */
>>>>> + switch (flash->read_cmd) {
>>>>> + case CMD_READ_QUAD_IO_FAST:
>>>>> + flash->dummy_cycles = 2;
>>>>> + break;
>>>>> + case CMD_READ_ARRAY_SLOW:
>>>>> + flash->dummy_cycles = 0;
>>>>> + break;
>>>>> + default:
>>>>> + flash->dummy_cycles = 1;
>>>>> + }
>>>>> +
>>>> what about dummy cycles for dual i/o(0xbb), it has 4 clock bit dummy
>>>> cycles(macronix), so
>>>> by your code you keep it to 1(8 bit) dummy cycle. ?
>>> Yes- Actually i miss used the names here.
>>> These are dummy_byte_count
>>>
>>> Ex: Except fast reads (array, dual and quad fast)
>>> dummy_byte_count = dummy_cycles * no.of lines
>>> dual i/o (4 dummy_cycles) - 4 * 2 = 1 dummy_byte
>>> quad i/o (4 dummy_cycles) - 4 * 4 = 2 dummy_byte
>>>
>> is this calculation documented in any of the flash sheet?
> I haven't see the exact calculation but ie. how the I/O operation usually works.
> quad read - cmd, 3byte_inst, 1 dummy_byte(8 dummy_cycles) goes on
> single line and data goes in 4 lines
> quad i/o - except cmd(1 lines) remaining goes in 4 lines.
>
Ok, got the point.
>>> fast, dual and quad fast have 8 dummy_cycles means 1 byte dummy the
>>> reason why I am not including
>>> no.of lines here is irrespective of fast(1 line), dual(2 lines) and
>>> quad(4 lines) only data can travel among the difference lines
>>> but the cmd,inst, dummy can travel only on single line. this can be
>>> opposite in i/o commands.
>>>
>>> Hope you understand - I just said based on my knowledge.
>>> I will change the dummy_cycles into dummy_bytes - nevertheless everything
>>> same.
>>>
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles
2014-01-06 10:35 ` Sourav Poddar
@ 2014-01-06 10:37 ` Jagan Teki
0 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2014-01-06 10:37 UTC (permalink / raw)
To: u-boot
On Mon, Jan 6, 2014 at 4:05 PM, Sourav Poddar <sourav.poddar@ti.com> wrote:
> On Monday 06 January 2014 04:00 PM, Jagan Teki wrote:
>>
>> On Mon, Jan 6, 2014 at 3:51 PM, Sourav Poddar<sourav.poddar@ti.com>
>> wrote:
>>>
>>> On Monday 06 January 2014 03:48 PM, Jagan Teki wrote:
>>>>
>>>> Hi Sourav,
>>>>
>>>> On Mon, Jan 6, 2014 at 12:34 PM, Sourav Poddar<sourav.poddar@ti.com>
>>>> wrote:
>>>>>
>>>>> On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki
>>>>> wrote:
>>>>>>
>>>>>> Discovered the read dummy_cycles based on the configured
>>>>>> read command.
>>>>>>
>>>>>> Signed-off-by: Jagannadha Sutradharudu Teki<jaganna@xilinx.com>
>>>>>> ---
>>>>>> drivers/mtd/spi/sf_internal.h | 2 ++
>>>>>> drivers/mtd/spi/sf_ops.c | 10 ++++++----
>>>>>> drivers/mtd/spi/sf_probe.c | 12 ++++++++++++
>>>>>> include/spi_flash.h | 2 ++
>>>>>> 4 files changed, 22 insertions(+), 4 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/mtd/spi/sf_internal.h
>>>>>> b/drivers/mtd/spi/sf_internal.h
>>>>>> index 7be0292..a9f5a81 100644
>>>>>> --- a/drivers/mtd/spi/sf_internal.h
>>>>>> +++ b/drivers/mtd/spi/sf_internal.h
>>>>>> @@ -10,6 +10,8 @@
>>>>>> #ifndef _SF_INTERNAL_H_
>>>>>> #define _SF_INTERNAL_H_
>>>>>>
>>>>>> +#define SPI_FLASH_3B_ADDR_LEN 3
>>>>>> +#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
>>>>>> #define SPI_FLASH_16MB_BOUN 0x1000000
>>>>>>
>>>>>> /* CFI Manufacture ID's */
>>>>>> diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
>>>>>> index 827f719..dda75b1 100644
>>>>>> --- a/drivers/mtd/spi/sf_ops.c
>>>>>> +++ b/drivers/mtd/spi/sf_ops.c
>>>>>> @@ -9,6 +9,7 @@
>>>>>> */
>>>>>>
>>>>>> #include<common.h>
>>>>>> +#include<malloc.h>
>>>>>> #include<spi.h>
>>>>>> #include<spi_flash.h>
>>>>>> #include<watchdog.h>
>>>>>> @@ -216,7 +217,7 @@ int spi_flash_write_common(struct spi_flash
>>>>>> *flash,
>>>>>> const u8 *cmd,
>>>>>> int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset,
>>>>>> size_t
>>>>>> len)
>>>>>> {
>>>>>> u32 erase_size;
>>>>>> - u8 cmd[4];
>>>>>> + u8 cmd[SPI_FLASH_CMD_LEN];
>>>>>> int ret = -1;
>>>>>>
>>>>>> erase_size = flash->erase_size;
>>>>>> @@ -255,7 +256,7 @@ int spi_flash_cmd_write_ops(struct spi_flash
>>>>>> *flash,
>>>>>> u32 offset,
>>>>>> {
>>>>>> unsigned long byte_addr, page_size;
>>>>>> size_t chunk_len, actual;
>>>>>> - u8 cmd[4];
>>>>>> + u8 cmd[SPI_FLASH_CMD_LEN];
>>>>>> int ret = -1;
>>>>>>
>>>>>> page_size = flash->page_size;
>>>>>> @@ -317,7 +318,7 @@ int spi_flash_read_common(struct spi_flash *flash,
>>>>>> const u8 *cmd,
>>>>>> int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
>>>>>> size_t len, void *data)
>>>>>> {
>>>>>> - u8 cmd[5], bank_sel = 0;
>>>>>> + u8 *cmd, bank_sel = 0;
>>>>>> u32 remain_len, read_len;
>>>>>> int ret = -1;
>>>>>>
>>>>>> @@ -335,8 +336,9 @@ int spi_flash_cmd_read_ops(struct spi_flash
>>>>>> *flash,
>>>>>> u32 offset,
>>>>>> return 0;
>>>>>> }
>>>>>>
>>>>>> + cmd = malloc(SPI_FLASH_CMD_LEN + flash->dummy_cycles);
>>>>>> + memset(cmd, 0, SPI_FLASH_CMD_LEN + flash->dummy_cycles);
>>>>>> cmd[0] = flash->read_cmd;
>>>>>> - cmd[4] = 0x00;
>>>>>>
>>>>>> while (len) {
>>>>>> #ifdef CONFIG_SPI_FLASH_BAR
>>>>>> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
>>>>>> index a049e72..b070adc 100644
>>>>>> --- a/drivers/mtd/spi/sf_probe.c
>>>>>> +++ b/drivers/mtd/spi/sf_probe.c
>>>>>> @@ -140,6 +140,18 @@ static struct spi_flash
>>>>>> *spi_flash_validate_params(struct spi_slave *spi,
>>>>>> }
>>>>>> }
>>>>>>
>>>>>> + /* Read dummy cycles */
>>>>>> + switch (flash->read_cmd) {
>>>>>> + case CMD_READ_QUAD_IO_FAST:
>>>>>> + flash->dummy_cycles = 2;
>>>>>> + break;
>>>>>> + case CMD_READ_ARRAY_SLOW:
>>>>>> + flash->dummy_cycles = 0;
>>>>>> + break;
>>>>>> + default:
>>>>>> + flash->dummy_cycles = 1;
>>>>>> + }
>>>>>> +
>>>>>
>>>>> what about dummy cycles for dual i/o(0xbb), it has 4 clock bit dummy
>>>>> cycles(macronix), so
>>>>> by your code you keep it to 1(8 bit) dummy cycle. ?
>>>>
>>>> Yes- Actually i miss used the names here.
>>>> These are dummy_byte_count
>>>>
>>>> Ex: Except fast reads (array, dual and quad fast)
>>>> dummy_byte_count = dummy_cycles * no.of lines
>>>> dual i/o (4 dummy_cycles) - 4 * 2 = 1 dummy_byte
>>>> quad i/o (4 dummy_cycles) - 4 * 4 = 2 dummy_byte
>>>>
>>> is this calculation documented in any of the flash sheet?
>>
>> I haven't see the exact calculation but ie. how the I/O operation usually
>> works.
>> quad read - cmd, 3byte_inst, 1 dummy_byte(8 dummy_cycles) goes on
>> single line and data goes in 4 lines
>> quad i/o - except cmd(1 lines) remaining goes in 4 lines.
>>
> Ok, got the point.
Anyway I can add the comments on to of this code.
Thanks for notice.
>
>>>> fast, dual and quad fast have 8 dummy_cycles means 1 byte dummy the
>>>> reason why I am not including
>>>> no.of lines here is irrespective of fast(1 line), dual(2 lines) and
>>>> quad(4 lines) only data can travel among the difference lines
>>>> but the cmd,inst, dummy can travel only on single line. this can be
>>>> opposite in i/o commands.
>>>>
>>>> Hope you understand - I just said based on my knowledge.
>>>> I will change the dummy_cycles into dummy_bytes - nevertheless
>>>> everything
>>>> same.
>>>>
>
--
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v6 09/12] sf: Add macronix set QEB support
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
` (7 preceding siblings ...)
2014-01-04 15:04 ` [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles Jagannadha Sutradharudu Teki
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
2014-01-04 15:04 ` [U-Boot] [PATCH v6 10/12] sf: probe: Enable macronix quad read/write cmds support Jagannadha Sutradharudu Teki
` (2 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
This patch adds set QEB support for macronix flash devices
which are trying to program/read quad operations.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/sf_internal.h | 5 +++++
drivers/mtd/spi/sf_ops.c | 26 ++++++++++++++++++++++++++
drivers/mtd/spi/sf_probe.c | 4 ++++
3 files changed, 35 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index a9f5a81..c69b53d 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -17,6 +17,7 @@
/* CFI Manufacture ID's */
#define SPI_FLASH_CFI_MFR_SPANSION 0x01
#define SPI_FLASH_CFI_MFR_STMICRO 0x20
+#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
#define SPI_FLASH_CFI_MFR_WINBOND 0xef
/* SECT flags */
@@ -61,6 +62,7 @@
/* Common status */
#define STATUS_WIP 0x01
#define STATUS_QEB_WINSPAN (1 << 1)
+#define STATUS_QEB_MXIC (1 << 6)
#define STATUS_PEC 0x80
/* Flash timeout values */
@@ -102,6 +104,9 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
/* Program the status register */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+/* Set quad enbale bit for macronix flashes */
+int spi_flash_set_qeb_mxic(struct spi_flash *flash);
+
/* Set quad enbale bit for winbond and spansion flashes */
int spi_flash_set_qeb_winspan(struct spi_flash *flash);
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index dda75b1..9681042 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -39,6 +39,32 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
return 0;
}
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_READ_STATUS;
+ ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
+ if (ret < 0) {
+ debug("SF: fail to read status register\n");
+ return ret;
+ }
+
+ if (qeb_status & STATUS_QEB_MXIC) {
+ debug("SF: Quad enable bit is already set\n");
+ } else {
+ ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
{
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index b070adc..cbde350 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -31,6 +31,10 @@ static u8 spi_read_cmds_array[] = {
static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
{
switch (idcode0) {
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+ case SPI_FLASH_CFI_MFR_MACRONIX:
+ return spi_flash_set_qeb_mxic(flash);
+#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
case SPI_FLASH_CFI_MFR_SPANSION:
case SPI_FLASH_CFI_MFR_WINBOND:
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 10/12] sf: probe: Enable macronix quad read/write cmds support
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
` (8 preceding siblings ...)
2014-01-04 15:04 ` [U-Boot] [PATCH v6 09/12] sf: Add macronix set QEB support Jagannadha Sutradharudu Teki
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
2014-01-04 15:04 ` [U-Boot] [PATCH v6 11/12] sf: Divide flash register ops from QEB code Jagannadha Sutradharudu Teki
2014-01-04 15:04 ` [U-Boot] [PATCH v6 12/12] sf: Code cleanups Jagannadha Sutradharudu Teki
11 siblings, 0 replies; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
Added macronix flash quad read/write commands support and
it's up to the respective controller driver usecase to
configure the respective commands by defining SPI RX/TX
operation modes from include/spi.h on the driver.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/sf_params.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index ad101fb..4cdb4c2 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -40,10 +40,10 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
{"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
{"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
- {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0, 0},
- {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0, 0},
- {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0, 0},
- {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0, 0},
+ {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP},
+ {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
{"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 11/12] sf: Divide flash register ops from QEB code
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
` (9 preceding siblings ...)
2014-01-04 15:04 ` [U-Boot] [PATCH v6 10/12] sf: probe: Enable macronix quad read/write cmds support Jagannadha Sutradharudu Teki
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
2014-01-06 7:09 ` Sourav Poddar
2014-01-04 15:04 ` [U-Boot] [PATCH v6 12/12] sf: Code cleanups Jagannadha Sutradharudu Teki
11 siblings, 1 reply; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_op
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/sf_internal.h | 11 ++++---
drivers/mtd/spi/sf_ops.c | 75 +++++++++++++++----------------------------
drivers/mtd/spi/sf_probe.c | 44 +++++++++++++++++++++++++
3 files changed, 77 insertions(+), 53 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index c69b53d..c77961f 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -101,14 +101,17 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
/* Flash erase(sectors) operation, support all possible erase commands */
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
+/* Read the status register */
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
+
/* Program the status register */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
-/* Set quad enbale bit for macronix flashes */
-int spi_flash_set_qeb_mxic(struct spi_flash *flash);
+/* Read the config register */
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
-/* Set quad enbale bit for winbond and spansion flashes */
-int spi_flash_set_qeb_winspan(struct spi_flash *flash);
+/* Program the config register */
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
/* Enable writing on the SPI flash */
static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 9681042..658294c 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -24,94 +24,71 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
cmd[3] = addr >> 0;
}
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
{
- u8 cmd;
int ret;
+ u8 cmd;
- cmd = CMD_WRITE_STATUS;
- ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
+ cmd = CMD_READ_STATUS;
+ ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
if (ret < 0) {
- debug("SF: fail to write status register\n");
+ debug("SF: fail to read status register\n");
return ret;
}
return 0;
}
-#ifdef CONFIG_SPI_FLASH_MACRONIX
-int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
{
- u8 qeb_status;
u8 cmd;
int ret;
- cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
+ cmd = CMD_WRITE_STATUS;
+ ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
if (ret < 0) {
- debug("SF: fail to read status register\n");
+ debug("SF: fail to write status register\n");
return ret;
}
- if (qeb_status & STATUS_QEB_MXIC) {
- debug("SF: Quad enable bit is already set\n");
- } else {
- ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
- if (ret < 0)
- return ret;
- }
-
- return ret;
+ return 0;
}
-#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
-static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
{
- u8 data[2];
- u8 cmd;
int ret;
+ u8 cmd;
- cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash, &cmd, 1, &data[0], 1);
+ cmd = CMD_READ_CONFIG;
+ ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
if (ret < 0) {
- debug("SF: fail to read status register\n");
- return ret;
- }
-
- cmd = CMD_WRITE_STATUS;
- data[1] = cr;
- ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
- if (ret) {
- debug("SF: fail to write config register\n");
+ debug("SF: fail to read config register\n");
return ret;
}
return 0;
}
-int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
{
- u8 qeb_status;
+ u8 data[2];
u8 cmd;
int ret;
- cmd = CMD_READ_CONFIG;
- ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
- if (ret < 0) {
- debug("SF: fail to read config register\n");
+ ret = spi_flash_cmd_read_status(flash, &data[0]);
+ if (ret < 0)
return ret;
- }
- if (qeb_status & STATUS_QEB_WINSPAN) {
- debug("SF: Quad enable bit is already set\n");
- } else {
- ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
- if (ret < 0)
- return ret;
+ cmd = CMD_WRITE_STATUS;
+ data[1] = wc;
+ ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
+ if (ret) {
+ debug("SF: fail to write config register\n");
+ return ret;
}
- return ret;
+ return 0;
}
#endif
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index cbde350..8715b7c 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -28,6 +28,50 @@ static u8 spi_read_cmds_array[] = {
CMD_READ_QUAD_IO_FAST,
};
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ int ret;
+
+ ret = spi_flash_cmd_read_status(flash, &qeb_status);
+ if (ret < 0)
+ return ret;
+
+ if (qeb_status & STATUS_QEB_MXIC) {
+ debug("SF: mxic: QEB is already set\n");
+ } else {
+ ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ int ret;
+
+ ret = spi_flash_cmd_read_config(flash, &qeb_status);
+ if (ret < 0)
+ return ret;
+
+ if (qeb_status & STATUS_QEB_WINSPAN) {
+ debug("SF: winspan: QEB is already set\n");
+ } else {
+ ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
{
switch (idcode0) {
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 11/12] sf: Divide flash register ops from QEB code
2014-01-04 15:04 ` [U-Boot] [PATCH v6 11/12] sf: Divide flash register ops from QEB code Jagannadha Sutradharudu Teki
@ 2014-01-06 7:09 ` Sourav Poddar
2014-01-06 7:40 ` Jagan Teki
0 siblings, 1 reply; 21+ messages in thread
From: Sourav Poddar @ 2014-01-06 7:09 UTC (permalink / raw)
To: u-boot
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
> QEB code comprises of couple of flash register read/write operations,
> this patch moved flash register operations on to sf_op
>
> Signed-off-by: Jagannadha Sutradharudu Teki<jaganna@xilinx.com>
> ---
> drivers/mtd/spi/sf_internal.h | 11 ++++---
> drivers/mtd/spi/sf_ops.c | 75 +++++++++++++++----------------------------
> drivers/mtd/spi/sf_probe.c | 44 +++++++++++++++++++++++++
> 3 files changed, 77 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
> index c69b53d..c77961f 100644
> --- a/drivers/mtd/spi/sf_internal.h
> +++ b/drivers/mtd/spi/sf_internal.h
> @@ -101,14 +101,17 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
> /* Flash erase(sectors) operation, support all possible erase commands */
> int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
>
> +/* Read the status register */
> +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
> +
> /* Program the status register */
> int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
>
> -/* Set quad enbale bit for macronix flashes */
> -int spi_flash_set_qeb_mxic(struct spi_flash *flash);
> +/* Read the config register */
> +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
>
> -/* Set quad enbale bit for winbond and spansion flashes */
> -int spi_flash_set_qeb_winspan(struct spi_flash *flash);
> +/* Program the config register */
> +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
>
> /* Enable writing on the SPI flash */
> static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
> diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
> index 9681042..658294c 100644
> --- a/drivers/mtd/spi/sf_ops.c
> +++ b/drivers/mtd/spi/sf_ops.c
> @@ -24,94 +24,71 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
> cmd[3] = addr>> 0;
> }
>
> -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
> +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
> {
> - u8 cmd;
> int ret;
> + u8 cmd;
>
> - cmd = CMD_WRITE_STATUS;
> - ret = spi_flash_write_common(flash,&cmd, 1,&sr, 1);
> + cmd = CMD_READ_STATUS;
> + ret = spi_flash_read_common(flash,&cmd, 1, rs, 1);
> if (ret< 0) {
> - debug("SF: fail to write status register\n");
> + debug("SF: fail to read status register\n");
> return ret;
> }
>
> return 0;
> }
>
> -#ifdef CONFIG_SPI_FLASH_MACRONIX
> -int spi_flash_set_qeb_mxic(struct spi_flash *flash)
> +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
> {
> - u8 qeb_status;
> u8 cmd;
> int ret;
>
> - cmd = CMD_READ_STATUS;
> - ret = spi_flash_read_common(flash,&cmd, 1,&qeb_status, 1);
> + cmd = CMD_WRITE_STATUS;
> + ret = spi_flash_write_common(flash,&cmd, 1,&sr, 1);
> if (ret< 0) {
> - debug("SF: fail to read status register\n");
> + debug("SF: fail to write status register\n");
> return ret;
> }
>
> - if (qeb_status& STATUS_QEB_MXIC) {
> - debug("SF: Quad enable bit is already set\n");
> - } else {
> - ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
> - if (ret< 0)
> - return ret;
> - }
> -
> - return ret;
> + return 0;
> }
> -#endif
>
> #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
> -static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
> +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
> {
> - u8 data[2];
> - u8 cmd;
> int ret;
> + u8 cmd;
>
> - cmd = CMD_READ_STATUS;
> - ret = spi_flash_read_common(flash,&cmd, 1,&data[0], 1);
> + cmd = CMD_READ_CONFIG;
> + ret = spi_flash_read_common(flash,&cmd, 1, rc, 1);
> if (ret< 0) {
> - debug("SF: fail to read status register\n");
> - return ret;
> - }
> -
> - cmd = CMD_WRITE_STATUS;
> - data[1] = cr;
> - ret = spi_flash_write_common(flash,&cmd, 1,&data, 2);
> - if (ret) {
> - debug("SF: fail to write config register\n");
> + debug("SF: fail to read config register\n");
> return ret;
> }
>
> return 0;
> }
>
> -int spi_flash_set_qeb_winspan(struct spi_flash *flash)
> +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
> {
> - u8 qeb_status;
> + u8 data[2];
> u8 cmd;
> int ret;
>
> - cmd = CMD_READ_CONFIG;
> - ret = spi_flash_read_common(flash,&cmd, 1,&qeb_status, 1);
> - if (ret< 0) {
> - debug("SF: fail to read config register\n");
> + ret = spi_flash_cmd_read_status(flash,&data[0]);
> + if (ret< 0)
> return ret;
> - }
>
> - if (qeb_status& STATUS_QEB_WINSPAN) {
> - debug("SF: Quad enable bit is already set\n");
> - } else {
> - ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
> - if (ret< 0)
> - return ret;
> + cmd = CMD_WRITE_STATUS;
> + data[1] = wc;
> + ret = spi_flash_write_common(flash,&cmd, 1,&data, 2);
> + if (ret) {
> + debug("SF: fail to write config register\n");
> + return ret;
> }
>
> - return ret;
> + return 0;
> }
> #endif
>
> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> index cbde350..8715b7c 100644
> --- a/drivers/mtd/spi/sf_probe.c
> +++ b/drivers/mtd/spi/sf_probe.c
> @@ -28,6 +28,50 @@ static u8 spi_read_cmds_array[] = {
> CMD_READ_QUAD_IO_FAST,
> };
>
> +#ifdef CONFIG_SPI_FLASH_MACRONIX
> +static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
> +{
> + u8 qeb_status;
> + int ret;
> +
> + ret = spi_flash_cmd_read_status(flash,&qeb_status);
> + if (ret< 0)
> + return ret;
> +
> + if (qeb_status& STATUS_QEB_MXIC) {
> + debug("SF: mxic: QEB is already set\n");
> + } else {
> + ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
> + if (ret< 0)
> + return ret;
> + }
> +
> + return ret;
> +}
> +#endif
> +
> +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
> +static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
> +{
> + u8 qeb_status;
> + int ret;
> +
> + ret = spi_flash_cmd_read_config(flash,&qeb_status);
> + if (ret< 0)
> + return ret;
> +
> + if (qeb_status& STATUS_QEB_WINSPAN) {
> + debug("SF: winspan: QEB is already set\n");
> + } else {
> + ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
> + if (ret< 0)
> + return ret;
> + }
> +
> + return ret;
> +}
> +#endif
> +
This looks to be the generic function used to set quad mode for both
spansion and
winbond flashes? If its the case, function name should be more generic
and without a
_winbond appended to it. Same goes with the other macros used in the
function.
> static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
> {
> switch (idcode0) {
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 11/12] sf: Divide flash register ops from QEB code
2014-01-06 7:09 ` Sourav Poddar
@ 2014-01-06 7:40 ` Jagan Teki
2014-01-06 8:22 ` Sourav Poddar
0 siblings, 1 reply; 21+ messages in thread
From: Jagan Teki @ 2014-01-06 7:40 UTC (permalink / raw)
To: u-boot
On Mon, Jan 6, 2014 at 12:39 PM, Sourav Poddar <sourav.poddar@ti.com> wrote:
> On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
>>
>> QEB code comprises of couple of flash register read/write operations,
>> this patch moved flash register operations on to sf_op
>>
>> Signed-off-by: Jagannadha Sutradharudu Teki<jaganna@xilinx.com>
>> ---
>> drivers/mtd/spi/sf_internal.h | 11 ++++---
>> drivers/mtd/spi/sf_ops.c | 75
>> +++++++++++++++----------------------------
>> drivers/mtd/spi/sf_probe.c | 44 +++++++++++++++++++++++++
>> 3 files changed, 77 insertions(+), 53 deletions(-)
>>
>> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
>> index c69b53d..c77961f 100644
>> --- a/drivers/mtd/spi/sf_internal.h
>> +++ b/drivers/mtd/spi/sf_internal.h
>> @@ -101,14 +101,17 @@ int spi_flash_cmd_write(struct spi_slave *spi, const
>> u8 *cmd, size_t cmd_len,
>> /* Flash erase(sectors) operation, support all possible erase commands
>> */
>> int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t
>> len);
>>
>> +/* Read the status register */
>> +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
>> +
>> /* Program the status register */
>> int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
>>
>> -/* Set quad enbale bit for macronix flashes */
>> -int spi_flash_set_qeb_mxic(struct spi_flash *flash);
>> +/* Read the config register */
>> +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
>>
>> -/* Set quad enbale bit for winbond and spansion flashes */
>> -int spi_flash_set_qeb_winspan(struct spi_flash *flash);
>> +/* Program the config register */
>> +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
>>
>> /* Enable writing on the SPI flash */
>> static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
>> diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
>> index 9681042..658294c 100644
>> --- a/drivers/mtd/spi/sf_ops.c
>> +++ b/drivers/mtd/spi/sf_ops.c
>> @@ -24,94 +24,71 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
>> cmd[3] = addr>> 0;
>> }
>>
>> -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
>> +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
>> {
>> - u8 cmd;
>> int ret;
>> + u8 cmd;
>>
>> - cmd = CMD_WRITE_STATUS;
>> - ret = spi_flash_write_common(flash,&cmd, 1,&sr, 1);
>> + cmd = CMD_READ_STATUS;
>> + ret = spi_flash_read_common(flash,&cmd, 1, rs, 1);
>>
>> if (ret< 0) {
>> - debug("SF: fail to write status register\n");
>> + debug("SF: fail to read status register\n");
>> return ret;
>> }
>>
>> return 0;
>> }
>>
>> -#ifdef CONFIG_SPI_FLASH_MACRONIX
>> -int spi_flash_set_qeb_mxic(struct spi_flash *flash)
>> +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
>> {
>> - u8 qeb_status;
>> u8 cmd;
>> int ret;
>>
>> - cmd = CMD_READ_STATUS;
>> - ret = spi_flash_read_common(flash,&cmd, 1,&qeb_status, 1);
>> + cmd = CMD_WRITE_STATUS;
>> + ret = spi_flash_write_common(flash,&cmd, 1,&sr, 1);
>>
>> if (ret< 0) {
>> - debug("SF: fail to read status register\n");
>> + debug("SF: fail to write status register\n");
>> return ret;
>> }
>>
>> - if (qeb_status& STATUS_QEB_MXIC) {
>>
>> - debug("SF: Quad enable bit is already set\n");
>> - } else {
>> - ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
>> - if (ret< 0)
>> - return ret;
>> - }
>> -
>> - return ret;
>> + return 0;
>> }
>> -#endif
>>
>> #if defined(CONFIG_SPI_FLASH_SPANSION) ||
>> defined(CONFIG_SPI_FLASH_WINBOND)
>> -static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
>> +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
>> {
>> - u8 data[2];
>> - u8 cmd;
>> int ret;
>> + u8 cmd;
>>
>> - cmd = CMD_READ_STATUS;
>> - ret = spi_flash_read_common(flash,&cmd, 1,&data[0], 1);
>> + cmd = CMD_READ_CONFIG;
>> + ret = spi_flash_read_common(flash,&cmd, 1, rc, 1);
>>
>> if (ret< 0) {
>> - debug("SF: fail to read status register\n");
>> - return ret;
>> - }
>> -
>> - cmd = CMD_WRITE_STATUS;
>> - data[1] = cr;
>> - ret = spi_flash_write_common(flash,&cmd, 1,&data, 2);
>>
>> - if (ret) {
>> - debug("SF: fail to write config register\n");
>> + debug("SF: fail to read config register\n");
>> return ret;
>> }
>>
>> return 0;
>> }
>>
>> -int spi_flash_set_qeb_winspan(struct spi_flash *flash)
>> +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
>> {
>> - u8 qeb_status;
>> + u8 data[2];
>> u8 cmd;
>> int ret;
>>
>> - cmd = CMD_READ_CONFIG;
>> - ret = spi_flash_read_common(flash,&cmd, 1,&qeb_status, 1);
>>
>> - if (ret< 0) {
>> - debug("SF: fail to read config register\n");
>> + ret = spi_flash_cmd_read_status(flash,&data[0]);
>>
>> + if (ret< 0)
>> return ret;
>> - }
>>
>> - if (qeb_status& STATUS_QEB_WINSPAN) {
>>
>> - debug("SF: Quad enable bit is already set\n");
>> - } else {
>> - ret = spi_flash_cmd_write_config(flash,
>> STATUS_QEB_WINSPAN);
>> - if (ret< 0)
>> - return ret;
>> + cmd = CMD_WRITE_STATUS;
>> + data[1] = wc;
>> + ret = spi_flash_write_common(flash,&cmd, 1,&data, 2);
>>
>> + if (ret) {
>> + debug("SF: fail to write config register\n");
>> + return ret;
>> }
>>
>> - return ret;
>> + return 0;
>> }
>> #endif
>>
>> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
>> index cbde350..8715b7c 100644
>> --- a/drivers/mtd/spi/sf_probe.c
>> +++ b/drivers/mtd/spi/sf_probe.c
>> @@ -28,6 +28,50 @@ static u8 spi_read_cmds_array[] = {
>> CMD_READ_QUAD_IO_FAST,
>> };
>>
>> +#ifdef CONFIG_SPI_FLASH_MACRONIX
>> +static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
>> +{
>> + u8 qeb_status;
>> + int ret;
>> +
>> + ret = spi_flash_cmd_read_status(flash,&qeb_status);
>> + if (ret< 0)
>> + return ret;
>> +
>> + if (qeb_status& STATUS_QEB_MXIC) {
>>
>> + debug("SF: mxic: QEB is already set\n");
>> + } else {
>> + ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
>> + if (ret< 0)
>> + return ret;
>> + }
>> +
>> + return ret;
>> +}
>> +#endif
>> +
>> +#if defined(CONFIG_SPI_FLASH_SPANSION) ||
>> defined(CONFIG_SPI_FLASH_WINBOND)
>> +static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
>> +{
>> + u8 qeb_status;
>> + int ret;
>> +
>> + ret = spi_flash_cmd_read_config(flash,&qeb_status);
>> + if (ret< 0)
>> + return ret;
>> +
>> + if (qeb_status& STATUS_QEB_WINSPAN) {
>>
>> + debug("SF: winspan: QEB is already set\n");
>> + } else {
>> + ret = spi_flash_cmd_write_config(flash,
>> STATUS_QEB_WINSPAN);
>> + if (ret< 0)
>> + return ret;
>> + }
>> +
>> + return ret;
>> +}
>> +#endif
>> +
>
>
> This looks to be the generic function used to set quad mode for both
> spansion and
> winbond flashes? If its the case, function name should be more generic and
> without a
> _winbond appended to it. Same goes with the other macros used in the
> function.
Thats what I reflected on the name right - as this code specific to
winbond and spansion -
I named as *_winspan() and macro looks the same *_WINSPAN
Any comments?
--
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v6 11/12] sf: Divide flash register ops from QEB code
2014-01-06 7:40 ` Jagan Teki
@ 2014-01-06 8:22 ` Sourav Poddar
0 siblings, 0 replies; 21+ messages in thread
From: Sourav Poddar @ 2014-01-06 8:22 UTC (permalink / raw)
To: u-boot
On Monday 06 January 2014 01:10 PM, Jagan Teki wrote:
> On Mon, Jan 6, 2014 at 12:39 PM, Sourav Poddar<sourav.poddar@ti.com> wrote:
>> On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
>>> QEB code comprises of couple of flash register read/write operations,
>>> this patch moved flash register operations on to sf_op
>>>
>>> Signed-off-by: Jagannadha Sutradharudu Teki<jaganna@xilinx.com>
>>> ---
>>> drivers/mtd/spi/sf_internal.h | 11 ++++---
>>> drivers/mtd/spi/sf_ops.c | 75
>>> +++++++++++++++----------------------------
>>> drivers/mtd/spi/sf_probe.c | 44 +++++++++++++++++++++++++
>>> 3 files changed, 77 insertions(+), 53 deletions(-)
>>>
>>> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
>>> index c69b53d..c77961f 100644
>>> --- a/drivers/mtd/spi/sf_internal.h
>>> +++ b/drivers/mtd/spi/sf_internal.h
>>> @@ -101,14 +101,17 @@ int spi_flash_cmd_write(struct spi_slave *spi, const
>>> u8 *cmd, size_t cmd_len,
>>> /* Flash erase(sectors) operation, support all possible erase commands
>>> */
>>> int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t
>>> len);
>>>
>>> +/* Read the status register */
>>> +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
>>> +
>>> /* Program the status register */
>>> int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
>>>
>>> -/* Set quad enbale bit for macronix flashes */
>>> -int spi_flash_set_qeb_mxic(struct spi_flash *flash);
>>> +/* Read the config register */
>>> +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
>>>
>>> -/* Set quad enbale bit for winbond and spansion flashes */
>>> -int spi_flash_set_qeb_winspan(struct spi_flash *flash);
>>> +/* Program the config register */
>>> +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
>>>
>>> /* Enable writing on the SPI flash */
>>> static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
>>> diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
>>> index 9681042..658294c 100644
>>> --- a/drivers/mtd/spi/sf_ops.c
>>> +++ b/drivers/mtd/spi/sf_ops.c
>>> @@ -24,94 +24,71 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
>>> cmd[3] = addr>> 0;
>>> }
>>>
>>> -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
>>> +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
>>> {
>>> - u8 cmd;
>>> int ret;
>>> + u8 cmd;
>>>
>>> - cmd = CMD_WRITE_STATUS;
>>> - ret = spi_flash_write_common(flash,&cmd, 1,&sr, 1);
>>> + cmd = CMD_READ_STATUS;
>>> + ret = spi_flash_read_common(flash,&cmd, 1, rs, 1);
>>>
>>> if (ret< 0) {
>>> - debug("SF: fail to write status register\n");
>>> + debug("SF: fail to read status register\n");
>>> return ret;
>>> }
>>>
>>> return 0;
>>> }
>>>
>>> -#ifdef CONFIG_SPI_FLASH_MACRONIX
>>> -int spi_flash_set_qeb_mxic(struct spi_flash *flash)
>>> +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
>>> {
>>> - u8 qeb_status;
>>> u8 cmd;
>>> int ret;
>>>
>>> - cmd = CMD_READ_STATUS;
>>> - ret = spi_flash_read_common(flash,&cmd, 1,&qeb_status, 1);
>>> + cmd = CMD_WRITE_STATUS;
>>> + ret = spi_flash_write_common(flash,&cmd, 1,&sr, 1);
>>>
>>> if (ret< 0) {
>>> - debug("SF: fail to read status register\n");
>>> + debug("SF: fail to write status register\n");
>>> return ret;
>>> }
>>>
>>> - if (qeb_status& STATUS_QEB_MXIC) {
>>>
>>> - debug("SF: Quad enable bit is already set\n");
>>> - } else {
>>> - ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
>>> - if (ret< 0)
>>> - return ret;
>>> - }
>>> -
>>> - return ret;
>>> + return 0;
>>> }
>>> -#endif
>>>
>>> #if defined(CONFIG_SPI_FLASH_SPANSION) ||
>>> defined(CONFIG_SPI_FLASH_WINBOND)
>>> -static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
>>> +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
>>> {
>>> - u8 data[2];
>>> - u8 cmd;
>>> int ret;
>>> + u8 cmd;
>>>
>>> - cmd = CMD_READ_STATUS;
>>> - ret = spi_flash_read_common(flash,&cmd, 1,&data[0], 1);
>>> + cmd = CMD_READ_CONFIG;
>>> + ret = spi_flash_read_common(flash,&cmd, 1, rc, 1);
>>>
>>> if (ret< 0) {
>>> - debug("SF: fail to read status register\n");
>>> - return ret;
>>> - }
>>> -
>>> - cmd = CMD_WRITE_STATUS;
>>> - data[1] = cr;
>>> - ret = spi_flash_write_common(flash,&cmd, 1,&data, 2);
>>>
>>> - if (ret) {
>>> - debug("SF: fail to write config register\n");
>>> + debug("SF: fail to read config register\n");
>>> return ret;
>>> }
>>>
>>> return 0;
>>> }
>>>
>>> -int spi_flash_set_qeb_winspan(struct spi_flash *flash)
>>> +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
>>> {
>>> - u8 qeb_status;
>>> + u8 data[2];
>>> u8 cmd;
>>> int ret;
>>>
>>> - cmd = CMD_READ_CONFIG;
>>> - ret = spi_flash_read_common(flash,&cmd, 1,&qeb_status, 1);
>>>
>>> - if (ret< 0) {
>>> - debug("SF: fail to read config register\n");
>>> + ret = spi_flash_cmd_read_status(flash,&data[0]);
>>>
>>> + if (ret< 0)
>>> return ret;
>>> - }
>>>
>>> - if (qeb_status& STATUS_QEB_WINSPAN) {
>>>
>>> - debug("SF: Quad enable bit is already set\n");
>>> - } else {
>>> - ret = spi_flash_cmd_write_config(flash,
>>> STATUS_QEB_WINSPAN);
>>> - if (ret< 0)
>>> - return ret;
>>> + cmd = CMD_WRITE_STATUS;
>>> + data[1] = wc;
>>> + ret = spi_flash_write_common(flash,&cmd, 1,&data, 2);
>>>
>>> + if (ret) {
>>> + debug("SF: fail to write config register\n");
>>> + return ret;
>>> }
>>>
>>> - return ret;
>>> + return 0;
>>> }
>>> #endif
>>>
>>> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
>>> index cbde350..8715b7c 100644
>>> --- a/drivers/mtd/spi/sf_probe.c
>>> +++ b/drivers/mtd/spi/sf_probe.c
>>> @@ -28,6 +28,50 @@ static u8 spi_read_cmds_array[] = {
>>> CMD_READ_QUAD_IO_FAST,
>>> };
>>>
>>> +#ifdef CONFIG_SPI_FLASH_MACRONIX
>>> +static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
>>> +{
>>> + u8 qeb_status;
>>> + int ret;
>>> +
>>> + ret = spi_flash_cmd_read_status(flash,&qeb_status);
>>> + if (ret< 0)
>>> + return ret;
>>> +
>>> + if (qeb_status& STATUS_QEB_MXIC) {
>>>
>>> + debug("SF: mxic: QEB is already set\n");
>>> + } else {
>>> + ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
>>> + if (ret< 0)
>>> + return ret;
>>> + }
>>> +
>>> + return ret;
>>> +}
>>> +#endif
>>> +
>>> +#if defined(CONFIG_SPI_FLASH_SPANSION) ||
>>> defined(CONFIG_SPI_FLASH_WINBOND)
>>> +static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
>>> +{
>>> + u8 qeb_status;
>>> + int ret;
>>> +
>>> + ret = spi_flash_cmd_read_config(flash,&qeb_status);
>>> + if (ret< 0)
>>> + return ret;
>>> +
>>> + if (qeb_status& STATUS_QEB_WINSPAN) {
>>>
>>> + debug("SF: winspan: QEB is already set\n");
>>> + } else {
>>> + ret = spi_flash_cmd_write_config(flash,
>>> STATUS_QEB_WINSPAN);
>>> + if (ret< 0)
>>> + return ret;
>>> + }
>>> +
>>> + return ret;
>>> +}
>>> +#endif
>>> +
>>
>> This looks to be the generic function used to set quad mode for both
>> spansion and
>> winbond flashes? If its the case, function name should be more generic and
>> without a
>> _winbond appended to it. Same goes with the other macros used in the
>> function.
> Thats what I reflected on the name right - as this code specific to
> winbond and spansion -
> I named as *_winspan() and macro looks the same *_WINSPAN
>
> Any comments?
>
Ok, yes, overlooked its winspan. its fine then.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v6 12/12] sf: Code cleanups
[not found] <1388847888-19474-1-git-send-email-jaganna@xilinx.com>
` (10 preceding siblings ...)
2014-01-04 15:04 ` [U-Boot] [PATCH v6 11/12] sf: Divide flash register ops from QEB code Jagannadha Sutradharudu Teki
@ 2014-01-04 15:04 ` Jagannadha Sutradharudu Teki
11 siblings, 0 replies; 21+ messages in thread
From: Jagannadha Sutradharudu Teki @ 2014-01-04 15:04 UTC (permalink / raw)
To: u-boot
- comment typo's
- func args have a proper names
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
drivers/mtd/spi/sf_internal.h | 6 +++---
drivers/mtd/spi/sf_ops.c | 4 ++--
drivers/mtd/spi/sf_probe.c | 4 ++--
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index c77961f..da69549 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -60,10 +60,10 @@
#endif
/* Common status */
-#define STATUS_WIP 0x01
+#define STATUS_WIP (1 << 0)
#define STATUS_QEB_WINSPAN (1 << 1)
#define STATUS_QEB_MXIC (1 << 6)
-#define STATUS_PEC 0x80
+#define STATUS_PEC (1 << 7)
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
@@ -105,7 +105,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
/* Program the status register */
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
/* Read the config register */
int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 658294c..7a499d5 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -39,13 +39,13 @@ int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
return 0;
}
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws)
{
u8 cmd;
int ret;
cmd = CMD_WRITE_STATUS;
- ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
+ ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
if (ret < 0) {
debug("SF: fail to write status register\n");
return ret;
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 8715b7c..98fc271 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -167,7 +167,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
cmd = spi_read_cmds_array[cmd - 1];
flash->read_cmd = cmd;
} else {
- /* Go for for default supported read cmd */
+ /* Go for default supported read cmd */
flash->read_cmd = CMD_READ_ARRAY_FAST;
}
@@ -200,7 +200,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
flash->dummy_cycles = 1;
}
- /* Poll cmd seclection */
+ /* Poll cmd selection */
flash->poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
if (params->flags & E_FSR)
--
1.8.3
^ permalink raw reply related [flat|nested] 21+ messages in thread