* [U-Boot] [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
@ 2014-01-06 21:31 Anson Huang
2014-01-07 10:15 ` Fabio Estevam
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Anson Huang @ 2014-01-06 21:31 UTC (permalink / raw)
To: u-boot
For low freq boot mode(ARM boot up with 396MHz), ROM
will not set AHB clock to 132MHz, and the reset value of
AHB divider is incorrect which will lead to wrong AHB
rate, need to correct it. To enable low freq boot mode,
need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL
SabreSD board and i.MX6SL EVK board.
Signed-off-by: Anson Huang <b20788@freescale.com>
---
arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a390296..edf3139 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -131,10 +131,30 @@ static void imx_set_wdog_powerdown(bool enable)
writew(enable, &wdog2->wmcr);
}
+static void set_ahb_rate(u32 val)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg, div;
+
+ div = get_periph_clk() / val - 1;
+ reg = readl(&mxc_ccm->cbcdr);
+
+ writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
+ (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
+}
+
int arch_cpu_init(void)
{
init_aips();
+ /*
+ * When low freq boot is enabled, ROM will not set AHB
+ * freq, so we need to ensure AHB freq is 132MHz in such
+ * scenario.
+ */
+ if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+ set_ahb_rate(132000000);
+
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [U-Boot] [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
2014-01-06 21:31 [U-Boot] [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode Anson Huang
@ 2014-01-07 10:15 ` Fabio Estevam
2014-01-07 10:37 ` Hui.Liu at freescale.com
2014-01-07 13:51 ` Stefano Babic
2 siblings, 0 replies; 5+ messages in thread
From: Fabio Estevam @ 2014-01-07 10:15 UTC (permalink / raw)
To: u-boot
Hi Anson,
On Mon, Jan 6, 2014 at 7:31 PM, Anson Huang <b20788@freescale.com> wrote:
> int arch_cpu_init(void)
> {
> init_aips();
>
> + /*
> + * When low freq boot is enabled, ROM will not set AHB
> + * freq, so we need to ensure AHB freq is 132MHz in such
> + * scenario.
> + */
> + if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
> + set_ahb_rate(132000000);
> +
> set_vddsoc(1200); /* Set VDDSOC to 1.2V */
Your patch looks good, but please rebase it against the latest
u-boot-imx tree because I sent a recent patch that sets vddsoc to
1.175V.
After doing so, you can add:
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 5+ messages in thread* [U-Boot] [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
2014-01-06 21:31 [U-Boot] [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode Anson Huang
2014-01-07 10:15 ` Fabio Estevam
@ 2014-01-07 10:37 ` Hui.Liu at freescale.com
2014-01-07 13:51 ` Stefano Babic
2 siblings, 0 replies; 5+ messages in thread
From: Hui.Liu at freescale.com @ 2014-01-07 10:37 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Anson Huang [mailto:b20788 at freescale.com]
> Sent: Tuesday, January 07, 2014 5:32 AM
> To: sbabic at denx.de; eric.nelson at boundarydevices.com;
> troy.kisky at boundarydevices.com; Estevam Fabio-R49496; Liu Hui-R64343
> Cc: u-boot at lists.denx.de
> Subject: [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
>
> For low freq boot mode(ARM boot up with 396MHz), ROM will not set AHB
> clock to 132MHz, and the reset value of AHB divider is incorrect which
> will lead to wrong AHB rate, need to correct it. To enable low freq boot
> mode, need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL SabreSD board
> and i.MX6SL EVK board.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
Looks good to me.
Acked-by: Jason Liu <r64343@freescale.com>
> ---
> arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index a390296..edf3139 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -131,10 +131,30 @@ static void imx_set_wdog_powerdown(bool enable)
> writew(enable, &wdog2->wmcr);
> }
>
> +static void set_ahb_rate(u32 val)
> +{
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> + u32 reg, div;
> +
> + div = get_periph_clk() / val - 1;
> + reg = readl(&mxc_ccm->cbcdr);
> +
> + writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
> + (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); }
> +
> int arch_cpu_init(void)
> {
> init_aips();
>
> + /*
> + * When low freq boot is enabled, ROM will not set AHB
> + * freq, so we need to ensure AHB freq is 132MHz in such
> + * scenario.
> + */
> + if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
> + set_ahb_rate(132000000);
> +
> set_vddsoc(1200); /* Set VDDSOC to 1.2V */
>
> imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register
> */
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 5+ messages in thread* [U-Boot] [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
2014-01-06 21:31 [U-Boot] [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode Anson Huang
2014-01-07 10:15 ` Fabio Estevam
2014-01-07 10:37 ` Hui.Liu at freescale.com
@ 2014-01-07 13:51 ` Stefano Babic
2 siblings, 0 replies; 5+ messages in thread
From: Stefano Babic @ 2014-01-07 13:51 UTC (permalink / raw)
To: u-boot
Hi Anson,
On 06/01/2014 22:31, Anson Huang wrote:
> For low freq boot mode(ARM boot up with 396MHz), ROM
> will not set AHB clock to 132MHz, and the reset value of
> AHB divider is incorrect which will lead to wrong AHB
> rate, need to correct it. To enable low freq boot mode,
> need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL
> SabreSD board and i.MX6SL EVK board.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> ---
> arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index a390296..edf3139 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -131,10 +131,30 @@ static void imx_set_wdog_powerdown(bool enable)
> writew(enable, &wdog2->wmcr);
> }
>
> +static void set_ahb_rate(u32 val)
> +{
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> + u32 reg, div;
> +
> + div = get_periph_clk() / val - 1;
> + reg = readl(&mxc_ccm->cbcdr);
> +
> + writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
> + (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
> +}
> +
> int arch_cpu_init(void)
> {
> init_aips();
>
> + /*
> + * When low freq boot is enabled, ROM will not set AHB
> + * freq, so we need to ensure AHB freq is 132MHz in such
> + * scenario.
> + */
> + if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
> + set_ahb_rate(132000000);
> +
Are we sure that mxc_get_clock() returns *exactly* 396000000 ?
As far as I see, this depends firstly from MXC_HCLK, that can be
configurable with CONFIG_SYS_MX6_HCLK and could have a different value
from the default 24000000. I do not know if there is cases where
CONFIG_SYS_MX6_HCLK is useful, no boards at the moment are setting it.
But the test requires that the computed frequency is exactly 396Mhz. Is
this reliable or should we simply test if frequency is lower of a
defined threshold ?
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
@ 2014-01-06 21:38 Anson Huang
0 siblings, 0 replies; 5+ messages in thread
From: Anson Huang @ 2014-01-06 21:38 UTC (permalink / raw)
To: u-boot
For low freq boot mode(ARM boot up with 396MHz), ROM
will not set AHB clock to 132MHz, and the reset value of
AHB divider is incorrect which will lead to wrong AHB
rate, need to correct it. To enable low freq boot mode,
need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL
SabreSD board and i.MX6SL EVK board.
Signed-off-by: Anson Huang <b20788@freescale.com>
---
arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a390296..edf3139 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -131,10 +131,30 @@ static void imx_set_wdog_powerdown(bool enable)
writew(enable, &wdog2->wmcr);
}
+static void set_ahb_rate(u32 val)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg, div;
+
+ div = get_periph_clk() / val - 1;
+ reg = readl(&mxc_ccm->cbcdr);
+
+ writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
+ (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
+}
+
int arch_cpu_init(void)
{
init_aips();
+ /*
+ * When low freq boot is enabled, ROM will not set AHB
+ * freq, so we need to ensure AHB freq is 132MHz in such
+ * scenario.
+ */
+ if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+ set_ahb_rate(132000000);
+
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2014-01-07 13:51 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-01-06 21:31 [U-Boot] [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode Anson Huang
2014-01-07 10:15 ` Fabio Estevam
2014-01-07 10:37 ` Hui.Liu at freescale.com
2014-01-07 13:51 ` Stefano Babic
-- strict thread matches above, loose matches on Subject: below --
2014-01-06 21:38 Anson Huang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox